4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY 524,288 only Singl
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MX29F040
4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY
524,288 only Single power supply operation 5.0V only operation read, erase program operation Fast access time: 55/70/90/120ns power consumption 30mA maximum active current(5MHz) typical standby current Command register architecture Byte Programming (7us typical) Sector Erase equal sectors 64K-Byte each Auto Erase (chip sector) Auto Program Automatically erase combination sectors with Erase Suspend capability. Automatically program verify data specified address Erase suspend/Erase Resume Suspends erase operation read data from, program data another sector that being erased, then resumes erase. Status Reply Data polling Toggle detection program erase cycle completion. Sector protect/unprotect only system system. Sector protection Hardware method disable combination sectors from program erase operations 100,000 minimum erase/program cycles Latch-up protected 100mA from VCC+1V write inhibit equal less than 3.2V Package type: 32-pin PLCC, TSOP PDIP Compatibility with JEDEC standard Pinout software compatible with single-power supply Flash years data retention
GENERAL DESCRIPTION
MX29F040 4-mega Flash memory organized 512K bytes bits. MXIC's Flash memories offer most cost-effective reliable read/write non-volatile random access memory. MX29F040 packaged 32-pin PLCC, TSOP, PDIP. designed reprogrammed erased system standard EPROM programmers. standard MX29F040 offers access time fast 55ns, allowing operation high-speed microprocessors without wait states. eliminate contention, MX29F040 separate chip enable (CE) output enable controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure programming. MX29F040 uses command register manage this functionality. command register allows 100% level control inputs fixed power supply levels during erase programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase program cycles. MXIC cell designed optimize erase program mechanisms. addition, combination advanced tunnel oxide processing internal electric fields erase programming operations produces reliable cycling. MX29F040 uses 5.0V±10% supply perform High Reliability Erase auto Program/Erase algorithms. highest degree latch-up protection achieved with MXIC's proprietary non-epi process. Latch-up protection proved stresses milliamps address data from
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
CONFIGURATIONS
PDIP
PLCC
MX29F040
MX29F040
TSOP (Standard Type) (8mm 20mm)
MX29F040
DESCRIPTION
SYMBOL A0~A18 Q0~Q7 NAME Address Input Data Input/Output Chip Enable Input Write Enable Input Output Enable Input Ground +5.0V single power supply
SECTOR STRUCTURE
MX29F040 SECTOR ADDRESS TABLE Sector Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh
Note:All sectors Kbytes size.
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REV. 1.6, AUG. 2001
MX29F040
BLOCK DIAGRAM
WRITE CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE
X-DECODER
MX29F040 FLASH ARRAY ARRAY
STATE REGISTER
ADDRESS LATCH A0-A18 BUFFER
SENSE AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE COMMAND DATA DECODER
DATA COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q7
BUFFER
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REV. 1.6, AUG. 2001
MX29F040
AUTOMATIC PROGRAMMING
MX29F040 byte programmable using Automatic Programming algorithm. Automatic Programming algorithm makes external system need have time sequence verify data programmed. typical chip programming time room temperature MX29F040 less than seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires user write commands command register using standard microprocessor write timings. device will automatically pre-program verify entire array. Then device automatically times erase pulse width, provides erase verification, counts number sequences. status toggling between consecutive read cycles provides feedback user status programming operation. Register contents serve inputs internal statemachine which controls erase programming circuitry. During write cycles, command register internally latches address data needed programming erase operations. During system write cycle, addresses latched falling edge whichever happeds later, data latched rising edge whichever happeds first. MXIC's Flash technology combines years EPROM experience produce highest levels quality, reliability, cost effectiveness. MX29F040 electrically erases bits simultaneously using FowlerNordheim tunneling. bytes programmed using EPROM programming mechanism electron injection. During program cycle, state-machine will control program sequences command register will respond command set. During Sector Erase cycle, command register will only respond Erase Suspend command. After Erase Suspend completed, device stays read mode. After state machine completed task, will allow command register respond full command set.
AUTOMATIC CHIP ERASE
entire chip bulk erased using erase pulses according MXIC's Automatic Chip Erase algorithm. Typical erasure room temperature accomplished less than second. Automatic Erase algorithm automatically programs entire array prior electrical erase. timing verification electrical erase controlled internally within device.
AUTOMATIC SECTOR ERASE
MX29F040 sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors array erased erase cycle. Automatic Sector Erase algorithm automatically programs specified sector(s) prior electrical erase. timing verification electrical erase controlled internally within device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require user only write program set-up commands (including unlock write cycle A0H) program command (program data address). device automatically times programming pulse width, provides program verification, counts number sequences. status similar DATA polling status toggling between consecutive read cycles, provide feedback user status programming operation.
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REV. 1.6, AUG. 2001
MX29F040
TABLE1. SOFTWARE COMMAND DEFINITIONS
First Command Reset Read Read Silicon Sector Protect Verify Porgram Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Unlock sector protect/unprotect Cycle Cycle Addr XXXH 555H 555H 555H 555H 555H XXXH XXXH 555H Data 2AAH 555H 555H 2AAH 555H 2AAH 2AAH 2AAH 2AAH 2AAH 555H 555H 555H 555H 555H 555H 2AAH 2AAH 555H 555H (SA)X Second Cycle Addr Data Third Cycle Addr Data Fourth Cycle Addr Data Fifth Cycle Addr Data Sixth Cycle Addr Data
Note: Address Device identifier; A1=0, manufacture code,A1=0, device code A2-A18=Do care. (Refer table Data Device identifier manufacture code, device code. RA=Address memory location read. RD=Data read location 2.PA Address memory location programmed. Data programmed location Address sector erased. 3.The system should generate following address patterns: 555H 2AAH Address A10~A0 Address A11~A18=X=Don't care address commands except Program Address (PA) Sector Address (SA). Write Sequence initiated with A11~A18 either state. 4.For Sector Protect Verify Operation read data 01H, means sector been protected.If read data 00H,it means sector still being protected.
COMMAND DEFINITIONS
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset device read mode. Table defines valid register command sequences. Note that Erase Suspend (B0H) Erase Resume (30H) commands valid only while Sector Erase operation progress. Either reset command sequences will reset device(when applicable).
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REV. 1.6, AUG. 2001
MX29F040
TABLE MX29F040 OPERATION
Mode Read Silicon Manfacturer Code(1) Read Silicon Device Code(1) Read Standby Output Disable Write Sector Protect with system(6) Chip Unprotect with system(6) Verify Sector Protect with system Sector Protect without system Chip Unprotect without system Verify Sector Protect/Unprotect without system Reset HIGH Code(5) VID(2) Code(5) VID(2) VID(2) VID(2) VID(2) DOUT HIGH HIGH DIN(3) VID(2) Pins VID(2)
NOTES: Manufacturer device codes also accessed command register write sequence. Refer Table Silicon-ID-Read high voltage, 11.5V 12.5V. Refer Table valid Data-In during write operation. VIH. Code=00H means unprotected. Code=01H means protected. A18~A16=Sector address sector protect. Refer sector protect/unprotect algorithm waveform. Must issue "unlock sector protect/unprotect" command before "sector protect/unprotect without system" command. "verify sector protect/unprotect without sysytem" only following "Sector protect/unprotect without system" command.
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MX29F040
READ/RESET COMMAND
read reset operation initiated writing read/reset command sequence into command register. Microprocessor read cycles retrieve array data. device remains enabled reads until command register contents altered. program-fail erase-fail happen, write will reset device abort operation. valid command must then written place device desired state.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
Chip erase six-bus cycle operation. There "unlock" write cycles. These followed writing "set-up" command 80H. more "unlock" write cycles then followed chip erase command 10H. Automatic Chip Erase does require device entirely pre-programmed prior executing Automatic Chip Erase. Upon executing Automatic Chip Erase, device will automatically program verify entire memory all-zero data pattern. When device automatically verified contain all-zero pattern, self-timed chip erase verify begin. erase verify operations completed when data which time device returns Read mode. system required provide control timing during these operations. When using Automatic Chip Erase algorithm, note that erase automatically terminates when adequate erase margin been achieved memory array(no erase verification command required). Erase operation unsuccessful, data "1"(see Table indicating erase operation exceed internal timing limit. automatic erase begins rising edge last whichever happeds first pulse command sequence terminates when data data stops toggling consecutive read cycles, which time device returns Read mode.
SILICON-ID-READ COMMAND
Flash memories intended applications where local alters memory contents. such, manufacturer device codes must accessible while device resides target system. PROM programmers typically access signature codes raising high voltage. However, multiplexing high voltage onto address lines generally desired system design practice. MX29F040 contains Silicon-ID-Read operation supplement traditional PROM programming methodology. operation initiated writing read silicon command sequence into command register. Following command write, read cycle with A1=VIL,A0=VIL retrieves manufacturer code C2H. read cycle with A1=VIL, A0=VIH returns device code MX29F040.
TABLE EXPANDED SILICON CODE
Pins Manufacture code Device code MX29F040 Sector Protection Verification
Code(Hex) 01H(Protected) 00H(Unprotected)
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REV. 1.6, AUG. 2001
MX29F040
SECTOR ERASE COMMANDS
Automatic Sector Erase does require device entirely pre-programmed prior executing Automatic Set-up Sector Erase command Automatic Sector Erase command. Upon executing Automatic Sector Erase command, device will automatically program verify sector(s) memory all-zero data pattern. system required provide control timing during these operations. When sector(s) automatically verified contain all-zero pattern, self-timed sector erase verify begin. erase verify operations complete when data data stops toggling consecutive read cycles, which time device returns Read mode. system required provide control timing during these operations. When using Automatic Sector Erase algorithm, note that erase automatically terminates when adequate erase margin been achieved memory array erase verification command required). Sector erase six-bus cycle operation. There "unlock" write cycles. These followed writing set-up command 80H. more "unlock" write cycles then followed sector erase command 30H. sector address latched falling edge whichever happeds later, while command(data) latched rising edge whichever happeds first. Sector addresses selected loaded into internal register sixth falling edge whichever happeds later. Each successive sector load cycle started falling edge whichever happeds later must begin within 30us from rising edge preceding whichever happeds first. Otherwise, loading period ends internal auto sector erase cycle starts. (Monitor determine sector erase timer window still open, section Sector Erase Timer.) command other than Sector Erase(30H) Erase Suspend(B0H) during time-out period resets device read mode.
Table Write Operation Status
Status Note1 Byte Program Auto Program Algorithm Auto Erase Algorithm Erase Suspend Read Progress Erase Suspended Mode (Erase Suspended Sector) Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program Byte Program Auto Program Algorithm Exceeded Auto Erase Algorithm Time Limits Erase Suspend Program Toggle Toggle Toggle Toggle Toggle Toggle Data Toggle Toggle Toggle Data Data Data Data Note2 Toggle Toggle Toggle
Note:
require valid address when reading status information. Refer appropriate subsection further details. switches when Auto Program Auto Erase operation exceeded maximum timing limits. "Q5:Exceeded Timing Limits more information.
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MX29F040
ERASE SUSPEND
This command only meaning while state machine executing Automatic Sector Erase operation, therefore will only responded during Automatic Sector Erase operation. When Erase Suspend command written during sector erase operation, device requires maximum 100us suspend erase operations. However, When Erase Suspend command written during sector erase time-out, device immediately terminates time-out period suspends erase operation. After this command been executed, command register will initiate erase suspend mode. state machine will return read mode automatically after suspend ready. this time, state machine only allows command register respond Read Memory Array, Erase Resume program commands. system determine status program operation using status bits, just standard program operation. After erase-suspend program operation complete, system once again read array data within non-suspended sectors. program opetation unsuccessful, data "1"(see Table indicating program operation exceed internal timing limit. automatic programming operation completed when data read stops toggling consecutive read cycles data equivalent data written these bits, which time device returns Read mode(no program verify command required).
DATA POLLING-Q7
MX29F040 also features Data Polling method indicate host system that Automatic Program Erase algorithms either progress completed. While Automatic Programming algorithm operation, attempt read device will produce complement data data last written Upon completion Automatic Program Algorithm attempt read device will produce true data last written Data Polling feature valid after rising edge fourth whichever happeds first pulse four write pulse sequences automatic program. While Automatic Erase algorithm operation, will read until erase operation competed. Upon completion erase operation, data will read "1". Data Polling feature valid after rising edge sixth whichever happeds first pulse write pulse sequences automatic chip/ sector erase. Data Polling feature active during Automatic Program/Erase algorithm sector erase time-out.(see section Sector Erase Timer)
ERASE RESUME
This command will cause command register clear suspend state return back Sector Erase mode only Erase Suspend command previously issued. Erase Resume will have effect other conditions.Another Erase Suspend command written after chip resumed erasing.
SET-UP AUTOMATIC PROGRAM COMMANDS
initiate Automatic Program mode, three-cycle command sequence required. There "unlock" write cycles. These followed writing Automatic Program command A0H. Once Automatic Program command initiated, next pulse causes transition active programming operation. Addresses latched falling edge, data internally latched rising edge whichever happeds first pulse. rising edge whichever happeds first also begins programming operation. system required provide further controls timings. device will automatically provide adequate internally generated program pulse verify margin.
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REV. 1.6, AUG. 2001
MX29F040
Q6:Toggle
Toggle indicates whether Automatic Program Erase algorithm progress complete, whether device entered Erase Suspend mode. Toggle read address, valid after rising edge final whichever happeds first pulse command sequence(prior program erase operation), during sector timeout. During Automatic Program Erase algorithm operation, successive read cycles address cause toggle. system either control read cycles. When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles returns reading array data. selected sectors protected, Automatic Erase algorithm erases unprotected sectors, ignores selected sectors that protected. system together determine whether sector actively erasing erase suspended. When device actively erasing (that Automatic Erase algorithm progress), toggling. When device enters Erase Suspend mode, stops toggling. However, system must also determine which sectors erasing erase-suspended. Alternatively, system program address falls within protected sector, toggles approximately after program command sequence written, then returns reading array data. also toggles during erase-suspend-program mode, stops toggling once Automatic Program algorithm complete. Table shows outputs Toggle toggles when system reads addresses within those sectors that have been selected erasure. (The system either control read cycles.) cannot distinguish whether sector actively erasing erase-suspended. comparison, indicates whether device actively erasing, Erase Suspend, cannot distinguish which sectors selected erasure. Thus, both status bits required sectors mode information. Refer Table compare outputs
Reading Toggle Bits
Whenever system initially begins reading toggle status, must read Q7-Q0 least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data Q7-Q0 following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section Q5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfuly completed program erase operation. still toggling, device complete operation successfully, system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation.
Q2:Toggle
"Toggle when used with indicates whether particular sector actively eraseing (that Automatic Erase alorithm process), whether that sector erase-suspended. Toggle valid after rising edge final whichever happeds first pulse command sequence.
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MX29F040
Exceeded Timing Limits
will indicate program erase time exceeded specified limits(internal pulse count). Under these conditions will produce "1". This time-out condition indicates that program erase cycle successfully completed. Data Polling Toggle only operating functions device under this condition. this time-out condition occurs during sector erase operation, specifies that particular sector reused. However, other sectors still functional used program erase operation. device must reset other sectors. Write Reset command sequence device, then execute program erase command sequence. This allows system continue other active sectors device. this time-out condition occurs during chip erase operation, specifies that entire chip combination sectors bad. this time-out condition occurs during byte programming operation, specifies that entire sector containing that byte this sector maynot reused, (other sectors still functional reused). time-out condition also appear user tries program blank location without erasing. this case device locks never completes Automatic Algorithm operation. Hence, system never reads valid data never stops toggling. Once Device exceeded timing limits, will indicate "1". Please note that this device failure condition since device incorrectly used. with control register architecture, alteration memory contents only occurs after successful completion specific command sequences. device also incorporates several features prevent inadvertent write cycles resulting from power-up powerdown transition system noise.
Sector Erase Timer
After completion initial sector erase command sequence, sector erase time-out will begin. will remain until time-out complete. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command, used determine sector erase timer window still open. high ("1") internally controlled erase cycle begun; attempts write subsequent commands device will ignored until erase operation completed indicated Data Polling Toggle Bit. ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent sector erase command. were high second status check, command have been accepted.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses less than 5ns(typical) will initiate write cycle.
LOGICAL INHIBIT
Writing inhibited holding VIL, VIH. initiate write cycle must logical zero while logical one.
DATA PROTECTION POWER SUPPLY DECOUPLING
MX29F040 designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transition. During power device automatically resets state machine Read mode. addition, order reduce power switching effect, each device should have 0.1uF ceramic capacitor connected between GND.
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REV. 1.6, AUG. 2001
MX29F040
SECTOR PROTECTION WITH SYSTEM
MX29F040 features sector protection. This feature will disable both program erase operations these sectors protected. activate this mode, programming equipment must force address control (suggest 12V) VIL.(see Table Programming protection circuitry begins falling edge whichever happeds later pulse terminated rising edge. Please refer sector protect algorithm waveform. verify programming protection circuitry, programming equipment must force address with VIH). When A1=1, will produce logical code device output protected sector. Otherwise device will produce unprotected sector. this mode, addresses, except don't care. Address locations with reserved read manufacturer device codes.(Read Silicon also possible determine sector protected system writing Read Silicon command. Performing read operation with A1=VIH, will produce logical protected sector. also possible determine chip unprotected system writing Read Silicon command. Performing read operation with A1=VIH, will produce data outputs(Q0-Q7) unprotected sector. noted that sectors unprotected after chip unprotect algorithm completed.
POWER-UP SEQUENCE
MX29F040 powers Read only mode. addition, memory contents only altered after successful completion predefined command sequences.
SECTOR PROTECTION WITHOUT SYSTEM
MX29F040 also feature sector protection method system without power suppply. programming equipment need supply volts protect sectors. details shown sector protect algorithm waveform.
CHIP UNPROTECT WITHOUT SYSTEM CHIP UNPROTECT WITH SYSTEM
MX29F040 also features chip unprotect mode, that sectors unprotected after chip unprotect completed incorporate changes code. recommended protect sectors before activating chip unprotect mode. activate this mode, programming equipment must force control address pins must VIL. Pins must VIH.(see Table Refer chip unprotect algorithm waveform chip unprotect algorithm. unprotection mechanism begins falling edge whichever happeds later, pulse terminated rising edge. MX29F040 also feature chip unprotection method system without power supply. programming equipment need supply volts unprotect sectors. details shown chip unprotect algorithm waveform.
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REV. 1.6, AUG. 2001
MX29F040
CAPACITANCE 25oC, MHz)
SYMBOL CIN1 CIN2 COUT PARAMETER Input Capacitance Control Capacitance Output Capacitance MIN. MAX. UNIT CONDITIONS VOUT
READ OPERATION
CHARACTERISTICS 5V±10%)
SYMBOL ISB1 ISB2 ICC1 ICC2 VOH1 VOH2 Input Voltage Input High Voltage Output Voltage Output High Voltage(TTL) Output High Voltage(CMOS) VCC-0.4 -0.3(NOTE Operating current PARAMETER Input Leakage Current Output Leakage Current Standby current MIN. MAX. 0.45 UNIT 2.1mA -2mA -100uA,VCC=VCC CONDITIONS VOUT 0.3V IOUT 0mA, f=5MHz IOUT 0mA, f=10MHz
NOTES: min. -1.0V pulse width equal less than max. 1.5V pulse width equal less min. -2.0V pulse width equal less than than over specified maximum value, read operation cannot guaranteed.
CHARACTERISTICS 70oC, 5V±10%)
29F040-55(note2)29F040-70 Symbol PARAMETER tACC Address Output Delay Output Delay Output Delay High Output Float (Note1) Address Output hold MIN. MAX. NOTE: defined time which output achieves open circuit condition data longer driven. 2.Under condition VCC=5V±10%,CL=50pF,VIH/VIL=3.0/
REV. 1.6, AUG. 2001
29F040-90
29F040-12 Conditions CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL
MIN. MAX. MIN. MAX. MIN. MAX. Unit
TEST CONDITIONS: Input pulse levels: 0.45V/2.4V Input rise fall times equal less than Output load: gate 100pF (Including scope jig) Reference levels measuring timing: 0.8V, 2.0V
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MX29F040
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Applied Input Voltage Applied Output Voltage Ground Potential -0.5V 7.0V -0.5V 7.0V -0.5V 7.0V -0.5V 13.5V VALUE 70oC -65oC 125oC NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operational sections this specification implied. Exposure absolute maximum rating conditions extended period affect reliability. NOTICE: Specifications contained within following tables subject change.
Ambient Temperature with Power -55oC 125oC
READ TIMING WAVEFORMS
Addresses
Valid
tACC
Outputs
HIGH
DATA Valid
HIGH
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
CHARACTERISTICS 70oC, 5V±10%)
SYMBOL ICC1 (Read) ICC2 ICC3 (Program) ICC4 (Erase) ICCES NOTES: min. -0.6V pulse width equal less than 20ns. over specified maximum value, programming operation cannot guranteed.
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PARAMETER Operating Current
MIN.
MAX.
UNIT
CONDITIONS IOUT=0mA, f=5MHz IOUT=0mA, F=10MHz Programming Erase CE=VIH, Erase Suspended
Erase Suspend Current
ICCES specified with device de-selected. device read during erase suspend mode, current draw ICCES ICC1 ICC2. current unless otherwise noted.
REV. 1.6, AUG. 2001
MX29F040
CHARACTERISTICS 70oC,
29F040-55(Note2) SYMBOL PARAMETER
tOES tCWC tCEP tCEPH1 tCEPH2 tCESC tAETC tAETB tAVT tBAL tVLHT tOESP tWPP1 tWPP2 setup time Command programming cycle programming pulse width programming pluse width High programming pluse width High Address setup time Address hold time Data setup time Data hold time setup time before command write Output disable time (Note Total erase time auto chip erase Total erase time auto sector erase Total programming time auto verify Sector address load time Hold Time setup going Voltge Transition Time Setup Time Active Write pulse width sector protect Write pulse width sector unprotect 4(TYP.)
29F040-70
29F040-90 MAX.
29F040-12 MIN.
MIN.
MAX. MIN.
4(TYP.)
MAX. MIN.
MAX. Unit
4(TYP.) 1.3(TYP.)10.4
4(TYP.) 1.3(TYP.)10.4
1.3(TYP.)10.4
1.3(TYP.) 10.4
NOTES: defined time which output achieves open circuit condition data longer driven. 2.Under conditions IOL=2mA,IOH=-2mA.
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MX29F040
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST 1.6K
1.2K
DIODES=IN3064 EQUIVALENT
CL=100pF Including capacitance 50pF 29F040-55
SWITCHING TEST WAVEFORMS
2.4V
2.0V 2.0V
TEST POINTS
0.8V
0.45V INPUT
0.8V OUTPUT
TESTING: Inputs driven 2.4V logic 0.45V logic "0". Input pulse rise fall times 20ns.(5ns 29F040-55) 29F040-55
COMMAND WRITE TIMING WAVEFORM
Addresses
Valid
tOES tCEPH1 tCWC
tCEP
Data
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MX29F040
AUTOMATIC PROGRAMMING TIMING WAVEFORM
byte data programmed. Verify fast algorithm additional programming external control required because these operations executed automatically internal control circuit. Programming completion verified DATA polling toggle checking after automatic verification starts. Device outputs DATA during programming DATA after programming Q7.(Q6 toggle bit; toggle bit, DATA polling, timing waveform)
AUTOMATIC PROGRAMMING TIMING WAVEFORM
A11~A18
Valid
A0~A10
555H
2AAH
555H
Valid
tCWC tCEPH1 tAVT tCESC
tCEP Q0,Q1,Q2 Q4(Note
Command Command #AAH (Q0~Q7) Command Command #55H Command Command #A0H Data
Command Command Data DATA
Command
DATA polling
DATA DATA
Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Time-out
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MX29F040
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data Address 555H
Write Data Address 2AAH
Write Data Address 555H
Write Program Data/Address
Toggle Checking Toggled
Invalid Command
Verify Byte Auto Program Completed
Reset
Auto Program Exceed Timing Limit
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MX29F040
AUTOMATIC CHIP ERASE TIMING WAVEFORM
data chip erased. External erase verification required because data erased automatically internal control circuit. Erasure completion verified DATA polling toggle checking after automatic erase starts. Device outputs during erasure after erasure Q7.(Q6 toggle bit; toggle bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM
A11~A18
A0~A10
555H
2AAH
555H
555H
2AAH
555H
tCWC tCEPH1
tAETC
tCEP Q0,Q1, Q4(Note
Command Command #AAH Command Command #55H Command Command #80H Command Command #AAH Command Command #55H Command Command #10H Command Command Command Command Command Command
DATA polling
(Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Time-out bit, Toggle
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MX29F040
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data Address 555H
Write Data Address 2AAH
Write Data Address 555H
Write Data Address 555H
Write Data Address 2AAH
Write Data Address 555H
Toggle Checking Toggled
Invalid Command
DATA Polling
Auto Chip Erase Completed
Reset
Auto Chip Erase Exceed Timing Limit
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MX29F040
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector data indicated erased. External erase verify required because data erased automatically internal control circuit. Erasure completion verified DATA polling toggle checking after automatic erase starts. Device outputs during erasure after erasure Q7.(Q6 toggle bit; toggle bit, DATA polling, timing waveform)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
A16-A18
Sector Address0
Sector Address1
Sector Addressn
A0~A10
555H
2AAH
555H
555H
2AAH tCWC
tCEPH1 tBAL tAETB
tCEP
Q0,Q1, Q4(Note
Command
Command
Command
Command
Command
Command
Command
Command
DATA polling
Command
Command
Command
Command
Command
Command
Command Command #30H
Command Command #30H
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H (Q0~Q7)
Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Time-out bit, Toggle
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MX29F040
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data Address 555H
Write Data Address 2AAH
Write Data Address 555H
Write Data Address 555H
Write Data Address 2AAH
Write Data Sector Address
Toggle Checking Toggled
Invalid Command
Load Other Sector Addrss Necessary (Load Other Sector Address)
Last Sector Erase
Time-out Checking Q3=1
Toggle Checking Toggled
DATA Polling
Auto Sector Erase Completed
Reset
Auto Sector Erase Exceed Timing Limit
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MX29F040
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data
Toggle checking toggled Read Array Program
Reading Programming Write Data
Continue Erase
Another Erase Suspend
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REV. 1.6, AUG. 2001
MX29F040
TIMING WAVEFORM SECTOR PROTECTION SYSTEM WITH
tVLHT Verify
tVLHT tWPP tVLHT
tOESP
Data
A18-A16
Sector Address
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
TIMING WAVEFORM CHIP UNPROTECTION SYSTEM WITH
tVLHT
Verify
tVLHT tWPP tVLHT
tOESP
Data
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
SECTOR PROTECTION ALGORITHM SYSTEM WITH
START
Sector Addr (A18, A17, A16)
PLSCNT=1
OE=VID,A9=VID,CE=VIL A6=VIL
Activate Pulse
Time 10us
WE=VIH, CE=OE=VIL should remain
Read from Sector Addr=SA, A1=1
PLSCNT=32?
Data=01H?
Device Failed
Protect Another Sector?
Remove from Write Reset Command
Sector Protection Complete
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
CHIP UNPROTECTION ALGORITHM SYSTEM WITH
START
Protect Sectors
PLSCNT=1
Write "unlock sector protect/unprotect" Command (Table
OE=A9=VIH CE=VIL,A6=1
Activate Pulse start Data do'nt care
Toggle checking Toggled OE=CE=VIL A9=VIH,A1=1 Increment PLSCNT
First Sector Addr
Read Data from Device
Increment Sector Addr
Data=00H?
PLSCNT=1000?
Device Failed
sectors have been verified? Write Reset Command
Chip Unprotect Complete
recommended before unprotect whole chip, sectors should protected advance.
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
TIMING WAVEFORM SECTOR PROTECTION SYSTEM WITHOUT
Toggle polling
Verify
tCEP
following Note!
Data
Don't care (Note
A18-A16
Sector Address
Note1: Must issue "unlock sector protect/unprotect" command before sector protection system without provided. Note2: Except
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
TIMING WAVEFORM CHIP UNPROTECTION SYSTEM WITHOUT
Toggle polling
Verify
tCEP
following Note!
Data
Don't care (Note
Note1: Must issue "unlock sector protect/unprotect" command before sector unprotection system without provided. Note2: Except
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
SECTOR PROTECTION ALGORITHM SYSTEM WITHOUT
START
PLSCNT=1
Write "unlock sector protect/unprotect" Command(Table1)
Sector Addr (A18, A17, A16)
OE=VIH,A9=VIH CE=VIL,A6=VIL
Activate Pulse start Data don't care
Toggle checking Toggled Increment PLSCNT CE=OE=VIL A9=VIH
Read from Sector Addr=SA, A1=1
PLSCNT=32?
Data=01H?
Device Failed
Protect Another Sector?
Write Reset Command
Sector Protection Complete
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
CHIP UNPROTECTION ALGORITHM SYSTEM WITHOUT
START
Protect Sectors
PLSCNT=1
OE=A9=VID CE=VIL,A6=1
Activate Pulse
Time 12ms
Increment PLSCNT
OE=CE=VIL A9=VID,A1=1
First Sector Addr
Read Data from Device
Increment Sector Addr
Data=00H?
PLSCNT=1000?
Device Failed
sectors have been verified? Remove from Write Reset Command
Chip Unprotect Complete
recommended before unprotect whole chip, sectors should protected advance.
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
CODE READ TIMING WAVEFORM
tACC tACC
A2-A8 A10-A18
DATA Q0-Q7
DATA
DATA
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
ORDERING INFORMATION
PLASTIC PACKAGE
PART MX29F040QC-55 MX29F040QC-70 MX29F040QC-90 MX29F040QC-12 MX29F040TC-55 MX29F040TC-70 MX29F040TC-90 MX29F040TC-12 MX29F040PC-55 MX29F040PC-70 MX29F040PC-90 MX29F040PC-12 ACCESS TIME (ns) OPERATING CURRENT MAX.(mA) STANDBY CURRENT MAX.(uA) PLCC PLCC PLCC PLCC TSOP (Normal Type) TSOP (Normal Type) TSOP (Normal Type) TSOP (Normal Type) PDIP PDIP PDIP PDIP PACKAGE
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
ERASE PROGRAMMING PERFORMANCE(1)
PARAMETER
Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles 100,000
MIN.
LIMITS TYP.(2)
MAX.(3)
10.4
UNITS
Cycles
Note:
1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured C,5V. 3.Maximunm values measured 25°C,4.5V.
LATCHUP CHARACTERISTICS
MIN. Input Voltage with respect pins except pins Input Voltage with respect pins Current Includes pins except Vcc. Test conditions: 5.0V, time. -1.0V -1.0V -100mA MAX. 13.5V 1.0V +100mA
DATA RETENTION
PARAMETER Data Retention Time MIN. UNIT Years
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
PACKAGE INFORMATION
32-PIN PLASTIC
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
32-PIN PLASTIC TSOP
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
REVISION HISTORY
Revision Description remove "Advanced Information" datasheet marking contain information products full production. improve ICC1:from 40mA @5MHz 30mA @5MHz description 100K endurance cycle modify timing sector address loading period while operating multi-sector erase from 80us 30us modify tBAL from 80us 100us 1.Program/erase cycle times:10K cycles->100K cycles 2.To remove from "timing waveform sector protection system without 12V" remove from "timing waveform chip unprotection system without 12V" 3.To data retention minimum years erase suspend ready max. 100us ERASE SUSPEND's section page modify "Package Information" "Ambient temperature with power applied" Page P1,13,14,33 P1,34 P1,34 P1,34 P35~37 Date JUL/01/1999 JUL/12/1999 OCT/04/1999
DEC/17/1999
MAY/29/2000 JUN/12/2001 AUG/08/2001
P/N:PM0538
REV. 1.6, AUG. 2001
MX29F040
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
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TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves right change product specifications without notice.
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