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LXP710
HDSL Framer/Mapper 1168 kbps Applications
LXP710 complete HDSL framer/mapper that multiplexes demultiplexes framed unframed 2.048 Mbps data stream onto 1168 kbps HDSL lines. LXP710 also supports point-to-point point-to-multipoint fractional applications with HDSL lines. LXP710 interfaces directly with Level SK70704/SK70707 1168 kbps HDSL data pump industry standard Framers Line Interface ICs. framer/mapper controlled monitored external microprocessor using 8-bit Intel Motorola compatible parallel interface. framer/mapper provides both programmable interrupts synchronized HDSL frame rate. LXP710 provides fully programmable mapping between HDSL interfaces more loops. LXP710 provides support system performance monitoring with internal CRC, FEBE error counters capability inject these errors. framer/mapper automatically controls synchronization between HDSL loop timing payload timing using digital timing recovery transmitter stuffing control circuit.
Product Features
Compliant with ETSI ETR-152 requirements Interfaces with Level HDSL Data Pumps industry standard Framers Line Interface 8-bit, Intel Motorola compatible parallel processor interface with programmable interrupts User definable kbps overhead channel HDSL Overhead Management DPLL Timing Recovery HDSL Transmit Stuffing Control
HDSL Loop Multiplexing/ Demultiplexing Programmable time slot mapping Accepts framed unframed data IDLE Code Insertion provides channel blocking demux directions Channel Grouping Loopbacks toward HDSL interfaces Diagnostics/Performance Monitoring QRSS Pattern Generation Detection CRC, FEBE counters error generators
January 2001, this document replaces Level document known HDSL Framer/Mapper 1168 kbps Applications.
Order Number: 249004-001 January 2001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. LXP710 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
HDSL Framer/Mapper 1168 kbps Applications LXP710
Contents
Assignments Signal Descriptions Functional Description.15
Multiplexer (MX) Demultiplexer (DX) Microprocessor Interface.18 Interface HDSL Interface.20
Register Definitions.21 Application information
Target Applications.62 ETSI Compliant Operation User Definable HDSL Overhead Bits System Software Guidelines 4.4.1 Board Initialization 4.4.2 Loop Activation.66 4.4.3 Normal Operation 4.4.4 Diagnostic Operation.67 4.4.5 External Communication
Test Specifications Mechanical Specifications.83
Figures
LXP710 Block Diagram LXP710 Pinout Diagram.10 Process Process Interface with Loopback Switching.19 HDSL Interface.20 Two-Loop HDSL System Unframed Data Transport Operation.64 Point-to-Multipoint HDSL System Frame Structure Pair Point-to-Point System Interface Input Timing Interface Output Timing HDSL Interface Input Timing HDSL Interface Output Timing Microprocessor Write Cycle-Motorola Mode.75 Microprocessor Read Cycle-Motorola Mode.76 Microprocessor Write Cycle-Intel Mode Microprocessor Read Cycle-Intel Mode.78 Peak Output Jitter Performance
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Output Wander Performance Typical Jitter Transfer Results. Jitter Transfer Measurement Setup. Typical Jitter Tolerance Results Jitter Tolerance Measurement Setup Plastic Leaded Chip Carrier Package Specification.
Tables
Descriptions Register Summary Control Register Demux Control Register HDSL Loop Control Register. HDSL Loop Overhead Control Register HDSL Loop Overhead Control Register HDSL Loop Overhead Control Register Time Slot Grouping Table Control Register Loop Time Slot Control Byte Loop Time Slot Control Byte Loop Time Slot Control Byte Loop Time Slot Control Byte Loop Time Slot Control Byte Loop Time Slot Control Byte Loop Time Slot Control Byte Loop Time Slot Control Byte Loop Time Slot Control Byte Loop Time Slot Control Byte Loop Time Slot Control Byte Programmable Idle Code Bytes QRSS Test Pattern Control Register Frame Pulse Sync Control Register Test Pattern Error Counter Status Register Demux Power Status Register Demux HDSL Repeater Present Status Register Demux Loss Signal Status Register. Loop Reversal Status Register General Interrupt Enable Register General Interrupt Status Register Interrupt Enable Register Interrupt Status Register Indicator Bits Triple Echo Enable Register Indicator Bits Triple Status Register. Global Control Register. Band Width Control (High Byte). Band Width Control (Low Byte) Demux Restart Counter Loop Bits (LSB) Loop Bits Loop Bits
HDSL Framer/Mapper 1168 kbps Applications LXP710
Loop Bits Loop Bits Loop Bits (MSB) Loop Message (High Byte) Loop Message (Low Byte) Loop Bits.43 Demux Loop Bits (LSB).43 Demux Loop Bits.44 Demux Loop Bits.44 Demux Loop Bits.44 Demux Loop Bits.44 Demux Loop Bits (MSB).44 Demux Loop Message (High Byte).45 Demux Loop Message (Low byte).45 Demux Loop Bits Demux Loop Error Count.46 Demux Loop FEBE Error Count Demux Loop Error Count Loop QRSS Test Pattern Error Counter (High byte) Loop QRSS Test Pattern Error Counter (Low).47 Loop Restart Counter Loop Bits (LSB) Loop Bits Loop Bits Loop Bits Loop Bits Loop Bits (MSB) Loop Message (High byte).49 Loop Message (Low byte) Loop Bits.49 Demux Loop Bits (LSB).50 Demux Loop Bits.50 Demux Loop Bits.50 Demux Loop Bits.50 Demux Loop Bits.50 Demux Loop Bits (MSB).51 Demux Loop Message (High byte) Demux Loop Message (Low byte).51 Demux Loop Bits Demux Loop Error Count.52 Demux Loop FEBE Error Count Demux Loop Error Count Loop QRSS Test Pattern Error Counter (High byte) Loop QRSS Test Pattern Error Counter (Low byte) Loop Restart Counter Loop Bits (LSB) Loop Bits Loop Bits Loop Bits Loop Bits
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Loop Bits (MSB) Loop Message (High byte) Loop Message (Low byte) Loop Bits Demux Loop Bits (LSB) Demux Loop Bits. Demux Loop Bits. Demux Loop Bits. Demux Loop Bits. Demux Loop Bits. Demux Loop Message (High byte). Demux Loop Message (Low byte). Demux Loop Bits. Demux Loop Error Count Demux Loop FEBE Error Count. Demux Loop Error Count Loop QRSS Test Pattern Error Counter (High byte) Loop QRSS Test Pattern Error Counter (Low byte) Loop Restart Counter HFMA Version Number Microprocessor Mode Testing Register Microprocessor Mode Testing Register Demux HDSL Frame Structure Pair Point-to-Point System Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics. Interface Input Timing Specifications (Figure Interface Output Timing Specifications (Figure HDSL Interface Input Timing Specifications (Figure HDSL Interface Output Timing Specifications (Figure Microprocessor Write Cycle Specifications-Motorola Mode (Table Microprocessor Read Cycle Specifications-Motorola Mode (Figure 16). Microprocessor Write Cycle Specifications-Intel Mode (Figure Microprocessor Read Cycle Specifications-Intel Mode (Figure ETSI Maximum Wander Values
HDSL Framer/Mapper 1168 kbps Applications LXP710
Revision History
Revision Date Description
HDSL Framer/Mapper 1168 kbps Applications LXP710
Figure LXP710 Block Diagram
FRCMXAIS LOSDI BPVI MULTIPLEX MAPPER ELASTIC STORE DATA PUMP INTERFACE
LPxDTO TFPx
E1FRMI E1DATI E1CLK1
INTERFACE
E1FRMO E1DATO E1CLKO
DPLL
LOSWx RFPx ICLKx LPxDTI
DEMULTIPLEX MAPPER ELASTIC STORE
CLK32M FMOUT EXPLLI MISCELLANEOUS OVERHEAD REGISTERS MICROPROCESSOR INTERFACE
DATA <7:0> ADDR <6:0> TIMING CONTROLS
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Assignments Signal Descriptions
Figure LXP710 Pinout Diagram
MBSE INTGEN INT6MS (RD) RESET E1FRMI E1DATI FT16 GND1 E1CLKI VCC1 FT15 E1CLKO FT14 E1DATO E1FRMO FRCMXAIS LOSDI BPVI FT13 FT12 TSTEN TSTMD1 VCC2 GND2 TSTMD2 (WR) VCC3 CLK32M GND3 FMOUT NME1CKO VCC4 EXPLLI GND4 LP1DTO TFP1 LOSW1 LP1DTI RFP1 ICLK1 FT11 GND6 ICLK3 VCC6 RFP3 LP3DTI LOSW3 TFP3 LP3DTO GND5 FT10 VCC5 REFCLK ICLK2 RFP2 LP2DTI LOSW2 TFP2 LP2DTO
Part
LXP710PE XXXXXX XXXXXXXX
NOTE: Intel compatible parallel interface signal names shown
HDSL Framer/Mapper 1168 kbps Applications LXP710
Package Topside Markings Marking Part Unique identifier this product family. Identifies particular silicon "stepping" refer specification update additional stepping information. Identifies batch. Identifies Finish Process Order. Definition
Table
Descriptions
I/O1 Volt Supply. Clock Input. This input clock samples data frame mark inputs. sampling edge this clock inverted INVMCK control bit. nominal frequency this clock 2.048 MHz. Ground. Factory Test. This should connected reserved factory test. Data Input. This input accepts data serial format. Frame Sync Input. This input identifies first frame position data. signal must High E1CLKI period. Reset (Active Low). Resets internal circuits control registers their default state when driven Low. Data Strobe Read Enable. Intel mode, enables read cycle when Low. Motorola mode, this signal functions data strobe. LXP710 drives D<7:0> with contents addressed register when Low. Interrupt. enabled EOC/Overhead bits Ready, Demux EOC/Overhead bits Ready, Triple-Echo Message Compare. General Purpose Interrupt (Active Low). This output enabled when more internal general purpose interrupt conditions have been met. Motorola Enable. When MBSE High, LXP710 configured Motorola mode. When MBSE Low, LXP710 configured Intel mode. This enable signal configures input function signal function Test Mode Enable. This input should tied disable factory test modes. Test Mode This input should tied reserved factory test modes. Description
Symbol VCC1 E1CLKI GND1 FT16 E1DATI E1FRMI RESET
(RD)
INT6MS INTGEN
MBSE TSTEN TSTMD1 VCC2 GND2
DI/O DI/O DI/O DI/O DI/O DI/O DI/O DI/O
Microprocessor Data Bus. This 8-bit, bidirectional, tri-state general purpose data path that transfer data between LXP710 microprocessor.
Volt Supply. Factory Test. This should connected reserved factory test. Ground.
digital input; digital output, DI/O digital input output; analog input, analog output.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table
Descriptions (Continued)
I/O1 Chip Select (Active Low). This input must enable read write access LXP710. Read/Write Write Enable. Intel mode, enables write cycle when Low. Motorola mode, this signal functions Read/Write control. D<7:0> contents latched into addressed register when Low. Volt Supply. External Reference Clock. Requires 32.768 input internal PLL. Ground. Factory Test. This should connected reserved factory test. Frame Pulse Output. This output provides active High, frame pulse selected from RFP1, RFP2, RFP3 external circuit. External Reference Clock. 2.048 reference framer when input clock. Volt Supply. External Input. This input clock accepts 2.048 phase locked clock from external circuit. Ground. Loop Data Output. This outputs data, which updated falling edge ICLK1, Loop transceiver. nominal rate this signal 1168 kbps. Loop Transmit Frame Pulse (Active Low). level this signal indicates last position each HDSL frame Loop position this pulse 7006 when stuffing added, 7010 when stuffing added. This pulse nominally occurs every milliseconds 1/584 milliseconds. Loop Loss Sync Word Status. This inputs LOSW status from Loop transceiver. This provides hardware override demux TMGSRC control bits, disables Loop error counters, force demux Partial-AIS. EXTDXAIS enabled). internal pull resistor, active High. Loop Data This signal inputs demux data, which sampled rising edge ICLK1, from Loop transceiver. nominal rate this signal 1168 kbps. Loop Receive Frame Pulse (Active Low). level this signal indicates last position each demux HDSL frame Loop position this pulse 7006 when stuffing added, 7010 when stuffing added. This pulse nominally occurs every milliseconds 1/584 milliseconds. Factory Test. This should connected reserved factory test. Loop Transceiver Interface Clock. This clock input synchronizes transfer HDSL data frame mark to/from Loop transceiver. This clock samples LP1DTI RFP1 inputs rising edge, outputs LP1DTO TFP1 outputs falling edge. nominal frequency this clock signal 1168 kHz. Microprocessor Address Bus. This 7-bit input used microprocessor select LXP710 registers read/write data transfer. Description Test Mode This Input should tied reserved factory test modes.
Symbol TSTMD2
(WR) VCC3 CLK32M GND3 FMOUT NME1CKO VCC4 EXPLLI GND4 LP1DTO
TFP1
LOSW1
LP1DTI
RFP1
ICLK1
digital input; digital output, DI/O digital input output; analog input, analog output.
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table
Descriptions (Continued)
I/O1 Description Factory Test. This should connected reserved factory test. Factory Test. This should connected reserved factory test. Factory Test. This should connected reserved factory test. Loop Data Output. This outputs data, which updated falling edge ICLK2, Loop transceiver. nominal rate this signal 1168 kbps. Loop Transmit Frame Pulse (Active Low). level this signal indicates last position each HDSL frame Loop This position this pulse 7006 when stuffing added, 7010 when stuffing added. This pulse nominally occurs every milliseconds 1/584 milliseconds. Loop Loss Sync Word Status. This inputs LOSW status from Loop transceiver. This provides hardware override demux TMGSRC control bits, disables Loop error counters, demux Partial-AIS. internal pull resistor. Loop Data This signal inputs demux data, which sampled rising edge ICLK1, from Loop transceiver. nominal rate this signal 1168 kbps. Loop Receive Frame Pulse (Active Low). level this signal indicates last position each demux HDSL frame Loop position this pulse 7006 when stuffing added, 7010 when stuffing added. This pulse nominally occurs every milliseconds 1/584 milliseconds. Factory Test. This should connected reserved factory test. Loop Transceiver Interface Clock. This clock input synchronizes transfer HDSL data frame mark to/from Loop transceiver. This clock samples LP2DTI RFP2 inputs rising edge, outputs LP2DTO TFP2 outputs falling edge. nominal frequency this clock signal 1168 kHz. Reference Clock. Provides 18.688 reference clock HDSL Loopback test. Volt Supply. Factory Test. This should connected reserved factory test. Ground. Mode Enable. When this input High, mode selected otherwise, mode selected. Loop Data Output. This outputs data, which updated falling edge ICLK3, Loop transceiver. nominal rate this signal 1168 kbps. Loop Transmit Frame Pulse (Active Low). level this signal indicates last position each HDSL frame Loop This position this pulse 7006 when stuffing added, 7010 when stuffing added. This pulse nominally occurs every milliseconds 1/584 milliseconds. Loop Loss Sync Word Status. This inputs LOSW status from Loop transceiver. This provides hardware override demux TMGSRC control bits, disables Loop error counters, force demux Partial-AIS. internal pull resistor. Loop Data This signal inputs demux data, which sampled rising edge ICLK1, from Loop transceiver. nominal rate this signal 1168 kbps. Loop Receive Frame Pulse (Active Low). level this signal indicates last position each demux HDSL frame Loop position this pulse 7006 when stuffing added, 7010 when stuffing added. This pulse nominally occurs every milliseconds 1/584 milliseconds. Volt Supply.
Symbol LP2DTO
TFP2
LOSW2
LP2DTI
RFP2
ICLK2
REFCLK VCC5 FT10 GND5 LP3DTO
TFP3
LOSW3
LP3DTI
RFP3
VCC6
digital input; digital output, DI/O digital input output; analog input, analog output.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table
Descriptions (Continued)
I/O1 Description Loop Transceiver Interface Clock. This clock input synchronizes transfer HDSL data frame mark to/from Loop transceiver. This clock samples LP3DTI RFP3 inputs rising edge, outputs LP3DTO TFP3 outputs falling edge. nominal frequency this clock signal 1168 kHz. Ground. Factory Test. This should connected reserved factory test. Factory Test. This should connected reserved factory test. Factory Test. This should connected reserved factory test. Indicator Input. This provides hardware access HDSL overhead each loop. active High pulse this activates indicator each loop next frame. This signal ORed with separate software control bits each loop that also activate bits. Loss Signal. This provides hardware access HDSL LOSD overhead each loop. active High pulse this activates LOSD indicator loops next frame. This signal ORed with separate software control bits each loop that also activate LOSD bits. Force AIS. When enabled EXTMXAIS control bit, High this forces insert AIS. Frame Sync Output. This output identifies first frame position demux data. signal must High E1CLKO period. nominal frequency this signal kHz. Data Output. This output signal provides data external framer. Factory Test. This should connected reserved factory test. Clock Output. This output used synchronize transfer frame mark data. output edge this clock inverted INVDXCK control bit. nominal frequency this clock 2.048 MHz. Factory Test. This should connected reserved factory test.
Symbol
ICLK3
GND6 FT11 FT12 FT13
BPVI
LOSDI
FRCMXAIS
E1FRMO E1DATO FT14 E1CLKO FT15
digital input; digital output, DI/O digital input output; analog input, analog output.
HDSL Framer/Mapper 1168 kbps Applications LXP710
Functional Description
framer separated into following blocks logic: multiplexer, demultiplexer, microprocessor interface, interface, HDSL interface. following subsections describe each logic function. ETSI Technical Report will yield better understanding ETSI HDSL system. Framer related sections include, limited HDSL core specifications, frame structure Application specific requirements. beyond scope this document completely explain details 152, some directly related HFMA functionality will covered.
Multiplexer (MX)
function block split payload into parts then multiplex each part with HDSL overhead (HOH) bits, including CRC6, Z-bits passed individual HDSL data pumps. block controls stuffing into HDSL data stream. block configuration registers programmed microprocessor. microprocessor also sets Z-bits. Individual loop testing supported generating test error patterns block. Sync word generation data scrambling, defined 152, done SK70707 digital transceiver, therefore performed HFMA. Figure shows simplified logic block process. MX_E1_CTL block uses selected clock load data from Interface into FIFOs. clock either derived clock from data stream, E1CLKI, internal nominal clock (E1_NMCK). MXE1CTL register Table page controls which clock selected well selecting whether data (all clocked into FIFOs. NMFMEN MXE1CTL register, when selects E1FRMI pin, otherwise internally generated frame pulse used. Loop Time Slot Control Byte registers, LnTSCTLx, listed Table through Table control which time slots data stream assigned which HDSL loop. values loaded these registers become valid only after setting LDTABLE TSCTL register (Table page 28). Process HDSL loop data routed HDSL Interface. HDSL loops aligned loop HDSL_MX block multiplexes bits with payload data shown Table page bits consist indicator bits, bits, 14-bit sync word, stuffing bits (when necessary). Each loop multiplexer. CRC6 calculated frame each loop excluding bits, 14-bit sync word stuffing bits. result stored transmitted following frame. other indicator bits febe, losd, bpv, ps1, ps2, hrp, rrbe, rcbe, rega, rta, indc/indr uib. febe generated from process sent HDSL device indicate that error occurred local received data. losd from LOSDI loss signal interface. from BPVI bipolar violation data. bits Power Status bits from (HTU-R) (HTU-C) only. HDSL Repeater Present (repeater only). rrbe, rcbe rega bits used regenerator/repeater status. remote (NTU) alarm. bits Unspecified Indicator Bits.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Several bits error injection testing loop basis. outgoing febe bits injected single errors. continuous error generation. Registers LnOHCTL, listed Table through Table control this activity. transmitted Z-bits bits microprocessor interface. Z-bit transmit registers MXL1Zx Table through Table MXL2Zx Table through Table MXL3Zx Table through Table 110. transmit registers MXL1EOC Table Table MXL2EOC Table Table MXL3EOC Table Table general applications, used HTU-C transmit command continuously HTU-R unit until HTU-R echoes same command back HTU-C three times. recommends some common commands that might used, each vendor specify detailed implementation. only defined Z-bits first three used loop identification. Other Z-bits reserved vendor use. PAT_GEN block generates QRSS pattern generate error that pattern. QRSS place data testing purposes. QRSS signal loop basis controlled PATCTL register described Table page Figure Process
LOSD, BPV, febe CRC6
Data FIFO
LPx_DATA
HDSL_MX
E1_NMCK CLKI MX_E1_CTL E1FRMI FRCMXAIS
PAT_GEN
HDSL Framer/Mapper 1168 kbps Applications LXP710
Demultiplexer (DX)
performs reverse function de-multiplexing HDSL bits into bits payload data then combining HDSL payloads into payload. bits, Z-bits, separated from payload, stored into registers microprocessor read. checks received CRC6 against data sets flag case error condition. also provides clock based upon internal PLL. Figure shows simplified logic diagram Process. Each individual loop data clocked into separate FIFO. DX_E1_CTL block controls Write Enable FIFOs blocking bits from being loaded into FIFOs. DX_E1_CTL selects from which FIFO load data. ordering time slots based values programmed into LnTSCTLx registers described Table through Table values loaded these registers become valid only after setting LDTABLE TSCTL register, Table data passed through DX_E1_DATA. other selection AIS. outgoing data controlled LSBs DXE1CTL register Table DX_E1_CTL block generates 1168KHz gapped clock reference E1_TMG_GEN block. DX_E1_CTL uses DX_E1_CK from E1_TMG_GEN track current position outgoing data stream generate DX_E1_FM, framing pulse. E1_TMG_GEN uses DX_GAP_CK reference DX_E1_CK. DX_E1_NMCK nominal clock used AIS, loopback source NME1CKO sync framer when clock. OH_PROC, overhead processor, looks bits incoming HDSL frames. There OH_PROC block each HDSL loop. received Z-bits, bits overhead bits latched into their respective registers UP_IF. calculated received data result stored comparison against bits following frame. error generates febe Process. OH_PROC increments associated error counters CRC, febe bpv. These counters µP_IF section. sync word bits stuffing bits discarded. OH_PROC compares loop received from each loop generates report µP_IF, LPRSTAT register Table sends loop correction bits HDSL Interface. PAT_DET block, loop, generates Pattern Sync Lost indication bit, PATLOS PATSTAT register (see Table page 35), when sync present. PAT_DET increments appropriate LnPATECL Table Table Table 109) counter each instance QRSS pattern failure. Overflows these counters indicated PATSTAT register OVERFLOW bits Table 24). Overflows also trigger interrupt µP_IF registers GENINTEN GENINTSTAT (Table Table 30).
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Figure Process
DX_LPx_CK DX_E1_DATA WRx_EN FIFO DX_LPx_CK DX_E1_FM DX_E1_CTL LOOP DATA
MODE
DX_GAP_CK PAT_DET
P_IF
febex OH_PROC
LPREVx
MODE_SELECT DX_E1_CK LOSWx E1_TMG_GEN DX_E1_NMCK CLK32M EXPLLI
Microprocessor Interface
microprocessor interface provides access LXP710's registers routes interrupt signals external pins. MBSE configures LXP710 microprocessor interface either Intel Motorola timing. LXP710 registers described 2Table through Table 113.
HDSL Framer/Mapper 1168 kbps Applications LXP710
Motorola Mode (MBSE High), data D<0:7>, address A<0:6>, used read write LXP710's internal registers. Intel Mode (MBSE Low), data D<0:7>, address A<0:6>, used read write LXP710's internal registers. board design must include latch, using ALE, address from Intel multiplexed bus. This latch could shared with data pumps other devices board that have non-multiplexed address pins. optimize code execution, external interrupt pins, INTGEN INT6MS, provided. INTGEN general purpose interrupts listed GENINTEN GENINTSTAT registers Table Table INDCR bits IND_3EOCINTEN IND_3EOCINTSTAT registers Table Table also tied INTGEN pin. INT6MS timing related functions such when Z-bits ready loaded transmit when Z-bits have been received. Additionally Triple-Echo Message Compare Detected bits IND_3EOCINTEN IND_3EOCINTSTAT registers (Table Table also tied INT6MS pin. This feature reduces software processing needed detect that message been received three times.
Interface
interface connects framer device. shown Figure incoming data routed controlled signals from framer. interface takes data from provides control signals framer. loopbacks available. first loopback input data output data. other loopback internal payload back block. shown diagram, loopbacks tied together. loopback achieved setting E1LB DXE1CTL register described Table
Figure Interface with Loopback Switching
E1CLKI E1FRMI E1DATI
MX_E1_CK MX_E1_FM MX_E1_DT
E1DAT0 E1FRM0 E1CLK0
DX_E1_DT DX_E1_FM DX_E1_CK
LXP710 HDSL Framer/Mapper 1168 kbps Applications
HDSL Interface
HDSL interface block connects HDSL loops blocks. block provide loop switching, well loopback each external incoming loop loopback internal signals block. Figure shows possible signal routings. When HDSLLB LPCTL register Table set, HDSL Interface loopbacks set. LOOP_REV block shows loop swap combination Process Figure 2.3. status loop connections monitored reading LPREV bits LPRSTAT register. Table
Figure HDSL Interface
MX_LP1 DX_LP1 MX_LP2 DX_LP2
LP1O LP1I LP2O LP2I
MX_LP3 DX_LP3 MUX_LB LOOP_REV HDSL_LB
LP3O LP3I
HDSL Framer/Mapper 1168 kbps Applications LXP710
Register Definitions
Table provides summary LXP710 registers. Table through Table provide detailed descriptions each LXP710 register bits. specified default values when LXP710 reset
Table
Address
Register Summary
Decimal Address Symbol MXE1CTL DXE1CTL LPCTL L1OHCTL L2OHCTL L3OHCTL TSCTL L1TSCTL1 L1TSCTL2 L1TSCTL3 L1TSCTL4 L2TSCTL1 L2TSCTL2 L2TSCTL3 L2TSCTL4 L3TSCTL1 L3TSCTL2 L3TSCTL3 L3TSCTL4 IDLECODE PATCTL FMSYNC_PLLCTL PATSTAT DXPSSTAT DXHRPSTAT DXLOSDSTAT LPRSTAT GENINTEN GENINTSTAT 6MSINTEN 6MSINTSTAT Type Description control register Demux control register HDSL loop control register HDSL Loop overhead control register HDSL Loop overhead control register HDSL Loop overhead control register Time slot grouping table control register Loop time slot control byte Loop time slot control byte Loop time slot control byte Loop time slot control byte Loop time slot control byte Loop time slot control byte Loop time slot control byte Loop time slot control byte Loop time slot control byte Loop time slot control byte Loop time slot control byte Loop time slot control byte Programmable idle code bytes QRSS test pattern control register Frame pulse sync control register Test pattern error counter status register Demux power status register Demux HDSL repeater present status register Demux loss signal status register Loop reversal status register General interrupt enable register General interrupt status register interrupt enable register interrupt status register
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table
Address 3D-3F 40-44
Register Summary (Continued)
Decimal Address 61-63 64-68 Symbol IND_3EOCINTEN IND_3EOCINTSTAT GLBCTL PLL_BWH PLL_BWL DXRSCNTR MXL1Z1 MXL1Z2 MXL1Z3 MXL1Z4 MXL1Z5 MXL1Z6 MXL1EOCH MXL1EOCL MXL1UIB DXL1Z1 DXL1Z2 DXL1Z3 DXL1Z4 DXL1Z5 DXL1Z6 DXL1EOCH DXL1EOCL DXL1UIB DXL1CRCEC DXL1FEBEEC DXL1BPVEC L1PATECH L1PATECL MX1RSCNTR MXL2Z1 MXL2Z2 MXL2Z3 MXL2Z4 MXL2Z5 Type Description Indicator bits triple echo enable register Indicator bits triple echo status register Global control register band width control (high byte) band width control (low byte) Demux loops restart counter loop bits (LSB) loop bits loop bits loop bits loop bits loop bits (MSB) loop message (high byte) loop message (low byte) loop bits Demux loop bits (LSB) Demux loop bits Demux loop bits Demux loop bits Demux loop bits Demux loop bits (MSB) Demux loop message (high byte) Demux loop message (low byte) Demux loop bits Demux loop error count Demux loop FEBE error count Demux loop error count Loop QRSS test pattern error counter (High) Loop QRSS test pattern error counter (Low) Loop restart counter Unused Unused loop bits (LSB) loop bits loop bits loop bits loop bits
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table
Address 5D-5F 60-64
Register Summary (Continued)
Decimal Address 93-95 96-100 Symbol MXL2Z6 MXL2EOCH MXL2EOCL MXL2UIB DXL2Z1 DXL2Z2 DXL2Z3 DXL2Z4 DXL2Z5 DXL2Z6 DXL2EOCH DXL2EOCL DXL2UIB DXL2CRCEC DXL2FEBEEC DXL2BPVEC L2PATECH L2PATECL MX2RSCNTR MXL3Z1 MXL3Z2 MXL3Z3 MXL3Z4 MXL3Z5 MXL3Z6 MXL3EOCH MXL3EOCL MXL3UIB DXL3Z1 DXL3Z2 DXL3Z3 DXL3Z4 DXL3Z5 DXL3Z6 DXL3EOCH Type Description loop bits (MSB) loop message (High byte) loop message (Low byte) loop bits Demux loop bits (LSB) Demux loop bits Demux loop bits Demux loop bits Demux loop bits Demux loop bits (MSB) Demux loop message (High byte) Demux loop message (Low byte) Demux loop bits Demux loop error count Demux loop FEBE error count Demux loop error counter Loop QRSS test pattern error counter (High byte) Loop QRSS test pattern error counter (Low byte) Loop restart counter Unused Unused loop bits (LSB) loop bits loop bits loop bits loop bits loop bits (MSB) loop message (High byte) loop message (Low byte) loop bits Demux loop bits (LSB) Demux loop bits Demux loop bits Demux loop bits Demux loop bits Demux loop bits (MSB) Demux loop message (High byte)
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table
Address
Register Summary (Continued)
Decimal Address Symbol DXL3EOCL DXL3UIB DXL3CRCEC DXL3FEBEEC DXL3BPVEC L3PATECH L3PATECL MX3RSCNTR MXTEST DXTEST Type Description Demux loop message (Low byte) Demux loop bits Demux loop error count Demux loop FEBE error count Demux loop error count Loop QRSS test pattern error counter (High byte) Loop QRSS test pattern error counter (Low byte) Loop restart counter HFMA version number
mode testing register mode testing register demux
Control Register
Address: Abbreviation: MXE1CTL Read/Write Table
Control Register
Name INVMXCK Default used; Always read Low. used; Always read Low. Invert Input Clock. When High, rising edge E1CLKI samples data frame mark. When this Low, falling edge samples data frame mark. Nominal Clock Enable. When High, nominal clock selected input MX_PROCESS block. When Low, recovered clock selected input MX_PROCESS block. Nominal Frame Pulse Enable. When High, nominal frame pulse selected input MX_PROCESS block. When Low, Demux frame pulse selected input MX_PROCESS block. Sliding Enable. When High, sliding mode selected. When Low, jerking mode selected. Send AIS. When High, inserted into HDSL payload two/three loops. When Low, incoming inserted. This control ORed with FRCMAIS input (when enabled) control AIS. External Enable. When High, FRCMAIS input enabled insert AIS. When Low, insert controlled solely SNDMAIS control bit. Description
NMCKEN
NMFMEN
MXSLIDEN
SNDMXAIS
EXTMAIS
HDSL Framer/Mapper 1168 kbps Applications LXP710
NOTE: Usage NMCKEN NMFMEN are: Operation Framed service Unframed service loopback loss signal (LOS) NMCKEN NMFMEN
(where framer doesn't provide clock LOS)
Demux Control Register
Address: Abbreviation: DXE1CTL Read/Write Table
Demux Control Register
Name INVDXCK Default Description Invert Demux Output Clock. When High, demux data frame mark signals updated falling edge E1CLKO. When this Low, data frame mark updated rising edge. Loopback. When High, both directions clock, data, frame mark looped back. When Low, normal operation enabled. Demux Timing Source Select. These bits select ADPLL output nominal clock E1CLK0. dependent status input pins LOSWx software setting LPCTL register. loop with first inactive LOSW status will selected. LOSWx active, force nominal clock. force loop force loop force loop Demux Loop Enable. When High, demux Loop payload forced ones. When Low, normal operation enabled. Demux Loop Enable. When High, demux Loop payload forced ones. When Low, normal operation enabled. Demux Loop Enable. When High, demux Loop payload forced ones. When Low, normal operation enabled. External Demux Enable. When High, LOSW1 input enabled force demux Loop payload ones, LOSW2 input enabled force demux Loop payload ones, LOSW3 input enabled force demux Loop payload ones. When EXTDAIS Low, external demux insertion disabled.
E1LB TMGSRC1
TMGSRC0
DXAIS3 DXAIS2 DXAIS1
EXTDAIS
LXP710 HDSL Framer/Mapper 1168 kbps Applications
HDSL Loop Control Register
Address: Abbreviation: LPCTL Read/Write Table
HDSL Loop Control Register
Name HDSLLB LOSW3C1 LOSW3C0 LOSW2C1 LOSW2C0 LOSW1C1 LOSW1C0 Default used; Always read Low. HDSL Loopback Enable. When High, both directions Loop Loop Loop frame mark data signals looped back. When Low, HDSL loopbacks disabled. LOSW3 Control Normal Operation: Force Active: Force Inactive: LOSW2 Control Normal Operation: Force Active: Force Inactive: LOSW1 Control Normal Operation: Force Active: Force Inactive: Description
HDSL Loop Overhead Control Register
Address: Abbreviation: L1OHCTL Read/Write Table
HDSL Loop Overhead Control Register
Name Default used; Always read Low. Loop FEBE Inject (Single-bit). Low-to-High transition this causes Loop FEBE overhead activated frame. After FEBE been inserted, this control automatically cleared. FEBE also activated each time demux error detected either loop). Loop Error Inject (Single-bit). Low-to-High transition this causes Loop overhead activated frame. After been transmitted, this control automatically cleared. indicator also activated input pin. Loop Error Inject (Continuous). When High, continuous error injected Loop code until this cleared microprocessor. Description
L1FEBE
L1BPV
L1CRCE
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table
HDSL Loop Overhead Control Register (Continued)
Name L1LOSD Default Description Loop LOSD Alarm Activate. When High, Loop LOSD alarm overhead activated until this reset microprocessor. When Low, LOSD alarm bits still sent when LOSD input active. Loop HDSL Repeater Present Control. When High, Loop overhead activated until this reset microprocessor. Loop Power Status Control. When High, Loop overhead activated until this reset microprocessor. Loop Power Status Control. When High, Loop overhead activated until this reset microprocessor.
L1HRP L1PS1 L1PS2
Note:
Although HDSL overhead indicator bits active HDSL data stream, control bits this register active High, i.e., overhead control bits inverted before they transmitted loop.
HDSL Loop Overhead Control Register
Address: Abbreviation: L2OHCTL Read/Write Table
HDSL Loop Overhead Control Register
Name Default used; Always read Low. Loop FEBE Inject (Single-bit). Low-to-High transition this causes Loop FEBE overhead activated frame. After FEBE been inserted, this control automatically cleared. FEBE also activated each time demux error detected either loop). Loop Error Inject (Single-bit). Low-to-High transition this causes Loop overhead activated frame. After been transmitted, this control automatically cleared. indicator also activated microprocessor. Loop Error Inject (Continuous). When High, continuous error injected Loop code until this cleared microprocessor. Loop LOSD Alarm Activate. When High, Loop LOSD alarm overhead activated until this reset microprocessor. When Low, LOSD alarm sent LOSD input active. Loop HDSL Repeater Present Control. When High, Loop overhead activated until this reset microprocessor. Loop Power Status Control. When High, Loop overhead activated until this reset microprocessor. Loop Power Status Control. When High, Loop overhead activated until this reset microprocessor. Description
L2FEBE
L2BPV
L2CRCE
L2LOSD
L2HRP L2PS1 L2PS2
Note:
Although HDSL overhead indicator bits active HDSL data stream, control bits this register active High, i.e., overhead control bits inverted before they transmitted loop.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
HDSL Loop Overhead Control Register
Address: Abbreviation: L3OHCTL Read/Write Table
HDSL Loop Overhead Control Register
Name Default used; Always read Low. Loop FEBE Inject (Single-bit). Low-to-High transition this causes Loop FEVE overhead activated frame. After FEBE been inserted, this control automatically cleared. FEBE also activated each time demux error detected either loop). Loop Error Inject (Single-bit). Low-to-High transition this causes Loop overhead activated frame. After been transmitted, this control automatically cleared. indicator also activated microprocessor. Loop Error Inject (Continuous). When High, continuous error injected Loop code until this cleared microprocessor. Loop LOSD Alarm Activate. When High, Loop LOSD alarm overhead activated until this reset microprocessor. When Low, LOSD alarm sent LOSD input active. Loop HDSL Repeater Present Control. When High, Loop overhead activated until this reset microprocessor. Loop Power Status Control. When High, Loop overhead activated until this reset microprocessor. Loop Power Status Control. When High, Loop overhead activated until this reset microprocessor. Description
L3FEBE
L3BPV
L3CRCE
L3LOSD
L3HRP L3PS1 L3PS2
Note:
Although HDSL overhead indicator bits active HDSL data stream, control bits this register active High, i.e., overhead control bits inverted before they transmitted loop.
Time Slot Grouping Table Control Register
Address: Abbreviation: TSCTL Read/Write Table
Time Slot Grouping Table Control Register
Name LPREN3 LPREN2 LPREN1 Default used; Always read Low. Loop Reversal Detection Enable. When High, enables loop detection operation. Loop Reversal Detection Enable. When High, enables loop detection operation. Loop Reversal Detection Enable. When High, enables loop detection operation. Description
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table
Time Slot Grouping Table Control Register (Continued)
Name SWAPEN LDTABLE FULLE1 Default Description Preferred Loop Enable. When High, time slot tables Loop Loop swapped. Load Time Slot Grouping Table. When High, time slot grouping tables loaded into Demux blocks cleared automatically. Full E1/Fractional Control. When High, fractional application selected. When Low, full selected.
HDSL Loop Time Slot Control Byte bytes)
Address: Abbreviation: L1TSCTL1 Read/Write Table Loop Time Slot Control Byte
Name TSG0 TSG1 TSG2 TSG3 TSG4 TSG5 TSG6 TSG7 Default Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code. Description
Address: Abbreviation: L1TSCTL2 Read/Write Table Loop Time Slot Control Byte
Name TSG8 TSG9 TSG10 TSG11 TSG12 TSG13 TSG14 TSG15 Default Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code. Description
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Address: Abbreviation: L1TSCTL3 Read/Write Table Loop Time Slot Control Byte
Name TSG16 TSG17 TSG18 TSG19 TSG20 TSG21 TSG22 TSG23 Default Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code. Description
Address: Abbreviation: L1TSCTL4 Read/Write Table Loop Time Slot Control Byte
Name TSG24 TSG25 TSG26 TSG27 TSG28 TSG29 TSG30 TSG31 Default Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code. Description
Address: Abbreviation: L2TSCTL1 Read/Write
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table Loop Time Slot Control Byte
Name TSG0 TSG1 TSG2 TSG3 TSG4 TSG5 TSG6 TSG7 Default Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code. Description
Address: Abbreviation: L2TSCTL2 Read/Write Table Loop Time Slot Control Byte
Name TSG8 TSG9 TSG10 TSG11 TSG12 TSG13 TSG14 TSG15 Default Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code. Description
Address: Abbreviation: L2TSCTL3 Read/Write
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Name TSG16 TSG17 TSG18 TSG19 TSG20 TSG21 TSG22 TSG23
Default
Description
Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code.
Address: Abbreviation: L2TSCTL4 Read/Write Table Loop Time Slot Control Byte
Name TSG24 TSG25 TSG26 TSG27 TSG28 TSG29 TSG30 TSG31 Default Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code. Description
Address: Abbreviation: L3TSCTL1 Read/Write Table Loop Time Slot Control Byte
<7:0> Name TSG<0:7> Default Description Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code.
Address: Abbreviation: L3TSCTL2 Read/Write
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table Loop Time Slot Control Byte
<7:0> Name TSG<8:15> Default Description Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code.
Address: Abbreviation: L3TSCTL3 Read/Write Table Loop Time Slot Control Byte
<7:0> Name TSG<16:23> Default Description Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code.
Address: Abbreviation: L3TSCTL4 Read/Write Table Loop Time Slot Control Byte
<7:0> Name TSG<24:31> Default Description Loop Time Slot Grouping (Byte Each that blocks transmission corresponding channel forcing bits idle code.
Programmable Idle Code Byte
Address: Abbreviation: IDLECODE Read/Write Table Programmable Idle Code Bytes
<7:0> Name IDLE<7:0> Default Description Programmable Idle Code. This code contains byte used channel blocking. IDLE7 first channel shifted out.
QRSS Test Pattern Control
Address: Abbreviation: PATCTL Read/Write
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table QRSS Test Pattern Control Register
Name PATEN3 Default used; Always read Low. Loop Test Pattern Generation/Detection Enable. When High, internal pattern inserted into HDSL payload. When Low, incoming inserted. Loop Test Pattern Generation/Detection Enable. When High, internal pattern inserted into HDSL payload. When Low, incoming inserted. Loop Test Pattern Generation/Detection Enable. When High, internal pattern inserted into HDSL payload. When Low, incoming inserted. Loop Test Pattern Error Injection. When High, error injected into loop payload. When Low, error injection disabled. After frame pulses occurs, this cleared. Loop Test Pattern Error Injection. When High, error injected into loop payload. When Low, error injection disabled. After frame pulses occurs, this cleared. Loop Test Pattern Error Injection. When High, error injected into loop payload. When Low, error injection disabled. After frame pulses occurs, this cleared. Description
PATEN2
PATEN1
PATERRI3
PATERRI2
PATERRI1
Frame Pulse Sync Control Register
Address: Abbreviation: FMSYNC_PLLCTL Read/Write Table Frame Pulse Sync Control Register
<7:5> Name SYNCEN Default used; Always read Low. Loops Alignment Enable. When High, this enables synchronization HDSL frames. Frame Pulse Synchronization Select: frame synchronization SYNCFM[1] Sync with Loop frame pulse Sync with Loop frame pulse Sync with Loop frame pulse SYNCFM[0] E1CLKSRC LOCKSEL Clock Source Select; External Timing Source; Internal Timing Source. Locking Time Select; Slow locking time; Fast locking time. Description
HDSL Framer/Mapper 1168 kbps Applications LXP710
Test Pattern Error Counter Status Register
HDSL overhead status bits this register latched active High when detected, remain High until write done microprocessor. Address: Abbreviation: PATSTAT Read/Write Table Test Pattern Error Counter Status Register
<7:6> <5:3> <2:0> Name OVERFLOW<3:1> PATLOS<3:1> Default used; Always read Low. Loop <3:1> Test Pattern Error Counter Status. When High, Pattern Error Counter overflowed. Loop <3:1> Sync Pattern Detector Status. When High, Pattern Sync lost. Description
Demux Power Status Register
Address: Abbreviation: DXPSSTAT Read/Write Table Demux Power Status Register
<7:6> Name DL3PS1 DL3PS2 DL2PS1 DL2PS2 DL1PS1 DL1PS2 Default used; Always read Low. Demux Loop3 power status Demux Loop3 power status Demux Loop2 power status Demux Loop2 power status Demux Loop power status Demux Loop power status Description
HDSL overhead status bits this register latched active High when detected, remain High until write done microprocessor. Note: Although HDSL overhead indicator bits active HDSL data stream, status bits this register active High, i.e., status bits inverted from what received loop.
Demux HDSL Repeater Present Status Register
Address: Abbreviation: DXHRPSTAT
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Read/Write Table Demux HDSL Repeater Present Status Register
<7:3> <2:0> Name D<3:1>HRP Default used; Always read Low. Demux loop<3:1> HDSL Repeater present status bit. Description
Note:
Although HDSL overhead indicator bits active HDSL data stream, status bits this register active High, i.e., status bits inverted from what received loop.
Demux Loss Signal Status Register
Address: Abbreviation: DXLOSDSTAT Read/Write Table Demux Loss Signal Status Register
<7:3> <2:0> Name D<3:1>LOSD Default used; Always read Low. Demux loop<3:1> loss signal status bit. Description
HDSL overhead status bits this register latched active High when detected, remain High until write logic done microprocessor. Note: Although HDSL overhead indicator bits active HDSL data stream, status bits this register active High, i.e., status bits inverted from what received loop.
Loop Reversal Status Register
Address: Abbreviation: LPRSTAT Read/Write Table Loop Reversal Status Register
Name LPRDONE3 LPRDONE2 LPRDONE1 Default used; Always read zero. Loop Reversal Detect. When HTUC Mode (LTU Loop detected loop identification returned from HTUR. HTUR Mode (LTU Loop detected same loop identification three times, Loop reversal done. Description
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table Loop Reversal Status Register (Continued)
Name LPREV[2] LPREV[1] Default Description 000: Directs Loop data Loop buffer Loop data Loop buffer. 001: Directs Loop data Loop buffer Loop data Loop buffer. 010: Directs Loop data Loop buffer Loop data Loop buffer. 011: Directs Loop data Loop buffer Loop data Loop buffer. LPREV[0] 100: Directs Loop data Loop buffer Loop data Loop buffer. 101: Directs Loop data Loop buffer Loop data Loop buffer.
General Interrupt Enable Register
Address: Abbreviation: GENINTEN Read/Write Table General Interrupt Enable Register
Name EIPATLOS EIECOVR EILOSD EIPS EIL3INDC_R EIL2INDC_R EIL1INDC_R Default used; Always read Low. Enable interrupt pattern sync loss. Enable Interrupt pattern error counter overflow. Enable interrupt demux loop loop loop LOSD. Enable interrupt demux loop power status indication. Enable interrupt demux loop indc/indr active. Enable interrupt demux loop indc/indr active. Enable interrupt demux loop indc/indr active. Description
General Interrupt Vector Status
HDSL overhead status bits this register latched active High when detected, remain High until write done microprocessor. When logic written these registers, these status bits cleared unless associated overhead still active. Address: Abbreviation: GENINTSTAT Read/Write Table General Interrupt Status Register
Name IVPATLOS IVECOVR IVLOSD Default used; Always read Low. Pattern sync loss. Pattern error counter overflow. Demux loop loop loop LOSD. Description
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table General Interrupt Status Register (Continued)
Name IVPS IVL3INDC_R IVL2INDC_R IVL1INDC_R Default Description Demux loops indication. Demux loop indc/r active, event. Demux loop indc/r active, event. Demux loop 1indc/r active, event.
Note:
INTGEN interrupt corresponds interrupt PATLOS, ECOVR, LOSD, status bits GENINSTAT register INDC/R status bits IND_3EOCSTAT register.
Interrupt Enable Register
Address: Abbreviation: 6MSINTEN Read/Write Table Interrupt Enable Register
<7:6> Name EIMX36MS EIMX26MS EIMX16MS EIDX36MS EIDX26MS EIDX16MS Default used; Always read Low. Enable interrupt loop interrupt. Enable interrupt loop interrupt. Enable interrupt loop interrupt. Enable interrupt loop demux interrupt. Enable interrupt loop demux interrupt. Enable interrupt loop demux interrupt. Description
Interrupt Vector Status
When logic written these registers, these status bits cleared unless associated overhead still active. Address: Abbreviation: 6MSINTSTAT Read/Write Table Interrupt Status Register
<7:6> Name L3MX6MS L2MX6MS L1MX6MS Default used; Always read Low. Loop interrupt. Loop interrupt. Loop interrupt. Description
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Table Interrupt Status Register (Continued)
Name L3DX6MS L2DX6MS L1DX6MS Default Loop demux interrupt. Loop demux interrupt. Loop demux interrupt. Description
Note:
INT6MS interrupt corresponds interrupt Demux status bits 6MSINTSTAT register triple-echo status bits IND_3EOCSTAT register.
Indicator Triple Echo Interrupt Enable Register
Address: Abbreviation: IND_3EOCINTEN Read/Write Table Indicator Bits Triple Echo Enable Register
<7:6> <5:3> Name EIL<3:1>INDCR Default used; Always read zero. Enable interrupt loop <3:1> ready receive indicator bit. Enable Interrupt Loop <3:1> Triple-Echo Message Compare. When High, addition enabling Triple-Echo Message interrupt, integrated message (which updated only when Triple_Echo message valid) output. When Low, non-integrated message (updated every sent receive message register each loop. Description
<2:0>
EIL<3:1>CMP
Indicator Triple Echo Interrupt Status Register
When logic written these registers, these status bits cleared unless associated overhead still active. Address: Abbreviation: IND_3EOCINTSTAT Read/Write Table Indicator Bits Triple Status Register
<7:6> <5:3> Name L<3:1>INDCR Default used; Always read zero. Loop <3:1> Ready Receive Indicator. This status active indicate distant HDSL transceiver that ready receive data. Loop <3:1> Triple-Echo Message Compare Detected. This status active only when message been received three consecutive times. Description
<2:0>
L<3:1>EOCCMP
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Global Control Register
Address: Abbreviation: GLBCTL Read/Write Table Global Control Register
Name LP_CFG[1] Default used; always read zero. HDSL loop configuration fractional application central office side. These bits will control relationship three data buffer's restart. loops coming from same remote terminal. LP_CFG[0] loops coming from same remote terminal. loops coming from same remote terminal. loops coming from different remote terminals. E1DTLB Data Loopback Enable fractional When High, both input/output directions data loopback, clock frame pulse. When Low, normal operation. Framer Select. Select DS2143; Select DS2181. E1FRM0 E1FRM1 coincide with first time slot E1DAT0 E1DATI respectively. E1FRM0 E1FRMI coincide with last time slot E1DAT0 E1DATI respectively. Threshold Modulation Enable. Threshold Modulation Disable. Indicates clock loop source status. <1:0> TMGSTAT loop loop loop Description
E1FMSEL
THMODEN
Band Width Control Registers bytes)
Address: Abbreviation: PLL_BWH Read/Write Table Band Width Control (High Byte)
<7:0> Name PLL_BWH Default Description locking time register High byte. values greater than 80h, longer locking time frequency, with lower jitter amplitude.
Address: Abbreviation: PLL_BWL Read/Write
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table Band Width Control (Low Byte)
<7:0> Name PLL_BWL Default Description locking time register byte. values less than 80h, longer locking time High frequency, with lower jitter amplitude.
Demux Restart Counter Register
Address: Abbreviation: DXRSCNTR Read only Table Demux Restart Counter
<7:0> Name Default Description Demux Restart Counter. Increments each time demux loop been restarted. Primarily used manufacture testing.
Loop Registers Bytes)
Address: Abbreviation: MXL1Z1 Read/Write Table Loop Bits (LSB)
<7:0> Name Z<1:8> Default Loop <1:8> Description
Address: Abbreviation: MXL1Z2 Read/Write Table Loop Bits
<7:0> Name Z<9:16> Default Loop <9:16> Description
Address: Abbreviation: MXL1Z3 Read/Write
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table Loop Bits
<7:0> Name Z<17:24> Default Loop <17:24> Description
Address: Abbreviation: MXL1Z4 Read/Write Table Loop Bits
<7:0> Name Z<25:32> Default Loop <25:32> Description
Address: Abbreviation: MXL1Z5 Read/Write Table Loop Bits
<7:0> Name Z<33:40> Default Loop <33:40> Description
Address: Abbreviation: MXL1Z6 Read/Write Table Loop Bits (MSB)
<7:0> Name Z<41:48> Default Loop <41:48> Description
Loop Transmit Message bytes)
Address: Abbreviation: MXL1EOCH Read/Write Table Loop Message (High Byte)
<7:5> <4:0> Name EOC<1:5> Default used; Always read Low. Loop <1:5> Description
HDSL Framer/Mapper 1168 kbps Applications LXP710
Address: Abbreviation: MXL1EOCL Read/Write Table Loop Message (Low Byte)
<7:0> Name EOC<6:13> Default Loop <6:13> Description
Loop User Indicator Register
Address: Abbreviation: MXL1UIB Read/Write Table Loop Bits
Name RRBE RCBE REGA INDC/R UIB1 UIB2 Default used; Always read Low. loop regenerator remote block error. loop regenerator central block error. loop internal alarm regenerator. loop remote terminal alarm. loop ready receive indicator LTU/NTU. loop 1uib loop Description
Demux Loop Registers Bytes)
Address: Abbreviation: DXL1Z1 Read Table Demux Loop Bits (LSB)
<7:0> Name Z<1:8> Default Demux Loop <1:8> Description
Address: Abbreviation: DXL1Z2 Read
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table Demux Loop Bits
<7:0> Name Z<9:16> Default Demux Loop <9:16> Description
Address: Abbreviation: DXL1Z3 Read Table Demux Loop Bits
<7:0> Name Z<17:24> Default Demux Loop <17:24> Description
Address: Abbreviation: DXL1Z4 Read Table Demux Loop Bits
<7:0> Name Z<25:32> Default Demux Loop <25:32> Description
Address: Abbreviation: DXL1Z5 Read Table Demux Loop Bits
<7:0> Name Z<33:40> Default Demux Loop <33:40> Description
Address: Abbreviation: DXL1Z6 Read Table Demux Loop Bits (MSB)
<7:0> Name Z<41:48> Default Demux Loop <41:48> Description
Demux Loop Transmit Message bytes)
Address:
HDSL Framer/Mapper 1168 kbps Applications LXP710
Abbreviation: DXL1EOCH Read Table Demux Loop Message (High Byte)
<7:5> <4:0> Name EOC<1:5> Default used; Always read Low. Demux Loop <1:5> Description
Address: Abbreviation: DXL1EOCL Read Table Demux Loop Message (Low byte)
<7:0> Name EOC<6:13> Default Demux Loop <6:13> Description
Demux Loop User Indicator Register
Address: Abbreviation: DXL1UIB Read Table Demux Loop Bits
Name RRBE RCBE REGA INDC/R UIB1 UIB2 Default used; Always read Low. Demux loop regenerator remote block error. Demux loop regenerator central block error. Demux loop internal alarm regenerator. Demux loop remote terminal alarm. Demux loop ready receive indicator LTU/NTU. Demux loop Demux loop Description
Demux Loop Error Counter
Address: Abbreviation: DXL1CRCEC Read
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table Demux Loop Error Count
Name Default Description Demux Loop Error Counter. This 8-bit counter increments each time more errors detected demux Loop CRC-6 bits. After microprocessor read, counter cleared. This counter disabled when LOSW1 signal High, automatically stops 0FFh prevent overflow.
<7:0>
CRC1EC<7:0>
Demux Loop FEBE Error Counter
Address: Abbreviation: DXL1FEBEEC Read Table Demux Loop FEBE Error Count
Name Default Description Demux Loop FEBE Error Counter. This 8-bit counter increments each time more errors detected demux Loop FEBE bits. After microprocessor read, counter cleared. This counter disabled when LOSW1 signal High, automatically stops 0FFh prevent overflow.
<7:0>
FEBE1EC<7:0>
Demux Loop Error Counter
Address: Abbreviation: DXL1BPVEC Read Table Demux Loop Error Count
Name Default Description Demux Loop Error Counter. This 8-bit counter increments each time more errors detected demux Loop bits. After microprocessor read, counter cleared. This counter disabled when LOSW1 signal High, automatically stops 0FFh prevent overflow.
<7:0>
BPV1EC<7:0>
Loop QRSS Test Pattern Error Counter bytes)
Address: Abbreviation: L1PATECH Read
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table Loop QRSS Test Pattern Error Counter (High byte)
Name Default Description Loop Test Pattern Error Counter (High byte). This 16-bit counter increments each time demux test pattern receiver detects pattern error. When upper byte read, current count both bytes latched counter cleared. This counter disabled when pattern sync lost. This counter does stop counting 0FFFFh, however, latched overflow status provided General Interrupt Vector Status register.
<7:0>
PAT1ECH <15:8>
Address: Abbreviation: L1PATECL Read Table Loop QRSS Test Pattern Error Counter (Low)
<7:0> Name PAT1ECL <7:0> Default Description Loop Test Pattern Error Counter (Low byte). lower byte latched when upper byte read. Therefore, this byte must read last when reading 16-bit Pattern Error Counter.
Loop Restart Counter
Address: Abbreviation: DX1RSCNTR Read Table Loop Restart Counter
<7:0> Name Default Description Loop Restart Counter. Increments each time loop been restarted. Cleared when read stops FFh.
Loop Register Bytes)
Address: Abbreviation: MXL2Z1 Read/Write Table Loop Bits (LSB)
<7:0> Name Z<1:8> Default Loop <1:8> Description
Address: Abbreviation: MXL2Z2
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Read/Write Table Loop Bits
<7:0> Name Z<9:16> Default Loop <9:16> Description
Address: Abbreviation: MXL2Z3 Read/Write Table Loop Bits
<7:0> Name Z<17:24> Default Loop <17:24> Description
Address: Abbreviation: MXL2Z4 Read/Write Table Loop Bits
<7:0> Name Z<25:32> Default Loop <25:32> Description
Address: Abbreviation: MXL2Z5 Read/Write Table Loop Bits
<7:0> Name Z<33:40> Default Loop <33:40> Description
Address: Abbreviation: MXL2Z6 Read/Write Table Loop Bits (MSB)
<7:0> Name Z<41:48> Default Loop <41:48> Description
HDSL Framer/Mapper 1168 kbps Applications LXP710
Loop Transmit Message bytes)
Address: Abbreviation: MXL2EOCH Read/Write Table Loop Message (High byte)
<7:5> <4:0> Name EOC<1:5> Default used; Always read Low. Loop <1:5> Description
Address: Abbreviation: MXL2EOCL Read/Write Table Loop Message (Low byte)
<7:0> Name EOC<6:13> Default Loop <6:13> Description
Loop User Indicator Register
Address: Abbreviation: MXL2UIB Read/Write Table Loop Bits
Name RRBE RCBE REGA INDC/R UIB1 UIB2 Default used; Always read Low. loop regenerator remote block error. loop regenerator central block error. Loop internal alarm regenerator. loop remote terminal alarm. loop ready receive indicator LTU/NTU. loop loop Description
Demux Loop Register Bytes)
Address: Abbreviation: DXL2Z1
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Read Table Demux Loop Bits (LSB)
<7:0> Name Z<1:8> Default Demux Loop <1:8> Description
Address: Abbreviation: DXL2Z2 Read Table Demux Loop Bits
<7:0> Name Z<9:16> Default Demux Loop <9:16> Description
Address: Abbreviation: DXL2Z3 Read Table Demux Loop Bits
<7:0> Name Z<17:24> Default Demux Loop <17:24> Description
Address: Abbreviation: DXL2Z4 Read Table Demux Loop Bits
<7:0> Name Z<25:32> Default Demux Loop <25:32> Description
Address: Abbreviation: DXL2Z5 Read Table Demux Loop Bits
<7:0> Name Z<33:40> Default Demux Loop <33:40> Description
HDSL Framer/Mapper 1168 kbps Applications LXP710
Address: Abbreviation: DXL2Z6 Read Table Demux Loop Bits (MSB)
<7:0> Name Z<41:48> Default Demux Loop <41:48> Description
Demux Loop Transmit Message bytes)
Address: Abbreviation: DXL2EOCH Read Table Demux Loop Message (High byte)
<7:5> <4:0> Name EOC<1:5> Default used; Always read Low. Demux Loop <1:5> Description
Address: Abbreviation: DXL2EOCL Read Table Demux Loop Message (Low byte)
<7:0> Name EOC<6:13> Default Demux Loop <6:13> Description
Demux Loop User Indicator Register
Address: Abbreviation: DXL2UIB Read Table Demux Loop Bits
Name RRBE RCBE REGA Default used; Always read Low. DemuX loop regenerator remote block error. Demux loop regenerator central block error. Demux loop internal alarm regenerator. Description
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table Demux Loop Bits (Continued)
Name INDC/R UIB1 UIB2 Default Description Demux loop remote terminal alarm. Demux loop ready receive indicator LTU/NTU. Demux loop Demux loop
Demux Loop Error Counter
Address: Abbreviation: DXL2CRCEC Read Table Demux Loop Error Count
Name Default Description Demux Loop Error Counter. This 8-bit counter increments each time more errors detected demux Loop CRC-6 bits. After microprocessor read, counter cleared. This counter disabled when LOSW2 signal High, automatically stops 0FFh prevent overflow.
<7:0>
CRC2EC<7:0>
Loop FEBE Error Counter
Address: Abbreviation: DXL2FEBEEC Read Table Demux Loop FEBE Error Count
Name Default Description Demux Loop FEBE Error Counter. This 8-bit counter increments each time more errors detected demux Loop FEBE bits. After microprocessor read, counter cleared. This counter disabled when LOSW2 signal High, automatically stops 0FFh prevent overflow.
<7:0>
FEBE2EC<7:0>
Loop Error Counter
Address: Abbreviation: DXL2BPVEC Read
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table Demux Loop Error Count
Name Default Description Demux Loop Error Counter. This 8-bit counter increments each time more errors detected demux Loop bits. After microprocessor read, counter cleared. This counter disabled when LOSW2 signal High, automatically stops 0FFh prevent overflow.
<7:0>
BPV2EC<7:0>
Loop QRSS Test Pattern Error Counter bytes)
Address: Abbreviation: L2PATECH Read Table Loop QRSS Test Pattern Error Counter (High byte)
Name Default Description Loop Test Pattern Error Counter (High byte). This 16-bit counter increments each time demux test pattern receiver detects pattern error. When upper byte read, current count both bytes latched counter cleared. This counter disabled when pattern sync lost. This counter does stop counting 0FFFFh, however, latched overflow status provided General Interrupt Vector Status register.
<7:0>
PAT2EC<15:8>
Address: Abbreviation: L2PATECL Read Table Loop QRSS Test Pattern Error Counter (Low byte)
<7:0> Name PAT2EC<7:0> Default Description Loop Test Pattern Error Counter (Low byte). lower byte latched when upper byte read. Therefore, this byte must read last when reading 16-bit Pattern Error Counter.
Loop Restart Counter Register
Address: Abbreviation: MX2RSCNTR Read Table Loop Restart Counter
<7:0> Name Default Description Loop restart counter. Increments each time loop been restarted.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Loop Register Bytes)
Address: Abbreviation: MXL3Z1 Read/Write Table Loop Bits (LSB)
<7:0> Name Z<1:8> Default Loop <1:8> Description
Address: Abbreviation: MXL3Z2 Read/Write Table Loop Bits
<7:0> Name Z<9:16> Default Loop <9:16> Description
Address: Abbreviation: MXL3Z3 Read/Write Table Loop Bits
<7:0> Name Z<17:24> Default Loop <17:24> Description
Address: Abbreviation: MXL3Z4 Read/Write Table Loop Bits
<7:0> Name Z<25:32> Default Loop <25:32> Description
Address: Abbreviation: MXL3Z5 Read/Write
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table Loop Bits
<7:0> Name Z<33:40> Default Loop <33:40> Description
Address: Abbreviation: MXL3Z6 Read/Write Table Loop Bits (MSB)
<7:0> Name Z<41:48> Default Loop <41:48> Description
Loop transmit Message bytes)
Address: Abbreviation: MXL3EOCH Read/Write Table Loop Message (High byte)
<7:5> <4:0> Name EOC<1:5> Default used; Always read Low. Loop <1:5> Description
Address: Abbreviation: MXL3EOCL Read/Write Table Loop Message (Low byte)
<7:0> Name EOC<6:13> Default Loop <6:13> Description
Loop User Indicator Register
Address: Abbreviation: MXL3UIB Read/Write
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table Loop Bits
Name RRBE RCBE REGA INDC/R UIB1 UIB2 Default used; Always read Low. loop regenerator remote block error. loop regenerator central block error. loop internal alarm regenerator. loop remote terminal alarm. Loop ready receive indicator LTU/NTU. loop loop Description
Demux Loop Register Bytes)
Address: Abbreviation: DXL3Z1 Read Table Demux Loop Bits (LSB)
<7:0> Name Z<1:8> Default Demux Loop <1:8> Description
Address: Abbreviation: DXL3Z2 Read Table Demux Loop Bits
<7:0> Name Z<9:16> Default Demux Loop <9:16> Description
Address: Abbreviation: DXL3Z3 Read Table Demux Loop Bits
<7:0> Name Z<17:24> Default Demux Loop <17:24> Description
HDSL Framer/Mapper 1168 kbps Applications LXP710
Address: Abbreviation: DXL3Z4 Read Table Demux Loop Bits
<7:0> Name Z<25:32> Default Demux Loop <25:32> Description
Address: Abbreviation: DXL3Z5 Read Table 100. Demux Loop Bits
<7:0> Name Z<33:40> Default Demux Loop <33:40> Description
Address: Abbreviation: DXL3Z6 Read Table 101. Demux Loop Bits
<7:0> Name Z<41:48> Default Demux Loop <41:48> Description
Demux Loop Transmit Message bytes)
Address: Abbreviation: DXL3EOCH Read Table 102. Demux Loop Message (High byte)
<7:5> <4:0> Name EOC<1:5> Default used; Always read Low. Demux Loop <1:5> Description
Address: Abbreviation: DXL3EOCL Read
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table 103. Demux Loop Message (Low byte)
<7:0> Name EOC<6:13> Default Demux Loop <6:13> Description
Demux Loop User Indicator Register
Address: Abbreviation: DXL3UIB Read Table 104. Demux Loop Bits
Name RRBE RCBE REGA INDC/R UIB1 UIB2 Default used; Always read Low. Demux loop regenerator remote block error. Demux loop regenerator central block error. Demux loop internal alarm regenerator. Demux loop remote terminal alarm. Demux loop ready receive indicator LTU/NTU. Demux loop Demux loop Description
Demux Loop Error Counter
Address: Abbreviation: DXL3CRCEC Read Table 105. Demux Loop Error Count
Name Default Description Demux Loop Error Counter. This 8-bit counter increments each time more errors detected demux Loop CRC-6 bits. After microprocessor read, counter cleared. This counter disabled when LOSW3 signal High, automatically stops 0FFh prevent overflow.
<7:0>
CRC3EC<7:0>
Demux Loop FEBE Error Counter
Address: Abbreviation: DXL3FEBEEC Read
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table 106. Demux Loop FEBE Error Count
Name Default Description Demux Loop FEBE Error Counter. This 8-bit counter increments each time more errors detected demux Loop FEBE bits. After microprocessor read, counter cleared. This counter disabled when LOSW3 signal High, automatically stops 0FFh prevent overflow.
<7:0>
FEBE3EC<7:0>
Loop Error Counter
Address: Abbreviation: DXL3BPVEC Read Table 107. Demux Loop Error Count
Name Default Description Demux Loop Error Counter. This 8-bit counter increments each time more errors detected demux Loop bits. After microprocessor read, counter cleared. This counter disabled when LOSW3 signal High, automatically stops 0FFh prevent overflow.
<7:0>
BPV3EC<7:0>
Loop QRSS Test Pattern Error Counter bytes)
Address: Abbreviation: L3PATECH Read Table 108. Loop QRSS Test Pattern Error Counter (High byte)
Name Default Description Loop Test Pattern Error Counter (High byte). This 16-bit counter increments each time demux test pattern receiver detects pattern error. When upper byte read, current count both bytes latched counter cleared. This counter disabled when pattern sync lost. This counter does stop counting 0FFFFh, however, latched overflow status provided General Interrupt Vector Status register.
<7:0>
PAT3EC<15:8>
Address: Abbreviation: L3PATECL Read Table 109. Loop QRSS Test Pattern Error Counter (Low byte)
<7:0> Name PAT3EC<7:0> Default Description Loop Test Pattern Error Counter (Low byte). lower byte latched when upper byte read. Therefore, this byte must read last when reading 16-bit Pattern Error Counter.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Loop Restart Counter Register
Address: Abbreviation: MX3RSCNTR Read Table 110. Loop Restart Counter
<7:0> Name Default Description Loop restart counter. Increments each time loop been restarted.
HFMA Version Number
Address: Abbreviation: Read Table 111. HFMA Version Number
<7:4> <3:0> Name Default Silicon version Version 1.1. Other values undefined time printing. Description
Microprocessor Mode Testing Register
Address: Abbreviation: MXTEST Read/Write Table 112. Microprocessor Mode Testing Register
<7:0> Name Default Description Defined manufacturing test only.
Microprocessor Mode Testing Register Demux
Abbreviations: DXTEST Address: Read/Write
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table 113. Microprocessor Mode Testing Register Demux
<7:0> Name Default Description Defined manufacturing test only.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Application information
Target Applications
LXP710 HDSL framer/mapper primarily intended transporting 2.048 traffic over loop systems. data either framed (primarily channelized voice), unframed (primarily data transport). two-loop HDSL system shown Figure service supports 64-kbps channels. Details channels structured found G.704 document. Definition signal found G.703 document. unframed data only transport system shown Figure framing signal supplied, HDSL system must operated line point-to-point mode. Point multipoint operation possible this mode. system Figure also support unframed operation setting LXP710 unframed mode. LXP710 also supports fractional service mode. Fractional service defined when customer supplied with less than channels service. signal delivered still 2.048 kbps with unused channels filled with idle code. Multipoint operation when more NTUs supported (Figure multipoint system always operates loops fractional mode, while fractional service loop NTU. Fractional operation must always framed mode. Unframed operation select which channels appropriate loops.
ETSI Compliant Operation
Many OEMs supply transport systems that must meet ETSI compliance found ETR(ETS)-152. LXP710 supports loop full three loop fractional operation. LXP710 forms HDSL frame format Table each loop provides access overhead bits loops independently. This necessary sufficient make piece equipment ETSI compliant. Other issues involve start process between NTU. (ETS) document describes this process. Also SK70707/8 data sheet data pump activation fits into ETSI start-up mode. Please contact Intel's Telecom Marketing department software assisting developing HDSL system. CRC-6 calculation method used LXP710 been revised silicon. earlier revisions detect CRC-6 errors, included stuffing bits, contrary ETR-152. revision corrects this, automatically compatible with older revisions. This achieved using UIB1 bit. (See Table page 58.) master unit typically located facility, while typically located facility. this document there references (HTU-C). ETSI designation, where HTU-C ANSI designation. HTU-x references given those readers more familiar with North American equipment nomenclature. Another common name local unit also known remote unit.
HDSL Framer/Mapper 1168 kbps Applications LXP710
User Definable HDSL Overhead Bits
ETSI specifications allocate overhead bits with intent command control between (HTU-C) (HTU-R) units. bits primarily used this; plus three Z-bits loop identification. remaining Z-bits frame loop open use. This yields kbps channel loop both directions data quality voice. ETSI compliance needed, then additional bits frame bring this value kbps. This extra channel accessible microprocessor with interrupts provided frame rate loop coordinate writing reading this channel. point-to-point system could pair these channels provide kbps channel ETSI compliant, kbps ETSI compliant channel.
Figure Two-Loop HDSL System
Microprocessor
Line
RSER RFSYNC RTIP RPOS RRING RNEG RCLK RPOS RNEG RCLK SK70707/8 TCLK TPOS TNEG Data Pump TPOS TNEG TCLK TSER TFSYNC E1CLKO E1DATO E1FRMO ICLK2 LOSW2 RFP2 LP2DTI TFP2 LXP710 LP2DTO ICLK LOSW RDATA TDATA SK70704 E1DATI E1FRMI E1CLKI LP1DTO TFP1 LP1DTI RFP1 LOSW1 ICLK1 TDATA RDATA LOSW ICLK
SK70704
TTIP TRING
HDSL Lines
LXT305A
DS2181A Framer
SK70707/8 Data Pump
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Figure Unframed Data Transport Operation
Microprocessor
E1FRMI RDATA RTIP RRING RCLK E1DATI E1CLKI BPVI LOSDI E1CLKO E1DATO
LP1DTO TFP1 LP1DTI RFP1 LOSW1 ICLK1
TDATA RDATA LOSW ICLK SK70707/8 Data Pump
SK70704
Line
TCLK TTIP TRING TDATA LXT350/360
HDSL Lines
ICLK2 LOSW2 RFP2 LP2DTI TFP2 LP2DTO ICLK LOSW RDATA TDATA
E1FRMO
LXP710
SK70704
SK70707/8 Data Pump
HDSL Framer/Mapper 1168 kbps Applications LXP710
Figure Point-to-Multipoint HDSL System
Microprocessor
Line
RSER RFSYNC RTIP RPOS RRING RNEG RCLK RPOS RNEG RCLK E1DATI E1FRMI E1CLKI LP1DTO TFP1 LP1DTI RFP1 LOSW1 ICLK1 TDATA RDATA LOSW ICLK SK70707/8 TCLK TPOS TNEG Data Pump TPOS TNEG TCLK TSER TFSYNC E1CLKO E1DATO E1FRMO ICLK2 LOSW2 RFP2 LP2DTI TFP2 LP2DTO ICLK LOSW RDATA TDATA
SK70704
TTIP TRING
HDSL Lines
LXT305A
DS2181A Framer
SK70704
SK70707/8 Data Pump
ICLK3 LOSW3 RFP3 LP3DTI TFP3 LP3DTO
ICLK LOSW RDATA TDATA
SK70704
LXP710
SK70707/8 Data Pump
System Software Guidelines
Many implementations HDSL systems contain microprocessor board which controls operation framer three data pumps. This processor usually also communicates with another rack that contains board. Though there other possibilities, this usually good compromise providing necessary computing power local control devices board. first glance software required HDSL system seems complex, let's break down some operational modes. These modes board initialization, loop activation, normal operation, diagnostic operation external communication mode. following discussion outlines major tasks needed HDSL system, details necessary complete system.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
4.4.1
Board Initialization
This usually first code which initializes microprocessor which turn writes desired starting values registers devices board. Configuration switches read determine whether board unit, full fractional, etc. After this phase complete board communicate with master controller rack. This necessary receive channel configuration report status loop. decide whether should automatically activate loops wait explicit command from rack controller.
4.4.2
Loop Activation
This phase prepares loops carry payload, this case data. data pumps must through sophisticated process training receivers echo cancellation, channel equalization level slicing adjustment. Fortunately Intel data pumps this automatically just setting Activation Request Control register. When Active State Status register set, this process complete. Interrupt generation used free processor from polling determine completion. Intel data pumps also automatically detect correct TIP/RING polarity reversal wire pair connection. Once data pumps able pass data, framers take over establish communication between NTU. first step establish that loop wire pairs connected correctly. sets Z-bits indicate loop identification. This done writing Z-bit registers. receives loop individual loops checks they correct, then framer must switch data paths internally match then loop back when this process complete. loop reversal detect switch done automatically LXP710 setting LPRENx bits TSCTL (06h) register during board initialization phase. second step each side indc/r when ready receive data. loop time slot control bytes must set. Default values stored boards loaded power Alternately could receive assignment from rack master and, after receiving indr from NTU, send configuration using unused Z-bits. Each loop could receive assignment loop. There standard time slot assignments made remotely must take care consistent future equipment designs maintain interoperability.
4.4.3
Normal Operation
Payload data transported both sides this mode. Additionally this mode monitors condition HDSL system. Operational characteristics such signal-to-noise ratio (SNR), loss signal (LOS) errors tracked each loop anticipate problems. LOSW from data pump definite indication that loop malfunctioning corrective action must taken. When symptoms indicate that corrective actions needed, HDSL system should make changes gracefully minimize effect link. instance HDSL loop failures should continually cycle through activation attempts, while should QUIET, time-
HDSL Framer/Mapper 1168 kbps Applications LXP710
then wait activation sequence. instances local lightning cable cut, system recover when lightning transient dies down, when cable spliced. Point-to-point systems program LXP710's automatic loop swap feature maintain operation selected channels surviving loop when primary loop cut. rack systems, should report abnormalities rack master. Local unit problems defined terms errors from either local HDSL interface. Remote units also experience errors. needs appropriate bits HDSL loop. rta, remote terminal alarm, used when other appropriate. Then interrogate through bits determine problem. (ETS) defines protocol certain actions performed, leaves open many register definitions. Again implementations will differ.
4.4.4
Diagnostic Operation
diagnostic mode used when system installed ensure proper operation troubleshoot operational system. into loopback modes isolate sections system performance measurement troubleshooting. Payload transport operation shut limited this mode. HDSL system should designed minimize impact properly operating loop when working failed one. LXP710 provides features change loop timing source maintain proper timing.
4.4.5
External Communication
This usually background mode rack systems. must protocol supply with configuration information receive diagnostic data from external system support remote performance monitoring command loopbacks, error injections, etc. This also provides option upgrade HDSL system's application software contained FLASH EPROM, taking care alter board bootload software.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table 114. HDSL Frame Structure Pair Point-to-Point System
Time Frame 1:14 17:1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767:3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517:5256 5257 1:14 Symbol SW<1:14> losd febe B01:B12 eoc01 eoc02 eoc03 eoc04 crc1 crc2 eoc05 B13:B24 eoc06 eoc07 eoc08 eoc09 crc3 crc4 rrbe rcbe rega B25:B36 eoc10 Description Sync word Loss input signal application interface block error Payload block 1:12 address address data/opcode Odd/Even Byte Cyclic redundancy check Cyclic redundancy check power status power status Bipolar violation unspecified Payload blocks 13:24 message message message message Cyclic redundancy check Cyclic redundancy check Regenerator present Regenerator remote block error Regenerator central block error Regenerator alarm Payload blocks 25:36 message CRC-6 CRC-6 HDSL payload including Zm25:Zm36 HDSL payload including Zm13:Zm24 CRC-6 CRC-6 only only HDSL payload including Zm1:Zm12 Notes Double barker code
HDSL Framer/Mapper 1168 kbps Applications LXP710
Table 114. HDSL Frame Structure Pair Point-to-Point System (Continued)
Time Frame 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267:7006 1/584 7007 7008 nominal 7009 7010 1/584 Symbol eoc11 eoc12 eoc13 crc5 crc6 indc/indr uib1 uib2 B37:B48 stq1s stq1m stq2s stq2m Description message message message Cyclic redundancy check Cyclic redundancy check Remote terminal alarm Ready receive Unspecified indicator Unspecified indicator Payload blocks 37:48 Stuff quat sign Stuff quat magnitude Stuff quat sign Stuff quat magnitude HDSL payload including Zm34:Zm48 Frame stuffing Frame stuffing Frame stuffing Frame stuffing CRC-6 CRC-6 only indc=LTU indr=NTU Notes
times listed relate last previous line.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Figure Frame Structure Pair Point-to-Point System
1/584) 1/584) 3503 3505 quats 12*72 1/2=870q 870q 870q 870q 0/2q
Sync. Word
HBBB
Sync. Word
HDSL Payload block HDSL Frame) Pair
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Byte Byte Byte Byte Byte Byte
Pair
Byte Byte Byte Byte Byte Byte
bits, quats bits/
Symbol B01:B48 Byte quat Sync word
Description HDSL system payload blocks. Byte from core frame 1:144). HDSL overhead (sw, eoc, crc,.). Quaternary symbol. Stuff quats. 7-symbol Barker codes. "Double Barker" bits. 1/584 1/584 Additional overhead bits bits). Indicates corresponding pair 1:2). Indicates number payload blocks 1:48).
HDSL Framer/Mapper 1168 kbps Applications LXP710
Note:
Test Specifications
minimum maximum values Table through Table Figure through Figure represent performance specifications LXP710 guaranteed test except, where noted, design.
Table 115. Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output current Storage temperature Symbol tSTOR -0.3 +6.0 +0.3 +150 Unit
Table 116. Recommended Operating Conditions
Parameter supply Ambient operating temperature Symbol 4.75 5.25 Unit
Table 117. Electrical Characteristics
Parameter Supply current (full operation) Input voltage Input High voltage Output voltage Output High voltage Input leakage current2 Tristate leakage current
CLREF
0.64 0.64
Typ1
0.14 0.06
Unit
Test Conditions
Input capacitance (individual pins) Load capacitance (REFCLK output)
Typical values design only; guaranteed subject production testing.
Table 118. Interface Input Timing Specifications (Figure
Parameter Setup time E1DATI E1FRMI Hold time E1DATI E1FRMI E1CLKI period Typ1 Unit Test Conditions Referenced from falling edge E1CLKI. Referenced from falling edge E1CLKI.
Typical values design only; guaranteed subject production testing.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Table 118. Interface Input Timing Specifications (Figure
Parameter E1CLKI pulse width E1CLKI pulse width High E1CLKI rise time E1CLKI fall time tPWL tPWH Typ1 Unit Test Conditions
Typical values design only; guaranteed subject production testing.
Figure Interface Input Timing
tPWL
tPWH
E1CLKI E1DATI, E1FRMI
Table 119. Interface Output Timing Specifications (Figure
Parameter Output delay time E1DATO E1FRMO E1CLKO period E1CLKO pulse width E1CLKO pulse width High E1CLKO rise time E1CLKO fall time tPWL tPWH Typ1 Unit Test Conditions Referenced from rising edge E1CLKO.
Typical values design only; guaranteed subject production testing.
HDSL Framer/Mapper 1168 kbps Applications LXP710
Figure Interface Output Timing
tPWH
tPWL
E1CLKO
E1DATO, E1FRMO
Table 120. HDSL Interface Input Timing Specifications (Figure
Parameter Setup time LP<1:3>DTI, RFP<1:3> Hold time LP<1:3>DTI, RFP<1:3> Typ1 Unit Test Conditions Referenced from rising edge ICLK1. Referenced from rising edge ICLK1.
Typical values design only; guaranteed subject production testing.
Figure HDSL Interface Input Timing
ICLK1
LP<1:3>DTI, RFP<1:3>
Table 121. HDSL Interface Output Timing Specifications (Figure
Parameter Output delay time LP<1:3>DTO, TFP<1:3> Typ1 Unit Test Conditions Referenced from falling edge ICLK1.
Typical values design only; guaranteed subject production testing.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Figure HDSL Interface Output Timing
ICLK1
LP<1:3>DTO, TFP<1:3>
Table 122. Microprocessor Write Cycle Specifications-Motorola Mode (Table
Parameter Address setup time D<0:7> setup time Data-In hold time from Allowable width Allowable assertion delay after Allowable width tASU tDSU tDHT tCPW tRSU tDPW Typ1 Unit Test Conditions
Typical values design only; guaranteed subject production testing.
HDSL Framer/Mapper 1168 kbps Applications LXP710
Figure Microprocessor Write Cycle-Motorola Mode
tASU
Address (A<0:6>)
tDSU
D<0:7>
tDHT
tCPW
tRSU
tDPW
Table 123. Microprocessor Read Cycle Specifications-Motorola Mode (Figure
Parameter D<0:7> valid after D<0:7> keep valid after negation Typ1 Unit Test Conditions
Typical values design only; guaranteed subject production testing.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Figure Microprocessor Read Cycle-Motorola Mode
Address (A<0:6>)
D<0:7>
Table 124. Microprocessor Write Cycle Specifications-Intel Mode (Figure
Parameter Address setup time D<0:7> setup time D<0:7> hold time after rising edge Allowable width Allowable width Allowable falling edge before rising tASU tDSU tDHT tCPW tRPW tWSU Typ1 Unit Test Conditions
Typical values design only; guaranteed subject production testing.
HDSL Framer/Mapper 1168 kbps Applications LXP710
Figure Microprocessor Write Cycle-Intel Mode
tASU
Address (A<0:6>)
tDSU
D<0:7>
tDHT
tCPW
(R/W)
tWPW tWSU
Table 125. Microprocessor Read Cycle Specifications-Intel Mode (Figure
Parameter D<0:7> valid after assertion D<0:7> keep valid after negation Allowed width Allowed width Address setup time assertion tDATA tDATN tCPW tRPW tASU Typ1 Unit Test Conditions
Typical values design only; guaranteed subject production testing.
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Figure Microprocessor Read Cycle-Intel Mode
tASU
Address (A<0:6>)
(DS)
tCPW
tRPW tDATA
D<0:7>
tDATN
HDSL Framer/Mapper 1168 kbps Applications LXP710
Figure Peak Output Jitter Performance
Peak Jitter
G.823 Output Jitter Limit (B1)
0.25 0.20
Output Jitter (fast mode) G.823 Output Jitter Limit (B2)
Output Jitter (slow mode) .0625
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Figure Output Wander Performance
(10-2S+10000)
10-11
MTIE (ns)
Proposed ETSI Spec 03036 Version (ETR-152
estimated wander
Measured MTIE
10-1
10-3
10-2
10-1
1010
Observation period(S) MTIE versus observation period output network node
Table 126. ETSI Maximum Wander Values
MTIE 2000 433t
Observation Interval 0.05 2000 2000
0.01t
HDSL Framer/Mapper 1168 kbps Applications LXP710
Figure Typical Jitter Transfer Results
JitterTransferSpec JitterTransferResult
Frequency
Includes effects Jitter Attenuator.
Figure Jitter Transfer Measurement Setup
(HTU-C)
(HTU-R)
Anritsu MP-1550A
LXP710 HDSL Framer/Mapper 1168 kbps Applications
Figure Typical Jitter Tolerance Results
JitterTolSpec JitterTolerance
Frequency
Includes effects Jitter Attenuator.
Figure Jitter Tolerance Measurement Setup
(HTU-C)
(HTU-R)
Anritsu MP-1550A
HDSL Framer/Mapper 1168 kbps Applications LXP710
Mechanical Specifications
Figure Plastic Leaded Chip Carrier Package Specification
LXP710PE
84-pin PLCC Extended Temperature Range (-40
Inches 1.185 1.150 0.018 0.167 0.098
Millimeters 0.181 0.110 4.242 2.490
4.598 2.794
0.050 (nominal) 0.028 1.195 1.158
1.27 (nominal) 0.711 30.099 29.210 0.457 30.353 29.412
BSC-Basic Spacing between Centers
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