84041 84045 CHIPSet Data Book Revision Copyright Notice Copy
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CS4041 CHIPSet
84041 84045 CHIPSet
Data Book Revision
Copyright Notice Copyright© 1994 1995 Chips Technologies, Inc. RIGHTS RESERVED. This manual copyrighted Chips Technologies, Inc. reproduce, transmit, transcribe, store retrieval system, translate into language computer language, form means, electronic, mechanical, magnetic, optical, chemical manual, otherwise, part this publication without express written permission Chips Technologies, Inc. Restricted Rights Legend Use, duplication, disclosure Government subject restrictions forth subparagraph (c)(1)(ii) Rights Technical Data Computer Software clause 252.277-7013. Trademark Acknowledgment CHIPS Logotype, CHIPSlink, CHIPSPort, ELEAT, LeAPSet, NEAT, NEATsx, PEAK, SCAT, SuperMathDX, Wingine registered trademarks Chips Technologies, Inc. Printgine, SuperState, SuperMath, WinPC XRAM Video Cache trademarks Chips Technologies, Inc. IBM®, registered trademarks International Business Machines Corporation. IBM® PS/2, Micro Channel, Enhanced Graphics Adapter, Color Graphics Adapter, Video Graphics Adapter, Color Display Color Display Monochrome Display trademarks International Business Machines Corporation. VESA® registered trademark Video Electronics Standards Association. VL-Bus trademark Video Electronics Standards Association. other trademarks property their respective holders. Disclaimer This document provided general information customer. Chips Technologies, Inc., reserves right modify information contained herein necessary customer should ensure that most recent revision document. CHIPS makes warranty products bears responsibility errors which appear this document. customer should notice that field personal computers subject many patents held different parties. Customers should ensure that they take appropriate action that their products does infringe upon patents. policy Chips Technologies, Inc. respect valid patent rights third parties infringe upon assist others infringe upon such rights.
Subject change without notice
CS4041 CHIPSet
Local
VESA Local Compatible Full Write Back Cache Support LDEV#s sets LREQ# LGNT# pairs provided directly Read write bursting from Masters supported DRAM Controller banks DRAMs supported double banks SIMMs, etc.) Page mode page interleave 256K, deep DRAMs supported Direct Drive Direct drive CAS, DWE, DRAM chips Hidden refresh with staggered memory support Variety timing modes system optimization Cache Controller Direct mapped, external tag, internal comparator byte line size 64K, 128K, 256K, 512K size Write back Write through
Single bank dual bank (word interleaved) cache Multiple timing modes supported cost performance tradeoff Power Management support Many power management features utilized without Internal Clock switching stopping Intel, AMD, Cyrix support Event monitoring restart capability Integrated Local Requires only Support drives connectors) Data port accesses accelerated local accesses Timing modes selectable each drive Keyboard Controller Integrated state machine based keyboard controller Mouse port included Keylock input provided multifunction
Optional
Cache
DRAM 4041
D0:7 SD8:15
Local
D0:31 A2:31 Control, status
DRAM Cache CTRL
commands XD0:7 MA0:11 SD0:7 SD8:15
Keyboard Mouse SA0:7 SA8:15 SA17:19 SA16, LA16:23
EPROM
4045 SIPC
SD0:7 A8:9 SA17:19 A17:23 Interrupts,
Figure System Block Diagram
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Preliminary
CS4041
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Revision History
Revision History
Revision Date 9/29/93 4/12/94 12/14/94 DJ/st DJ/st Comments First Release: Confidential-NDA Required; Subject change without notice. Second Release: Added Index Register Subject change without notice. Third Release: Added 84041 84045 Diagrams; Added 84041/84045 Absolute Maximum Conditions, Recommended Operations, Characteristics; Added 84041 84045 Mechanical Specifications; Subject change without notice. Fourth Release: Added Characteristics; Numerous minor clarifications corrections. Official Release
1/27/95 2/10/95
DJ/st/bb DH/st
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Table Contents
Table Contents
Introduction
1.1. CPUs Supported 1.2. External Chips
Pinouts
2.1. Descriptions 2.2. 84041 Overview 2.3. 84045 Overview 2.4. 84041 Descriptions 2.5. 84045 Descriptions
Registers
3.1. Ports Configuration Registers 3.2. 84041 Port Addresses 3.3. 84041 Index Configuration Registers 3.4. 84045 Port Addresses 3.5. 84045 Configuration Registers
System Level Functions Cross References
4.1. Clocks 4.2. Reset GATEA20 4.3. Arbitration 4.3.1 Control Link 4.4. Refresh 4.5. Co-processor Logic 4.6. Features 4.7. Local Support 4.8. DRAM controller 4.9. Cache Controller 4.10. Keyboard/Mouse Controller 4.11. Controller 4.12. CPUs Containing Writeback Caches
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CS4041
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Table Contents
4.13. Capabilities Power Management 4.13.1 Clock Control 4.13.2 System Management Mode (SMM)
84041 Functional Description
5.1. DRAM/Cache/ISA Controller Chip 5.2. Clocks 5.2.1. Clock Generating Logic 5.2.2. Clock Inputs 5.3. Reset GATEA20 5.3.1. Reset 5.3.2. Emulated 8042 KBRESET# GATEA20 5.4. Arbitration 5.5. Address Mapping 5.5.1. Addressing 5.5.2. Memory Addressing 5.6. Memory Support 5.6.1. 4041 Memory Details 5.6.2. Additional 4041 Features 5.7. CPUs Supported 5.7.1. Differences 5.7.2. Clock Differences 5.7.3. Cache Options 5.7.4. Connections 5.8. Write Back Cache Snooping 5.9. Secondary Cache Controller 5.9.1. Usage 5.9.2. External Connections 5.9.3. SRAM Requirements 5.9.4. Cacheability 5.9.5. Write Protection 5.9.6. Cache Power-Down 5.9.7. Cache Coherency 5.9.8. Cache Operation 5.9.9. Cache Mode Initialization 5.9.10. Data SRAM Testing 5.10. DRAM Controller 5.10.1. Block Decodes 5.10.2. Address Muxing 5.10.3. Timing Modes 5.10.4. DRAM Refresh 5.10.5. DRAM Parity 5.10.6. Alternate Master Accesses Master, DMA) 5.10.7. Programming Timing Modes. 5.10.8. Automatic DRAM Sizing Setup
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Table Contents
5.11. 5.11.1. Master Accesses 5.11.2. Master Accesses .116 5.11.3. Master Accesses DRAM Slaves 5.12. Fast 5.12.1. Connections Signal Generation 5.12.2. Cycle Description 5.12.3. Software Considerations 5.13. Multifunction Pins .123 5.13.1. Functions 5.13.2. Cache DRAM Functions .123 5.13.3. VL-Bus Functions 5.13.4. Power Management Functions 5.13.5. Chip Selects I/Os, Misc 5.13.6. Selection 5.14. Power Management 5.14.1. Power Management Techniques 5.14.2. Sources 5.14.3. Timing Modes 5.14.4. Activity Monitor Timers 5.14.5. Wake Events 5.14.6. Events Detection 5.14.7. Restart 5.14.8. Power Management Clock Changing 5.15. Internal Keyboard/Mouse Controller .136 5.15.1. Host Commands 5.16. Manufacturing Test Modes
84045 Functional Description .142
6.1. SIPC Chip Overview 6.1.1. 4045 Added Features 6.1.2. Using 4045 place 4035 .143 6.1.3. quick design checklist. 6.2. Clocks 6.2.1. 14.31818 clock 6.2.2. SCLK. .144 6.2.3. Refresh clock generation. 6.2.4. 32.768KHz clock 6.3. Reset 6.3.1. Inhibiting Reset Suspend 6.4. GATEA20 6.5. Arbitration 6.5.1. Arbitration Overview 6.5.2. Master Arbitration 6.5.3. Main Arbitration Logic
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6.6. Performance Control (DeTurbo) 6.7. Refresh. 6.8. 6.9. Functions 6.9.1. Controllers 6.9.2. Interrupt Controllers 6.9.3. Timers 6.9.4. RTC. 6.10. Address Buffers 6.11. Internal Decode configuration register access. 6.11.1. Configurations Registers. 6.11.2. decodes. 6.12. Floating point logic 6.13. Keyboard Mouse Interrupts. 6.14. Port Speaker logic 6.15. Manufacturing Test Modes
Electrical Specifications .164 Mechanical Specifications .170
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CS4041
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List Figures
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 5.10 Figure 5.11 Figure 5.12 Figure 5.13 Figure 5.14 Figure 5.15 Figure 5.16 Figure 5.17 Figure 5.18 Figure 5.19 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure System Block Diagram 84041 Pinout 84045 Pinout Write Back Cache Snoop Cache Data SRAM Connections Cache Power Option Connections Cache Connections Cache Read Cache Read Miss Cache Read Miss, -2-2-2 Cache Writes Cache Write Back Cache Write Cache Write Back Burst Read Timing Modes Burst Write Timing Modes Timing Modes Precharge Timing Modes Refresh cycle Basic Fast Timing. Fast Programmable Parameters .120 Cyrix SMI# Timing Restart Timing WBACK# Timing Hidden Refresh Timing Cycle Timing Interrupt Controller Internal Connections 8254 Timer Internal Connections Timing Waveform Timing Waveform Timing Waveform Timing Waveform Timing Waveform 84041 Packaging Dimensions 84045 Packaging Dimensions
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CS4041
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List Tables
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table 5.8.1 Table Table 5.10 Table 5.11 Table 5.12 Table 5.13 Table 5.14 Table 5.15 Table 5.16 Table 5.17 Table 5.18 Table 5.19 Table 5.20 Table 5.21 Table 5.22 Table 5.23 Table 5.24 Table 5.25 Table 5.26 Table 5.27 Table 5.28: Table 5.29: Table 5.30: Table 5.30.1 Table 5.31 Table 5.32 Table 5.33 Table 5.34 Table 5.34.1 Table 5.35 Table 5.36 Table 5.37 Table 5.38 Table 5.39 84041 List. 84045 List. 84041 84045 Port Summary 84041 84045 Configuration Register Summary Chip Reset Signal Routing Clock Divider GATEA20 KBRESET Source. Owner Indication Decode Lower Mask (A6:0) Decode Upper Mask (A15:7) DRAM Shadow Encoding Programmable Memory Decode Size Placement User/SMM Space Shadow Bits Address Usage Cache Usage Mapping Data SRAM Configurations SRAM Configurations Suggested Cache Timing Modes Speeds Cache Modes. Cache Test Window Location 512K Cache Test Mode Mapping When Lower .104 usage DRAM Block Starting Address DRAM Size Options Address Assignments Interleaving Non-Interleaving Address Multiplexing Staggered Refresh Assignment Suggested DRAM Timing Modes Default signal states Programmable Timing Parameters Determine Which Drive Active Fast Register Drive Speed Selection Register Settings Timing Programming Standard Modes .122 Typical Timing Parameters Multifunction Function Programming Multifunction Programming Registers Status Enable Registers Activity Timer Selectable Functions .129 Time Base Selection Slow Clock Programming Timer Resolutions Time-Outs Event Functions .131 External Event Modes Index Register Event Fixed Address Ranges
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CS4041
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List Tables
Table 5.40 Table 5.41 Table 5.42 Table Table Table
Selectable Ranges Specific Events Power Management Configuration Registers Stabilization Delay Time Timer usage setup Real Time Clock/CMOS addresses SIPC Port bits
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Preliminary
CS4041
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Introduction
Introduction
CS4041 first product GreenCHIPS CHIPSet product portfolio Chips Technologies, Inc. provides system logic implementing high performance, Energy Star compliant PC/AT design, while maintaining extremely competitive cost structure. powerful feature includes CHIPS "standard" system blocks offers level system integration while addressing ever evolving requirements that market place demands. 100% PC/AT compatible directly supports 486DX, 486DX2, 486DX4, 486SX derivatives that support write back cache architecture. high performance CHIPSet consists F84041 Systems Controller F84045 GreenCHIPS IPC. F84041 System Controller packaged 208-pin PQFP integrates major system logic functions. Included F84041 CHIPS patented Page Interleave DRAM controller, high performance cache controller, local controller, controller, power management module, local controller fully compatible 8042 keyboard controller with PS/2 mouse support. companion F84045 packaged PQFP contains industry standard Integrated Peripheral Controller (IPC) which includes controllers, timers, interrupt controllers real time clock. enhanced feature GreenCHIPS DRAM cache controllers perfect today's High Performance PC/AT designs. page interleave DRAM controller offers high performance well extreme flexibility supporting memory subsystems. DRAM controller supports eight banks memory that configured with 256K, memory devices. Page interleaving, timing modes, memory options, direct drive support block block parity support tuned meet most optimum requirements system design. addition, high performance secondary cache controller provides options that optimized performance, cost both. direct mapped cache architecture employs internal comparators with external data SRAM that operate writethrough write-back mode. Cache sizes from supported with flexible single bank dual bank support that allow flexible timing mode selection based speed SRAM speed. "Green" GreenCHIPS comes from Power management support integrated CHIPSet. CS4041 provides perfect level power management support Energy Star compliant desktops. Included power management section direct support operation clock switching popular derivatives. event timers, programmable pins, restart programmable event detection provide wide range options power management selection customization. CS4041 provides levels integration system logic CHIPSets providing local interface keyboard controller. robust local interface decoupled from state machine does local load. interface versatile enough support eight drives allowing each drive have unique command settings. result best performance each drive type allowing significant performance gains over standard interface. This accomplished without compromise standard local bus.
1.1. CPUs Supported
Intel CPUs CPUs Cyrix CPUs CPUs (CPU) write back cache fully supported support (both Intel Cyrix) Clock Frequencies: 25MHz, 33MHz, 40MHz, 50MHz
1.2. External Chips
Parts Basic System LS245 LS245 F244 Cache: F244 IDE: LS245 LS244 DRAM Buffers F244 Used XD0:7 SD0:7 MA2:9 SD8:15 Clock buffer Miscellaneous Cache address W/R# combining Data buffers Control Signal Buffers banks full complement DRAMs. Buffering based loading.
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Preliminary
CS4041
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Introduction
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Preliminary
CS4041
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Pinouts
Pinouts
CS4041 CHIPSet comprised chips, 84041 84045. Following 84041 84045 pinout diagrams descriptions.
Figure 2.1: 84041 Pinout
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Preliminary
CS4041
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Pinouts
Figure 2.2: 84045 Pinout
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Preliminary
CS4041
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Overview
2.1. Descriptions
2.2. 84041 Overview
84041 table below lists pins signal names. detailed functional descriptions 84041 follow list. Table 2.1: 84041 List
Signal CLKIN CLK2OUT SCLKOUT CPUCLK STPCLK# SUSPA# CLK2 SCLK CWS# BUSCLK SYSRESET HLDA DGNT# MASTER# SMIACT# SMIADS# ADS# RDY# BRDY# KEN# FLUSH# BLAST# EADS# HITM# WBACK# BALE MEMR# MEMW# IOR# IOW# IOCHRDY 0WS# MEMCS16# IOCS16# BE0-3# A2-9 A10:16 A17:23 A24:27, SBHE# XA0-1 ROMCS# LDEV0:2# CA3A,B CRDA,B CWEA#,B TAGWE# TAG0:10 In/out Driver (mA) (mA) Ext. Load (pF) External Pull-up Comments From oscillator 4041 CLK2 4041, 4045, (usually buffered) (usually buffered Cyrix Oscillator circuit Oscillator circuit Unbuffered clock Buffer CPU, loc. dev. CPU, loc. dev. CPU, loc. dev. CPU, loc. dev. CPU, loc. dev. CPU, loc. dev. CPU, loc. dev. CPU, loc. dev. 4045 slots CPU, loc. dev. CPU, loc. dev., buffers CPU, loc. dev., buffers CPU, loc. dev., buffers CPU, loc. dev., buffers F245 chip, 8042CS From VL-Bus slots cache RAMs cache RAMs cache RAMs cache RAMs RAMs
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Overview
Table 2.1: 84041 List (continued)
Signal RAS0-7# CAS0-3# DWE# MA0-11 D0:31 DP0:3 XD0:7 SDIR0:1 SDEN# IOCHCK# SMI# INTR IDEIOR# IOEIOW# IDECS0,1# IDEEN# FDD7 LOUT KBCLK, KBDATA MCLK, MDATA GPIOA GPIOB:D Total In/out driver (mA) (mA) Ext. Load (pF) External Pull-up 4.7K 4.7K 4.7K Comments DRAMs DRAMs DRAMs DRAMs CPU, DRAMs, local CPU, DRAMs 8042, ROM, LS245, 4045 F245 F245, inverter 4045 Buffer Buffer Buffer Buffer enables Keyboard connector, etc. Mouse connector
Driver types: tri-state, open collector.
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Preliminary
CS4041
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Overview
2.3. 84045 Overview
84045 table below lists pins signal names. detailed functional descriptions 84045 follows list. Table 2.2: 84045 List
Signal In/out driver (mA) (mA) Ext. Load (pF) External Pull-up Comments
14MX1 14MX2 SCLK PWRGOOD CPURESET SYSRESET HOLD HLDA DGNT# WBACK# LREQ0# LGNT0# MASTER# REFRESH# DREQ0:3, DACK0:3, 5:7# SLOW# LREQ1# FLUSH# LGNT1# MEMR#, MEMW# SMEMR#, SMEMW# IOR#, IOW# IOCHRDY SBHE# SA0:7 A8:9 SA17 LREQ2# SA18 LGNT2# SA19 IOCS# A17:19 A20:23 A20M# TEST# XD0:7 IRQ1, 3:7, 9:11,14:15 IRQ12 INTR FERR# IRQ13 IGNNE#/INTCLR#/RTCIRQ# SPKR 32KX1 32KX2 PSRSTB LOUT Total
14.31818MHz crystal input 14.31818MHz crystal output Oscillator circuit Power supply circuit CPU(s) Coproc, 4025, buffer CPU(s) 4041, buffer direction 4041 Local Master. Pull used Local Master Turbo Button Bus, 4041. Driven cycles only. Bus, 4041. Always driven. Bus, 4041. Driven cycles only. Bus, 4041 Bus, 4041 Bus, F245 CPU, 4041 Master Master decode CPU, 4041. Driven DMA, CPU, 4041. Driven DMA. 4041, LS244, 8042, (IRQ1 from 8042) internal mouse option coprocessor logic coprocessor logic Speaker buffer Crystal Circuit Crystal Circuit circuit 4041 4041
Analog pin. Recommended external crystal circuit should used series, biasing). Totem-Pole, Tri-State, Open Collector.
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CS4041
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Descriptions
2.4. 84041 Descriptions
CLOCKs RESET
CLKIN Input from Oscillator. Either determined powerup (high 2x). Used create CLK2OUT, SCLKOUT (optionally) BUSCLK. Also used time base power management timers. system clock (when CLKIN 2x). full speed mode CLK2OUT buffered version CLKIN. slow mode output clock divider. When CLKIN CLK2OUT will also will same frequency phase SCLKOUT. either mode very skew with respect SCLKOUT CPUCLK. externally back CLK2 4041, other logic requiring clock. system clock everything except CPU. This output buffered back SCLK 4041, goes 4045, VL-Bus. unbuffered SCLKOUT used CWS#. Suspend Acknowledge from Cyrix CPU. left floating used. Required only Cyrix CPUs which contain PLL. This enabled with Configuration Register clock. This output same SCLKOUT except that stopped power management hardware. Stop Clock signal CPU. Used series CPUs stop clock between core. 4041 will optionally drive this before changing clock frequencies. clock input. Used DRAM state machine. also used source clock divider. clock input. Cache Write strobe. This advanced clock used cache write strobe order meet data hold time SRAMs. normally advanced 35nS from SCLK. clock. Generated dividing CLKIN down variety factors. BUSCLK should driven onto through non-inverting buffer. (BALE generated during phase BUSCLK). System reset from 4045.
CLK2OUT
SCLKOUT
SUSPA#
CPUCLK STPCLK#
CLK2 SCLK CWS#
BUSCLK
SYSRESET
Arbitration
HLDA Hold Acknowledge. low, indicates that control local bus. When high, either local master, controller, master bus. 4041 chip generates parity DRAM write cycles when this high. Cache line fills only done when HLDA low. DRAM controller switch timing modes based HLDA provide relaxed timing alternate masters. controller grant. When low, indicates that either controller master control bus. 4041 becomes slave floats commands when this signal low. Preliminary CS4041
DGNT#
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Descriptions
MASTER#
master signal. Indicates that master bus. 4041 uses this determine difference between master cycles. used determining timing IOCHRDY generation.
Local control signals
SMIACT# SMIADS# Indicates memory accesses. function depends type. Intel SMIACT# status signal. Cyrix ADS# cycles. Address Strobe. Input local master cycles, output master cycles. Write/Read status signal. Input local master cycles, output master cycles. Data/Code status signal. Input local master cycles, output master cycles. Memory/IO status signal. Input local master cycles, output master cycles. Burst ready. utput when 4041 slave. Input from local slave external cache controller. Burst Ready. Output when 4041 slave. Input from local slave external cache controller. Cache Enable CPU. Always driven. Only local DRAM cached CPU. Certain areas marked non-cacheable. Flush cache. used when entering SMM. Burst Last. Driven (low) master cycles. External Address Strobe. Used snoop invalidate cache master memory cycles. Floated when local master bus. Optionally driven active writes write protected memory. Modified. Input from indicating that result snoop dirty cache line, i.e., cache contains only valid copy data that alternate master attempting read. also WBACK# below. Writeback. Output 4045 slots based HITM# inpu indicating that needs perform cache writeback operation before alternate master receives data that master attempting read. 4041 determines when allow writeback occur relation other system activity. cycle from alternate master will aborted allow write back data. When 4041 control local (ISA masters DMA) will back while WBACK# low. required protocol, local master (LBM) must capable aborting cycle (without RDY# BRDY#), then restarting cycle again after writeback operation completed. response WBACK#, 4045 drops HOLD long enough give control CPU, then re-asserts HOLD gives control back alternate master after finished writeback operation re-asserted HLDA. Preliminary CS4041
ADS# RDY# BRDY# KEN# FLUSH# BLAST# EADS#
HITM#
WBACK#
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Descriptions
BALE MEMR# MEMW# IOR# IOW# IOCHRDY Buffered Address Latch Enable. Direct drive bus. Memory Read Strobe. Direct drive bus. Output when HLDA LGNT# low. Input when they both high. Memory Write Strobe. Direct drive bus. Output when HLDA LGNT# low. Input when they both high. Read Strobe. Direct drive bus. Output when HLDA LGNT# low. Input when they both high. Write Strobe. Direct drive bus. Output when HLDA LGNT# low. Input when they both high. ready. Output when slave (DMA master accesses local DRAM local slaves). Open collector. Input local master accesses bus. Zero wait state signal. slave will drive this signal when memory command falls force wait state cycle. also used force wait state cycle memory I/O. Output when slave (DMA master accesses local DRAM local slaves). Open collector. Input local master accesses bus. Input local master accesses bus.
0WS#
MEMCS16#
IOCS16#
Address
BE0:3# 160, 159, 158, SBHE# XA0:1 A2:9 Byte enables. Input local master accesses bus. Output master cycles. Generated from XA0:1 SBHE#. BHE#. Output local master accesses bus. Input master cycles. Output local master accesses bus. Input master cycles.
106,
195, 194, 193, 192, 191, 185, 184, Local Address bus. Always inputs.
A10:16
182, 181, 180, 177, 176, 175, Local Address bus. Output cycles. A10:16 address sent XD0:6 from 4045 latched 4041.
A17:23
173, 172, 171, 169, 168, 167, Local Address bus. Always inputs.
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Descriptions
A24:27,
165, 164, 163, 162, Local address. Driven master cycles. Logical chip select 8042 chip select. 8042 chip select active ports chip select programmable. Local Device. local slave cache controller drives these signals indicate that will handle cycle. This signal sampled either first second LDEV1# LDEV2# redefined other inputs. They disabled power LDEV0# enabled power
ROMCS# KBCS# LDEV0:2#
85,86,87
Cache Controller
CA3A, CA3B CRDA#, CRDB# #CWEA, CWEB# TAGWE# TAG0:10 Cache address single bank cache. Upper most data SRAM address (A15,16,17,18,or double bank cache. Cache address each bank double bank cache. CA3A used single bank. Cache Read strobe each bank double bank cache. CRDA# used single bank.
Cache Write strobe each bank double bank cache. CRDA# used single bank. Generated from CWS#. Write enable. Driven during read miss cycles when changing dirty from clean dirty.
201, 200, 199, 198, 197, 196, 190, 189, 188, 187, bits. TAG0 dirty bit. tags supported. TAG0:7 always used tag, TAG0:8 tag. Unused bits must pulled
DRAM Controller
RAS0:7# 151, 150, 149, 148, 155, 154, 153, CAS0:3# each DRAM banks. Direct Drive.
146, 145, 143, CAS0:3 each byte DRAM Direct drive banks DRAM write enable. Direct drive banks DRAM. Also used control direction external DRAM data buffers used.
DWE# MA0:1
140,
MA2:9/XD8:15 138, 137, 136, 132, 131, 130, 129, MA10:11 135, DRAM address/upper data bus. Direct drive banks DRAM. During cycles MA2:9 become XD8:15 respectively (the upper byte data). They buffered with generate SD8:15. MA0:1 10:11 output only. Preliminary CS4041
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Descriptions
Data
D0:7 D8:15 D16:23 D24:31 DP0:3 Local data.
125, 124, 123, DRAM parity bits. Connected DP0:3 also. generates parity when bus. local masters, cycles, masters, 4041 generates parity. Parity checked 4041 cycles.
XD0:7
121, 120, 119, 118, 113, 112, 111, Intermediate data bus. Connected directly 4045, BIOS ROM, 8042, and, through LS245, bus. XD8:15, MA2:9. Direction control XD0:7 SD0:7 (SDIR0) XD8:15 SD8:15 (SDIR1) buffer. 0=SD enable. Connects enable buffers. Goes high disable buffers during local portion master cycles, allowing used DRAMs.
SDIR0:1 SDEN#
Local
IDEIOR# IDEIOW# IDECS0# IDECS1# IDEEN# FDD7 controller read strobe. Driven either loca logic IOR# logic, depending cycle. controller write strobe. Driven either local logic IOR# logic, depending cycle. controller Chip Select Decodes addresses 1F0:1F7 (when default address used). controller Chip Select Decodes addresses 3F6:3F7 (when default address used). driver enable. Connected enable pins drivers. Used floppy disk controller disk change reads. Normally this connected directly SD7. connected directly DSKCHG# floppy connector instead.
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Descriptions
Interrupts
IOCHCK# Parity error indicator from bus. Generates sets IOCHCK# flag. CPU. Generated DRAM parity errors when IOCHCK# gone low. Each these enable bits plus final mask. This also sampled SYSRESET (falling edge) determine whether 4041 will operate clock mode (pin pulled mode (pin pulled down). System Management Interrupt. Output power management logic. INTR from 4045. Used detect system events. Specifically used restart clock when been stopped.
SMI# INTR
Control Link Keyboard
LOUT Control Link input from 4045. Transfers following information: Port Refresh Request, Refresh Complete, Address Strobe. Control Link output 4045. Transfers following information: Interrupt Acknowledge cycle, Reset Request, Refresh Acknowledge, keyboard interrupt (from internal keyboard controller). Keyboard data internal keyboard controller. internal keyboard controller disabled, this signal becomes Gate signal from external 8042. 4041 detects transitions this transmits them 4045 over control link. Keyboard clock internal keyboard controller. internal keyboard controller disabled, this signal becomes reset from external 8042. When this signal goes low, 4041 sends code across control link inform 4045 this. 4045 will perform reset (restart). Mouse data internal 8042. Mouse clock internal 8042.
KBDATA/GATEA20
KBCLK KBRESET#
MDATA MCLK
Multifunction Pins
GPIOA GPIOB GPIOC GPIOD Multifunction pin. Always input. Multifunction pin. Always output. Multifunction pin. Always output. Multifunction pin. Always output.
VCC,
pins) pins) 133, 170, 126, 127, 144, 147, 178, 179,
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CS4041
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Descriptions
2.5. 84045 Descriptions
Clocks
14MX1 14MX2 SCLK 14.31818MHz crystal input. Divided internally 8254 clock inputs. also used source clock. 14.31818MHz crystal output. This buffered externally used signal. clock input. Used arbitration logic, reset generation, selectively divided down make clock.
Resets
PWRGOOD CPURESET SYSRESET From power supply power clear circuit. RESET only. Synchronized SCLK. Connects SRESET series CPU. RESET rest system. same timing CPURESET, only active following PWRGOOD being low. Connects RESET series CPURESET used SRESET.
Arbitration
HOLD HLDA LREQ0# LGNT0# HOLD CPU. Synchronous SCLK. HLDA from CPU. 4045 assumes synchronous SCLK. request from local masters. Arbitrated with other LREQN# signals used) with controllers control bus. Grant local masters. This signal goes give control local master. additional LREQ/LGNT pairs provided multifunction pins. Multiple sets also created externally with PAL. 4045 will optionally preempt local master when unmasked request occurs. controller hold acknowledge output only). Indicates that controller master control bus. Used buffer steering goes 4041. When PWRGOOD SYSRESET high this input select SA17:19 configuration. High SA17:19. alternate functions. This signal used take HOLD clocks regardless state arbitration. used allow with write back cache perform write back following snoop DMA, Master, local master cycle. also floats address lines A8:9, A17:23 cycle progress allow drive these lines. masters pull this signal after gaining control through channel's DREQ DACK# signals. When this signal goes output taken low. refresh signal. 4045 drives this signal during refresh cycles. During refresh cycles while master control bus, master drives low.
DGNT#
WBACK#
MASTER#
REFRESH#
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Descriptions
address enable. High refresh cycles, other times, which includes when CPU, local masters masters have control bus. main function this signal disable decodes system. terminal count. This signal goes high during final cycle transfer. used mainly floppy disk controller, also used other devices.
DREQ0:3 DREQ5:7
requests. channels. channels. used masters, preferred because there less arbitration overhead.
DACK0:3# DACK5:7#
acknowledges. Dual Function pin, determined configuration register. Turbo switch input. slow, high fast. Performance Control registers must before this signal effect. purpose emulate speed 8MHz software (mostly games copy protect schemes) which assume certain execution speed. LREQ1#. Additional VL-Bus master request. Internally arbitrated with other LREQ#s. Dual Function pin, determined configuration register. FLUSH#. This signal, when used, connected FLUSH# pin. used conjunction with performance control. cache optionally flushed each time into HOLD performance control better control speed execution. LGNT1#. Additional VL-Bus master grant.
SLOW# LREQ1#
FLUSH# LGNT1#
(4045)
MEMR# MEMW# SMEMR# Memory Read strobe. Connected directly bus. Output during cycles, input other times generate SMEMR#. Memory Write strobe. Connected directly bus. Output during cycles, input other times generate SMEMR#. Memory Read strobe bottom 1Mbyte. Connected directly bus. Output times. This signal function A20:23 MEMR#, when those signals low. Memory Write strobe bottom 1Mbyte. Connected directly bus. Output times. This signal function A20:23 MEMW#, when those signals low. Write strobe. Connected direc bus. Output during cycles, input other times, access internal I/O. Write strobe. Connected directly bus. Output during cycles, input other times, access internal I/O. Preliminary CS4041
SMEMW#
IOR# IOW#
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Descriptions
IOCHRDY
ready. Input during cycles wait states command strobes. Output during accesses controller registers optionally wait state.
Address (4045)
SBHE# byte high enable. Driven only during cles. (channels 0:3) driven with inverse (channels 5:7) driven low.
SA0:7
address bits 0:7. Direct drive bus. Outputs during cycles refresh cycles. Inputs other times. Local address bits 8:9. Connected local bus. Outputs during cycles. Inputs other times. Dual Function. address SA17. Direct drive bus. Output times except master cycles, where floated. driven from A17. LREQ2#. Additional VL-Bus master request. Internally arbitrated with other LREQ#s. Dual Function. address SA18. Direct drive bus. Output times except master cycles, where floated. driven from A18. LGNT2#. Additional VL-Bus master grant. Dual Function. address SA19. Direct bus. Output times except master cycles, where floated. driven from A19. IOCS#. Internal chip select. When high internal disabled. connected decode A10:15, which provided 4041.
A8:9
SA17 LREQ2#
SA18 LGNT2#
SA19 IOCS#
A17:19
Local address bits 17:19. Connected local bus. Outputs during cycles, inputs drive SA17:19) other times.
A20:23
Local address bits 20:23. Connected local bus. Outputs during cycles, floated other times. Also used inputs generate SMEMR# SMEMW#. Connected A20M# pin. This emulated keyboard GATEA20 fast GATEA20 (port After reset this TEST# input. pulled 4045 will into test mode. becomes A20M# output after configuration been set, which time begins driving ignoring input. pull-up should connected this prevent test mode from being entered keep A20M# high power
A20M# TEST#
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Descriptions
Data (4045)
XD0:7 Data bus. Outputs reads internal registers. Inputs writes internal registers. Also outputs pass A10:16 4041 start cycles.
Interrupts
IRQ1 IRQ3:7 IRQ9:12 IRQ14:15 Interrupt inputs 8259s. Active high. Dual function pin. Normally FERR# from goes internal coprocessor error logic. optionally IRQ13, coprocessor error logic external (for Weitek support). IRQ13 active high.
FERR# IRQ13
IGNNE# INTCLR# RTCIRQ# Dual function pin. Normally IGNNE# comes from internal coprocessor error logic. optionally INTCLR# (active write strobe ports F1), coprocessor error logic external (for Weitek support). When PWRGOOD this provides alarm interrupt output. open collector this time. When alarm occurs, this driven low. INTR Interrupt request CPU.
Timer
SPKR Speaker output. Connected speaker, externally buffered needed adequate speaker drive. When speaker idle (Port '0'), this output remains continuously high. Real time clock 32KHz crystal input. When internal disabled, function this changes become IRQ8# input. logic level IRQ8# causes INTR asserted (high), subject programmed INTC mode. Real time clock 32KHz crystal Output. Real Time clock Power Strobe. This signal being indicates that real time clock lost power. should connected 4045 pins (which receive battery backed power) through 100K resistor, through 0.1uF cap.
32KX1/IRQ8#
32KX2 PSRSTB#
Control Link, Etc. (4045)
Control Link input from 4041. Transfers following information: Interrupt Acknowledge cycle, Reset Request, Refresh Acknowledge, keyboard interrupt (from internal keyboard controller). Control Link output 4041. Transfers following information: Port Refresh Request, Refresh Complete, Address Strobe. Preliminary CS4041
LOUT
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Descriptions
VCC,
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Registers
Registers
3.1. Ports Configuration Registers
Table 3.1: 84041 84045 Port Summary Ports 00-0F 20-21 22-23 26-27 40-43 80-8F A0-A1 C0-DF F0-F1 170-177 1F0-1F7 376-377 3F6-3F7 570-577 5F0-5F7 776-777 7F6-7F7 4041 4045 Description controller DMA). Interrupt Controller (IRQ0-7). Configuration register Address Data Port. Configuration register Address Data Port. Timer Chip (8254). Keyboard Data Mouse port. "Port Keyboard Command/Status port. Real Time Clock Address Port mask. (4041: write only) Real Time Clock Data Port. Page Registers Fast reset GATEA20. Interrupt Controller (IRQ8-15). Controller DMA). Error Reset. (Secondary) (Primary) (Secondary) (Primary) (Fourth) (Third) (Fourth) (Third)
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Registers
Table 3.2: 84041 84045 Configuration Register Summary Indexes 0D-0F 25-27 Revision 4041 4045 Description controller wait states, clock. command delays wait states, address hold. clock selection Performance Control 4045 Misc. Control Clock selection. Arbitration WBACK# control Port feature control (Reserved 4045) DRAM Timing DRAM Setup DRAM Configuration, blocks DRAM Configuration, blocks DRAM block Starting Address DRAM block Starting Address DRAM block Starting Address DRAM block Starti Address Video shadow local control. DRAM shadow read enable. DRAM shadow write enable. ROMCS enable. Shadow enable. DRAM Block Parity Enable Flash shadow enable Secondary DRAM Timing register (Reserved) Secondary Timing Select Register. Cache Controller Mode Cache Controller Configuration Cache Testing Control Data port testing, bits Data port testing, bits 8:10 (Reserved) Decode Address Low. Decode Address High. Decode Size Mask. Decode Configuration. Decode Address Low. Decode Address High. Decode Size Mask. Decode Configuration. Memory Decode Address Low. Memory Decode Address High. Memory Decode Size Destination. Memory Decode Attributes. Memory Decode Address Low. Memory Decode Address High. Memory Decode Size Destination. Memory Decode Attributes. Preliminary CS4041
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Table 3.3: 84041 84045 Configuration Register Summary (continued) Indexes 3A-3B 48:4F 4041 4045 Description Modes 8042 Modes. (Reserved). Multifunction selection register Multifunction selection register General Purpose Output data register General Purpose Input data register (Reserved) IDE. Enables Control Functions Drive Timing Modes Drive Timing Modes Timing Read Write pulse Widths Timing Command Recovery Address Setup Timing Read Write pulse Widths Timing Command Recovery Address Setup (Reserved) IDE. EventA Selection Interrupts. EventA Selection memory accesses WakeA Event Selection Interrupts WakeA Event Selection Memory Accesses EventB Selection WakeB Selection Port Selection Events Interrupt Acknowledge base. TimerA Control Register TimerA Count Register TimerB Control Register TimerB Count Register Time Base Selection Clock Switching modes. Software Commands Status EXT0 EXT1 Mode Status Register Status Register Enable Register Enable Register Modes. Restart Selection Port shadow register
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Port Addresses
3.2. 84041 Port Addresses
Note: "Default" register values refer power-on hardware defaults established automatically following hardware reset, before alternate values have been written BIOS. "Typical" values refer typical settings normal system operation. Addr Bits Description
Configuration register Address Port.
Write only port which holds address Chips Technologies Index register accessed through port This register must written before each access port even same index register being accessed twice row.
Configuration register data.
Accessing this port accesses Configuration register pointed port second access port without writing port between will ignored. Unless otherwise noted register descriptions, reserved undefined index registers should written reserved bits within defined index register should written zero written with same value previously read).
Configuration Register Address Port
Write only. address written here stored separately from port This register used config register index when port read written.
Configuration Register Data Port
Accessing this port accesses Configuration register pointed port second access port without writing port between will ignored. "accessed" separate port 26/27 22/23 windows.
Keyboard Data port.
Used keyboard GATEA20 Fast Reset function.
(Continued next page)
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Port Addresses
Addr
Bits
Description
"Port
This compatible port with miscellaneous information. Bits read/write. Bits read only. Only bits contained 4041. remainder 4045. reads, half bits come from each chip. Default 20h. (Timer gate). This 4045 enables disables 1.19 clock input Timer output from Timer conjunction with below, provides signal speaker. this Timer enabled, programmed will produce square wave programmed frequency. When this below forced speaker output signal will high depending below. (Speaker Data). This 4045. This ANDed with output timer inverted produce signal actually sent speaker. When gate (bit above) low, this gives direct software control speaker. speaker signal will high when this respectively. When speaker idle, bits normally will both speaker output signal will high. Enable Parity Check. enables local DRAM parity checking. disables local DRAM parity checking clears local parity error flip-flop. This inverted sent active preset flip-flop. output PCK# logic. parity error clocks flip-flop There also index register block local DRAM parity errors. prevents flip-flop from being clocked. flip-flop where Preset precedence Clear precedence Enable IOCHCK. enables IOCHCK interrupt. disables IOCHCK clears IOCHCK flip-flop. This inverted sent active clear flip-flop. IOCHCK# sent active Preset input. output logic. output sent this register. flip-flop ALS74 where Preset precedence Clear precedence (Refresh Detect). This 4045. This read only toggles each refresh. should toggle whenever timer produces pulse (about every 15us). This should done even refresh disabled. Some software uses this time delay. (Timer output). This 4045. Read only. This allows software monitor output timer which ANDed with this register inverted produce speaker signal. speaker signal when bits both either speaker output high. setting bits '01', software Timer without generating speaker output. Channel Check latch. indicates that IOCHCK# been activated. This output flip-flop mentioned this register. Parity Check latch. indicates that local parity error occurred. output flipflop mentioned this register.
Port Parity CHCK (Tmr (Ref Detect) chck enable parity enab (spkr data) (tmr2 gate)
Keyboard Command/Status port.
Used keyboard GATEA20 Fast Reset function.
Real Time Clock Address Port mask.
Write only shadow register. Read back through index Mask. This inverted ANDed with sources (the several sources). result function CPU. This allows "Non-Maskable Interrupt" maskable externally.
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Port Addresses
Addr
Bits
Description
Fast reset. Write only 4041. Read 4045 Fast reset. transition activates reset. Detected 4041 redirection SMI. Write only. (Not used 4041). Some these bits contained 4045. Controller Primary Address.
When fast enabled this address, (byte, word, double word access) activates internal state machine. 1F0:1F7 generate IDECS0#. 3F6:3F7 generate IDECS1#. data redirected buffers.
1F0:1F7 3F6:3F7
170:177 376:377
Controller Secondary Address.
When fast enabled this address, (byte, word, double word access) activates internal state machine. 170:177 generate IDECS0#. 376:377 generate IDECS1#. data redirected buffers.
5F0-5F7 7F6:7F7 570-577 776:777
Controller Third Address. Controller Fourth Address.
following ports decoded event detection, etc., actual ports themselves reside externally 4041 (except keyboard, which contained 4041): 170:177 1F0:1F7 2E8:2EF 278:27F 2F8:2FF 3E8:3EF 370:375 376:377 378:37F 3B0:3BB 3BC:3BE 3C0:3DF 3F0:3F5 3F6:3F7 3F8:3FF Keyboard Controller Secondary Primary COM4 COM2 COM3 Secondary Floppy Secondary (monochrome section) (extended color sections) Floppy Primary COM1
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Configuration Registers
3.3. 84041 Index Configuration Registers
Note: Various suggestions programming Configuration Registers included register descriptions. following bits affected type; refer respective descriptions specific programming suggestions: Index bits Index bits through Index Index bits
Index
Bits
Description
command delays Default Typical setting bits each cycle type. BCLK delay (command active falling edge default memory). BCLK delay (default cycles except memory). BCLK delay BCLK delay cycle command delay. Default memory command delay Default memory command delay Default (Reserved). Write
dly0 dly1 dly0 dly1 dly0
Index Function
Wait States, Address hold. Default Typical setting 24h.
(Reserved) wait states BUSCLK wait states (default) BUSCLK wait states. BUSCLK wait states. BUSCLK wait states. wait states BUSCLK wait states (default) BUSCLK wait states. BUSCLK wait states. BUSCLK wait states. (Reserved). address hold time (ready delayed extra clock after command goes inactive). additional hold time (default) additional hold time.
Function wait state hold wait1 wait0 wait1 wait0
Index
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Configuration Registers
Index
Bits
Description
Clock selection. Default
Clock select internal state machine. source clock CLKIN except when 14.3 selected source. internal state machine clock runs twice externally generated BUSCLK rate. CLKIN frequency parenthesis indicates which settings yield 8.00 8.33MHz BUSCLK rate. CLKIN will same frequency when using mode, twice speed when using mode (see CLKIN description). 0000 CLKIN/20 (Power-up default. CLKIN) 0001 CLKIN/16 (133.3 CLKIN) 0010 CLKIN/12 (100 CLKIN) 0011 (Reserved) 0100 (Reserved) 0101 (Reserved) 0110 (Reserved) 0111 14.3 clock input multifunction pin) divided 1000 1001 1010 1011 1100 1101 1110 1111 (Reserved) CLKIN/10 CLKIN/8 CLKIN/6 CLKIN/5 CLKIN/4 CLKIN/3 (Reserved (Reserved CLKIN) (66.7 CLKIN) CLKIN) CLKIN) 33.3 CLKIN) CLKIN)
This register usually follows: CLKIN (CLKIN/3) CLKIN 33.3 (CLKIN/4) CLKIN (CLKIN/5) CLKIN (CLKIN/6) CLKIN 66.7 (CLKIN/8) BUSCLK 14.3 mode requires 14.3 brought into 4041 either LDEV1# pin, Configuration Register programmed select 14.3 MHz.
Index Function clock clk3 clk2 clk1 clk0
08-0F
(4045 chip)
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Configuration Registers
Index
Bits
Description
DRAM Timing
Default Typical setting DRAM 33.3 clock mode, 66.7 CLKIN clock mode. Read Timing Mode. 3-2-2-2 page hits (default) Valid clock mode only. 4-3-3-3 page hits 5-4-4-4 page hits (50MHz) Read cycle timing generated states (1.5 3-2-2-2 mode) after (default) generated states (2.5 3-2-2-2 mode) after (Reserved) Write wait states, single write. wait state writes state minimum cycle) wait state writes state minimum cycle) Precharge Time. states precharge time. states precharge time. Write burst Timing. -2-2-2 burst write timing (default) -3-3-3 burst write timing Refresh pulse width. states states (40MHz 80ns RAMs, 50MHz 80ns RAMs)
width write burst prechg write RAS-CAS read burst1 read burst0
Index Function dram timing
DRAM Setup Default Typical setting interleaving, interleave banks
Interleave bank Should zero bank enabled. bank interleaved, address range doubled active only when interleave (A11 A12) compares. Banks compare interleave banks compare proper interleaving, banks must same size have same starting address. text interleaving more information what must done interleave properly. interleave bank Interleave. Interleave bank Should zero bank enabled. Interleave bank Should zero bank enabled. Interleave bank Should zero bank enabled. (Reserved) DRAM refresh enable. DRAM refresh disabled. refresh handshaking still occur. DRAM refresh enabled. Enable Local DRAM parity. 1=enabled. This provides additional disable parity checking over above Port parity checking occur, both this Port must enabled port 61). mask must also send (I/O port selective parity enabling bank, Index 1Dh.
Function dram setup dram refresh rate
Index
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Index
Bits
Description
DRAM Configuration, blocks Default Typical setting single-bank deep DRAM (4MB total). Block consists banks (RAS0# RAS4#). Block consists banks (RAS1# RAS5#).
Banks DRAM type bank disabled 256K deep DRAMs (256Kx1 256Kx4) deep DRAMs (1Mx1 1Mx4) deep DRAMs (4Mx1 4Mx4) deep DRAMs (16Mx1) (Reserved). (Reserved). banks installed block Bank only (RAS0#) Banks (RAS0# RAS4#) Banks DRAM type definitions same banks banks installed block Bank only (RAS1#) Banks (RAS1# RAS5#)
DRAM Configuration, blocks Default Typical settings: blocks empty, block empty block contains deep dual-bank DRAM (128MB total). Block consists banks (RAS2# RAS6#). Block consists banks (RAS3# RAS7#). Banks DRAM type definitions same banks banks installed block Bank only (RAS2#) Banks (RAS2# RAS6#) Block DRAM type definitions same banks banks installed block Bank only (RAS3#) Banks (RAS3# RAS7#)
#banks1 #banks3 size1 size3 size1 size3 size1 size3 #banks0 #banks2 size0 size2 size0 size2 size0 size2
Index Function dram config dram config
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Configuration Registers
Index
Bits
Description
14-17
DRAM block Starting Address
Default Typical setting lowest addressed block system, block that starts 1MB, Largest blocks should programmed lowest starting addresses. DRAM block Starting address DRAM block Starting address DRAM block Startin address DRAM block Starting address
Index
A27-A20 starting address
Function start start start start
Video area shadow local control. Default Typical setting 80h.
A0000-AFFFF Shadow enable. Access goes bus. Access goes local DRAM. B0000-BFFFF Shadow enab Access goes bus. Access goes local DRAM. Shadow cache disable Shadow cacheable Cache disabled shadow (A0000:FFFFF DRAM). this unless also `1'. (This restriction does apply Index Index Shadow cache disable Shadow cacheable Cache disabled shadow (A0000:FFFFF DRAM). Local time-out time (default) Time enabled LDEV# Sample point. first second This delays start accesses. Shadow Shadow write back Shadow write through (may Write Protect Method. Write protected DRAM cache. Write protected DRAM placed cache, EADS# generated writes. `1', typically should also when using shadow with writeback CPU, unless non-cacheable (see section 5.9.5.1.)
eads local sample local timeout shadow shadow
Index Function shad, etc. wprotmode
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Configuration Registers
Index
Bits
Description
DRAM shadow read enable. Default Typical setting system BIOS video BIOS both shadowed. list below reads corresponding address range come from bus. reads that range come from local DRAM. also Index 1Dh. DRAM shadow write enable. Default Typical setting write-protected shadow RAM. list below writes corresponding address range bus. writes that range local DRAM. also Index 1Dh. ROMCS enable. Default 60h. Typical setting system BIOS (Fxxxxh) extension firmware (Exxxxh) both ROM, system BIOS (Fxxxxh) extension firmware (Exxxxh) video BIOS (C0xxxh-C7xxxh) ROM. reads from that location activate ROMCS#. ROMCS# activated. ROMCS# will activated access directed local DRAM, i.e., indexes have precedence over 1Bh. determines whether activate ROMCS# writes.
assignments registers C0000-C3FFF. C4000-C7FFF. C8000-CBFFF. CC000-CFFFF. D0000-DFFFF. E0000-EFFFF. F0000-FFFFF. Note: Memory read write cycles range FFFx xxxxh (top 1MB) always (ROMCS# generated, cycle timing) regardless value Index 1Bh, WPROT# (Index 3Dh) remains high. 19,1A (Reserved) Activate ROMCS writes also. default=0. activate writes. activate ROMCS# writes addresses selected bits 0-6.
Function shadow shadow ROMCS F0000 F0000 F0000 E0000 D0000 CC000 C8000 C4000 C0000 E0000 D0000 CC000 C8000 C4000 C0000 E0000 D0000 CC000 C8000 C4000 C0000
Index
Index
shadow enable. Default Typical setting 77h. This register used instead registers bits while mode, allowing DRAM enabled only during mode. reads writes from that location come from bus. reads writes from that location come from local DRAM. also Index 1Dh. D0000-DFFFF read enable. E0000-EFFFF read enable. F0000-FFFFF read enable. (Reserved) D0000-DFFFF write enable. E0000-EFFFF write enable. F0000-FFFFF write enable. (Reserved)
Function shad F0000 E0000 D0000 F0000 E0000 D0000
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Configuration Registers
Index
Bits
Description
DRAM Block Parity Enable 32KB Shadow Control. Default Typical setting
enable parity checking four blocks. This register allows parity enabled disabled individual DRAM blocks. Parity checking occurs only corresponding DRAM block enabled Index 13h. also Index 0=Parity checked. 1=Parity checked. Block (RAS0# RAS4#) Block (RAS1# RAS5#) Block (RAS2# RAS6#) Block (RAS3# RAS7#) Bits below provide means enabling shadow with 32KB granularity Exxxxh Fxxxxh ranges. This allows flash programming when only 64KB memory segment available software. Shadow enabled either these bits bits Indexes 1Ah. Unlike 1Ah, these bits enable both reads writes, both user mode SMM. These bits usually should turned before turning bits Indexes make sure that executing program remains accessible. E0000h-E7FFFh Shadow enable. Disabled (shadow controlled Indexes 1Ah). Enable Shadow read write this area both user mode SMM. E8000h-EFFFFh Shadow enable. F0000h-F7FFFh Shadow enable. F8000h-FFFFFh Shadow enable.
F8shdw F0shdw E8shdw E0shdw ParBlk3 ParBlk2 ParBlk1 ParBlk0
Index Function shdw/parity
Secondary DRAM Timing register. Default Typical setting should same Index
speed slower. This register sets timing mode used DRAMs when HLDA high, i.e., when DRAM accessed local master, master, transfer. Read Timing Mode. 3-2-2-2 page hits (default). only clock mode. 4-3-3-3 page hits 5-4-4-4 page hits (50MHz) timing generated states (1.5 3-2-2-2 mode) after (default) generated states (2.5 3-2-2-2 mode) after (Reserved) Write wait states, single write. wait state writes. wait state writes. Precharge Time. states precharge time. states precharge time. Write burst Timing. -2-2-2 burst write timing (default) -3-3-3 burst write timing. (Reserved) (Refresh pulse width always uses register mode)
write burst prechg write RAS-CAS read burst1 read burst0
Index Function dram
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Configuration Registers
Index
Bits
Description
Cache Controller Mode.
Default Typical setting normal operation with dual-bank secondary cache writeback mode, cache initialization. WRMODE Write Mode. Selects write-hit policy. Never change state this while '1'. Write through Write back (preferred highest performance) INITCACHE Initialize cache. cacheable memory read cycles update cache. castouts performed. Write-hit cycles executed write through. This should never changed from unless changed same time. While this '1', effect. Similarly, should changed from unless changed same time. Cache responds read hits Read hits disabled. FRZCDIR Freeze cache directory (intended diagnostic testing) Normal cache operation directory update. Cache Enable. (default) disable cache. enable cache. Never change this from without initializing cache first. Also, '1', never change from without performing cache flush first. Cache write timing mode 2-1-1-1 burst write (for typical cache configurations) (Reserved) 3-2-2-2 burst write (for single-bank slow SRAM) 4-2-2-2 burst write Cache read timing mode 2-1-1-1 bursts (for typical cache configurations) 2-2-2-2 bursts (for single-bank slow SRAM) 3-2-2-2 bursts (Reserved)
cache read1 cache read0 cache write1 cache write0 cache enable frzcdir initcache wrmode
Index Function cache mode
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Configuration Registers
Index
Bits
Description
Cache Controller Configuration Default Typical setting single-bank 128KB cache with 8-bit tag, after upgrade dual-bank 256KB. (Reserved. Write width bits (default) bits bits (Reserved). (Reserved. Write used future expansion width field). Cache size: bytes (default) 128K bytes 256K bytes 512K bytes 1Mbyte Single Dual bank mode Single bank Dual Bank
cache size2 cache size1 cache size0 width width time
Index Function cache config cache banks
Cache Testing Control. Default Typical setting normal operation. Data SRAM test mode. disabled (default). disables DRAM cycles within test window. test mode. disabled (default) (Reserved). SRAM test window select. Test Window 64K, 128K, 256K cache: 40000h-7FFFFh; 512K cache: 20000:9FFFF. Test Window cache sizes: 100000h-1FFFFFh (Reserved) Code data caching. These bits affect secondary cache line fills only. They affect cache read write hits, which must function normal. cache (via KEN# signal) affected. Code data cache. Code only Data only (Reserved)
Function cache test code/data1 code/data0 test window test SRAM test
Index
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Configuration Registers
Index
Bits
Description
Data port testing, bits 0-7. Default undefined (may vary from power
next). Typical setting normal operation (value effect). When test mode enabled, writes test window cause value this register written bits RAM. Reads from test window cause bits written into this register. Data port testing, bits 8-10. Default undefined (may vary from power next). Typical setting normal operation (value effect). index description. Register bits bits 8-10. Register bits reserved.
Index Function cache cache TAG7 TAG6 TAG5 TAG4 TAG3 TAG2 TAG10 TAG1 TAG9 TAG0 TAG8
25-27
exist. Decode Address Low. Default Typical setting doesn't matter effect) unless
Index non-zero. Address bits compared decode.
Decode Address High. Default Typical setting doesn't matter effect) unless
Index non-zero. Address bits 15:8 compared decode.
Decode Size Mask. Default Typical setting doesn't matter effect) unless
Index non-zero. Decode size bits. Provides mask bits address. byte (port) bytes (ports) bytes (ports) bytes (ports) bytes (ports) bytes (ports) bytes (ports) bytes (ports) Mask 0=decode, 1=ignore address bit. Mask 0=decode, 1=ignore address Mask 0=decode, 1=ignore address bit. Mask A10. 0=decode, 1=ignore address bit. Mask A15:11. 0=decode, 1=ignore address bits.
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Configuration Registers
Index
Bits
Description
Decode Configuration. Default Typical settings: disable Decode
enable strobed chip select read write, enable LDEV# internally local slave that doesn't provide LDEV# signal. (Reserved) Local range. forces function range Activate Chip Select reads. don't activate, activate. note text limitation. Activate Chip Select writes. don't activate, activate. note text limitation. Allow Chip Select Master accesses. disable master, 1=allow master. Chip select strobe. acts chip select decoded from address M/IO# only ANDed with read and/or write strobe.
Decode Address Low. Default Decode Address High. Default Decode Size Mask. Default Decode Configuration. Default disable Decode 00h.
descriptions bits.
Index Index function high mask/size mask15:11 config cs/stb mask10 master mask9 writes mask8 reads mask7 local size2 size1 size0
Memory Decode Address Low. Default Typical setting Decode
disabled. Address bits 23:16
Memory Decode Address High Default Typical setting Decode
disabled. Address bits 31:24
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Configuration Registers
Index
Bits
Description
Memory Decode Size Destination Default disable Decode write this register program Index disable MEMCS0# output signal. Memory Decode used generating MEMCS0#, creating hole local DRAM, forcing internal LDEV# signal local slaves that don't generate LDEV#, creating non-cacheable area, controlling WB/WT mode cache selected local non-local address range. Range Size 0000 byte range 0111 8Mbyte range 0001 128K byte range 1000 16Mbyte range 0010 256K byte range 1001 32Mbyte range 0011 512K byte range 1010 64Mbyte range 0100 1Mbyte range 1011 128Mbyte range 0101 2Mbyte range 11xx (Reserved) 0110 4Mbyte range (Reserved). Hole DRAM Range allowed DRAM DRAM within this range disabled. Local area. disabled. Force LDEV# signal this range. Accesses this range will local bus. Setting this will prevent local DRAM access. memory range must either outside local DRAM decode above must also set. (Reserved). Memory Decode Attributes. Default Typical setting Decode disabled.
Cache Mode. This affects cache mode regardless cycle's destination. CHIPSet does support caching memory other than DRAM (which could memory), however. default cache status this area (based destination, etc). defaults typically: cache DRAM writeback supports it), cache nonDRAM areas. Non-Cache. cache memory either cache. Cache write through cache. cache unaffected this mode, cached according current mode. Cache write back mode cache unaffected this mode, cached according current mode. selected address range entirely within local DRAM, mode won't work local master, Master, read occurs selected range target memory unable back needed (due data being more current than data target memory). (Reserved)
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Configuration Registers
Index
Bits
Description
Memory decode address low. Default Index 30h. Memory decode address high. Default Index 31h. Memory decode size destination. Default Index 32h. Memory decode attributes. Default Index 33h.
dec0 Index dec1 Index function high destination attrib local hole Size3 Size2 Size1 cache1 Size0 cache0
Modes. Default Typical setting clock mode cache.
HITM# Sampling. Write Through. DRAM cache controllers wait HITM#. HITM# disabled this mode used general purpose input bit. Write Back. DRAM cache controllers wait HITM# non-CPU generated memory cycles. HITM# Sample Point clocks after ADS# (end first clocks after ADS# (end second SUSPA# Enable (Reserved) CLKIN Mode (Latched state during power-on reset. writeable.) sampled high during reset, signifying CLKIN mode sampled during reset, signifying CLKIN mode
EADS hitm# sample
Disable SUSPA# Enable SUSPA# (intende Cyrix CPUs)
Index Function modes CLKINmode
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
Soft Reset GATEA20. Default 04h. Typical setting internal keyboard/mouse
controller, external controller. Mouse Interrupt enable control link Disabled (mouse interrupt sent 4045) Enabled (send mouse interrupt notification 4045) function. Test Function (default). Link input (normal operation). This should before enabling 4045 LOUT (Index Also, 4041 should have pull-up resistor keep high during immediately following reset. 4041 Test Mode desired (for hardware testing), 4041 externally pulsed while this register Enable Internal 8042. Disabled. Keyboard pins GATEA20 KBRESET#. Internal 8042 enabled. Keyboard pins KBCLK KBDATA. Enable Mouse port Disabled. Internal 8042 mouse port enabled. must also set. 8042 RESET2 Emulation. Disabled. Emulated 8042 KBRESET# function will cause Soft Reset. 8042 GATEA20 Emulation. Emulated 8042 GATEA20 logic ignores 8042 commands. 8042 commands enabled ulated 8042 GATEA20 logic Bits optional with either internal external keyboard controller, setting these bits normally will provide performance benefit. reset. Always reads Effect write: effect nothing). Reset mode disabled. Otherwise, generate request reset. Disable 8042 emulated commands. 8042 commands 8042. GATEA20 RESET2 commands 8042 have IOW# blocked speed operation 8042 commands.
Function cont 8042 reset kbga20 kbres IntMouse Int8042 Mouse lout
Index
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
3A-3B
(Reserved) Multifunction Selection Register Default
This register determines function pins. future, more functions added. When added input pins, these bits should programmed "General Purpose Inputs", which disables their other functions. LDEV1# usage. always input. Input 14MHz clock mgmt BUSCLK) #LDEV1 (Reserved) LDEV2# usage. This always input. Input Inhibit input LDEV2# External Event mgmt) usage. This always input. Input XDIO# clock External Event usage. This always output. IRQ12 (Mouse Interrupt) ISAEN General Purpose Output
Multifunction Selection Register Default
This register determines function pins, which outputs. RAS6# usage. This always output. RAS6# MEMCS0# (memory chip select MA12 General Purpose Output RAS7# usage. This always output. RAS7# MEMCS1# (memory chip select IOC4045# (4045 chip sel) General Purpose Output usage. This always output. WPROT# (CPU prot) IOCS0# (I/O chip select CACHECS# General Purpose Output usage. This always output. DRAMCS# IOCS1# (I/O chip select ISAEN General Purpose Output
General Purpose Output data register. Default This register supplies data pins which selected general purpose Output bits. Data RAS6# when programmed general purpose output bit. Data RAS7# when programmed general purpose output bit. Data when programmed general purpose outpu bit. Data when programmed general purpose output bit. Data when programmed general purpose output bit. Data FLUSH# when programmed general purpose output bit. Function FLUSH# pin. FLUSH# General Purpose Output bit. IOCS0# (I/O Chip Select General Purpose Output
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
General Purpose Input data register (read only).
This register reads current state listed pins. These pins read regardless selected function pins. This register intended read-only. Writing this register cause GPOUT signals malfunction.
Index
LDEV1# LDEV2# (Reserved) MCLK MDATA (Reserved)
Function select select GPout data GPin data gpBsel1 gpDsel1 flushsel gpBsel0 gpDsel0 GPAsel1 gpCsel1 FLUSH# MDATA gpAsel0 gpCsel0 MCLK ldev1sel1 ras6sel1 ldev1sel0 ras7sel0 ldev0sel1 ras6sel1 RAS7# LDEV2# ldev0sel0 ras6sel0 RAS6# LDEV1#
(Reserved) Enables Control Functions. Typical setting local connectors. Connector enable (Addresses 1F0:1F7, 3F6:3F7) Connector enable (Addresses 170:177, 376:377) Connector enable (Addresses 5F0:5F7, 7F6:7F7) Connector enable (Addresses 570:577, 776:777) Disabled. Accesses bus. IDEEN#, IDECS0:1# active. Enabled. Accesses 4041 logic. Command Start. This specifies earliest that commands active local data port accesses. commands active first commands active Second Data hold. This specifies long IDEEN# held following IDEIOW# going high, long RDY# delayed. state states. Force Defaults. Default value forcing disabled. IDECS0:1#, XA0:1, SBHE# forced default. SBHE# SBHE# always SBHE#. Address setup timer starts SBHE# used IDEA2. Address setup timer starts when addresses forced their defaults.
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
Drive Timing mode. Typical setting local connectors.
Drive Timing Mode (First connector Drive Drive Timing Mode (First connector Drive Drive Timing Mode (Second connector Drive Drive Timing Mode (Second connector Drive Timing Mode Timing Mode (Reserved) cycles used data port (use slow drives).
Drive Timing mode. Typical setting 55h.
Drive Timing Mode (Third connector, Drive Timing Mode Timing Mode Drive Timing Mode (Third connector, Drive Drive Timing Mode (Fourth connector, Drive Drive Timing Mode (Fourth connector, Drive (Reserved)
Function misc drv3:0 drv7:4 forceDefault drv3sped1 UseSBHE drv3sped0 datahold drv2sped1 tstatestart drv2sped0 ideen76 drv1sped1 drv7sped ideen54 drv1sped0 drv6sped ideen32 drv0sped1 drv5sped ideen10 drv0sped0 drv4sped
Index
Timing Read Write pulse Widths
Read Pulse Width Timing Selects clocks (1x) IDEIOR pulse width data port reads. 0000 0100 1000 1100 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Write Pulse Width Timing Selects clocks (1x) IDEIOW pulse width data port writes. Encoding same reads.
Typical Settings:
Mode (46h) (47h) 2Ch*
*IDE Mode (with instead 25h) optimum many existing drives, drive specifications should always checked before using modes listed above.
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
Timing Command Recovery Address Setup
recovery time commands, Timing Selects minimum number clocks which IDEIOR# IDEIOW# must remain high between accesses. Used only local timing state machine. Encoding follows: 0000 0100 1000 1100 0000 0100 1000 1100 0001 0101 1001 1101 0010 0110 1010 1110 0011 0111 1011 1111 Address setup time commands, Timing Selects minimum number between address being setup command going active. timing begins when default values forced onto address pins, from start SBHE# provide provided from CPU). (Reserved)
Index
Timing Read Write pulse Widths
register
Timing Command Recovery Address Setup
register
Function timing timing timing timing wrA3 wrA2 wrA1 asuA0 wrB3 wrB2 wrB1 asuB0 wrA0 asuA0 wrB0 asuB0 rdA3 inacA3 rdB3 inacB3 rdA2 inacA2 rdB2 inacB2 rdA1 inacA1 rdB1 inacB1 rdA0 inacA0 rdB0 inacB0
EventA Selection Interrupts.
Setting these bits will enable specified occurrence generate EventA, which normally restarts TimerA. EventA other function. TimerA, turn, automatically slow clock trigger SMI, both. specified occurrence will ignored. events selected indicate system activity, that system should slowed down. IRQs detected corresponding INTA cycle. INTR detected high level. IRQ0 (Timer Tick) IRQ1 (Keyboard) IRQ3,4,5, (serial parallel ports) IRQ6 (floppy hard disk) IRQ9 (video coprocessor) IRQ8,10,11,12, (Misc Interrupts) INTR. Time INTR goes high (indicating unmasked interrupt) NMI. high transition pin.
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
index
Description
EventA Selection Memory Accesses.
Disk accesses. Which ones determined Index 86h. Serial Parallel Ports. Which addresses determined Index 86h. Keyboard controller (60h 64h) Video Memory (A0000h BFFFFh) Ext0 multifunction pin). Polarity, etc, selected elsewhere. Master (HLDA high). Master, Master, cycle Programmable address (see Indexes 28:2B) Programmable address (see Indexes 2C:2F)
function EventA EventA prog INTR prog
IRQ8,10:12,15
master
IRQ9,13 Ext0
IRQ6,14 video
irq3,4,5,7
IRQ1 com/lpt
IRQ0 disk
WakeA Event Selection Interrupts
Setting these bits will enable specified occurrence generate WakeA, which generate and/or switch clock back full speed. specified occurrence will ignored. events selected indicate occurrence which should bring system back operating speed either operator external event. events detected identically EventA positions identical. Only INTR, (i.e., IOCHCK#), Ext0 detectable WakeA events while clock stopped. IRQ0 IRQ9,13 IRQ1 IRQ8,10,12,15 IRQ3,4,5,7 INTR IRQ6,14
index
WakeA event selection memory accesses
Identical selections register Disk Serial/Parallel Ports Keyboard Video Memory
function WakeupA WakeupA prog INTR prog
IRQ8,10:12,15
Ext0 Master Programmable Programmable
IRQ9,13 Ext0 IRQ6,14 video irq3,4,5,7 IRQ1 com/lpt IRQ0 disk
master
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
EventB selection.
Setting these bits will enable specified occurrence generate EventB, which normally restarts TimerB. EventB other function. TimerB, turn, automatically stop clock trigger SMI, both. specified occurrence will ignored. events selected usually indicate short term system activity, that system should slowed down. events available those which will often selected reset TimerA, should reset TimerB. IRQ0 Ext1 multifunction pin). INTR Video Memory. Keyboard (Reserved) Programmable range EventA (the output EventA logic)
function EventB EventA prog keyboard video INTR IRQ0
index
WakeB selection.
Setting these bits will enable specified occurrence generate WakeB, which normally restarts stopped clock generate SMI. specified occurrence will ignored. events selected usually indicate request usage. events available those which occur when clock stopped. (Reserved) INTR going from high (e.g., IOCHCK#) SMI# low. (Reserved) Alternate master active (HLDA active) External selected register WakeA (the output WakeA logic)
function WakeupB wakeA event master INTR
index
Port Selection Events.
Bits 0,1, this register selects which serial, parallel ports indicate event when COM/LPT EventA WakeA registers. Bits select which ports cause event when DISK EventA WakeA registers. COM1 COM2 addresses included COM/LPT events (3F8:3FF 2F8:2FF) COM3 COM4 addresses included COM/LPT events (3E8:3EF 2E8:2EF) LPT1, LPT2, LPT3 addresses included COM/LPT events (3BC:3BE, 378:37F, 278:27F). (Reserved) Floppy ports included DISK events (3F0:3F1 3F3:3F5). included. IDE1 ports included DISK events (1F0:1F7, 3F6:3F7) IDE2 ports included DISK events (170:177, 376:377) (Reserved)
IDE2 IDE1 floppy lpt1,2,3 com3&4 com1&2
index function select which
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
Interrupt Acknowledge base. Typical setting with DOS, subject change
automatically whenever INTC2 interrupt vector base changed software. This register used 4041 determine whether INTA cycle caused IRQ8:15 not, since 4041 does receive pins directly does have access interrupt vector returned during INTA cycle. (See also Indexes 82h.) INTA vector matches contents this register (bits 7:3), came from IRQ8:15. not, interrupt came from IRQ0:7. vector itself (bits 2:0) then indicates which specific within group being acknowledged. Writing interrupt vector base automatically causes value this index register match value, writing this index does alter value written since actual INTC2 resides 4045. Software BIOS normally should never write this register (Index 87h), since value automatically tracks whatever written INTC2. (Reserved) Specifies upper bits interrupt acknowledge vector which corresponds IRQ8:15. Typically (via ports A1h) 01110 DOS, 01011 Windows.
intabase7 intabase6 intabase5 intabase4 intabase3
index function INTA base
TimerA Control Register
This register provides rate function TimerA function WakeA Event. TimerA also cause SMI. This enabled enable register. TimerA count rate. Off. Counter remains restart value. 64uS 16mS 256mS seconds seconds (Reserved) (Reserved) Slow Down clock TimerA timeout. Disabled TimerA timing will cause clock slowed down. This done either internal divider external synthesizer, specified elsewhere. (Reserved) Switch full speed clock WakeA Events. Disabled. WakeA event switches clock back full speed.
TimerA Count Register
Writing this register sets count value. value between written. This value reloaded timer each time EventA occurs. Reading this register gives current value timer. With rate OFF, current value timer will restart value last programmed here. TimerA restart value.
tmrA6 tmrA5 TimerASlow tmrA4 tmrA3 rateA2 tmrA2 rateA1 tmrA1 rateA0 tmrA0
index function timerA cntrl WakeAFast timerA tmrA7
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
TimerB Control Register
This register provides rate function TimerB function WakeB Event. TimerB also cause SMI. This enabled enable register. TimerB count rate. Off. 256mS 64uS seconds seconds 16mS (Reserved) (Reserved) Stop clock TimerB timeout. Disabled TimerB timing will cause clock stopped. selected Stop-Clock protocol will followed, specified elsewhere. (Reserved)
TimerB Count Register
Writing this register sets count value. value between written. This value reloaded timer each time EventB occurs. Reading this register gives current value timer. With rate OFF, current value timer will restart value last programmed here. TimerB restart value.
tmrB7 tmrB6 tmrB5 Stop tmrB4 tmrB3 rateB2 tmrB2 rateB1 tmrB1 rateB0 tmrB0
index function timerB cntl timerB
Time Base Selection Slow Clock frequency
This register selects clock source divider necessary make approximately 1MHz time base timer delay functions. Divider Selection. Divide Divide Divide (Reserved) Divide (Reserved) Divide Clock source selection. CLKIN (divided clock mode). Multifunction (used 14.31818MHz clock in). Slow clock divider. Specifies divider used system clock when slow mode selected. switching actually done setting. Full speed Divide Divide (Reserved) Divide (Reserved) Divide (Reserved) STPCLK# usage STPCLK# STPCLK# STPCLK# switched CLKSPEED pin. 1=Full Speed, 0=reduced speed. used control external clock generator.
stpclk pin# slowclk2 slowclk1 sloclk0 cksel div2 div1 div0
index function Time Base
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
Clock switching modes.
These bits select clock switching stopping modes. Stop Halt. 1=Stop clock HALT cycle. Stop Halt while Slow. 1=Stop clock HALT cycle only when clock SLOW mode. Stop Clock Mode. Pull STPCLK# only. Pull STPCLK# then actually stop clock. Pull STPCLK# when switching clock. pull STPCLK# when switching clock frequency. Activate STPCLK# before clock change. delay. Delay between changing clock frequency removing STPCLK# delay 256uS delay 32uS delay 512uS delay 64uS delay delay 128uS delay delay Wait Stop Clock Acknowledge cycle. wait Stop Clock Acknowledge cycle. Wait Stop Clock Acknowledge before changing clock.
waitstopack plldelay2 plldelay1 plldelay0 stpclk4slow stopmode StopHaltnslo StopOnHalt
index function Stop Clock
Software Commands Status.
Writing this register causes specific actions taken. action occurs. action taken that function. There actual register which holds values written here. Reading this register provides status information internal hardware functions. Writing: GoSlow command. Writing causes clock slowed down whatever means selected. Bits should both written GoFast command. Writing causes clock return full speed. Stpclk. This will cause clock stopped using selected stop clock method. Generate SMI. Writing will generate software SMI. (Reserved, write Reading: Clock Speed. 0=slow clock, 1=full speed. (Reserved)
index function Commands GenSMI Stpclk GoFast GoSlow
External Event function.
EXT0 function: Active level triggered Active high level triggered Active edge triggered (negative edge) Active high edge triggered (positive edge) EXT1 function (same definitions EXT0) (Reserved)
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
Status Register
This register indicates what events currently causing SMI. will currently pulling low. Writing location resets that (except TimerA Timeout TimerB Timeout WakeA Event WakeB Event Restart Halt cycle (Reserved). status Register
Status Register
Additional sources. will currently pulling low. Writing location resets that bit. bits this register appear Status Register Software restart request. External External (Reserved)
Enable Register
This register enables sources. disables, enables. TimerA Timeout TimerB Timeout WakeA Event WakeB Event Restart Halt cycle (Reserved). Global enable bit. Disables sources routines should this then back again before leaving SMM, guarantee edge SMI# sources still active. Otherwise, fail return response active source. (This necessary other sources active, indicated reading Index 90h.)
Enable Register
Additional enables. Software restart request. External (EXT0 pin) External (EXT1 pin) (Reserved) SMI# Mode Intel Mode Cyrix Mode
function statusA next register statusB enableA global enable EnableB mode Halt Halt Restart Restart WakeupB External1 WakeupB External1 WakeupA External0 WakeupA External0 TimerB TimerA restart Software TimerB TimerA restart Software
index
Revision
2/10/95
Preliminary
CS4041
Subject change without notice Index Bits Description
Configuration Registers
modes.
This register controls modes CPU. SMIACT3 SMIADS# mode SMIACT# function (Intel method) SMIADS# function (Cyrix method) Force FLUSH SMM. flush cache upon entry into Flush cache pulsing FLUSH# when SMIACT# goes low. This should only done with Intel CPU. need done when windows below used. Force A20M# SMM. effect A20M# Drive A20M# high with SMIACT# Disable KEN# SMM. effect KEN# Drive KEN# high accesses. Soft redirection. redirect soft resets. Disable soft resets redirect SMI. (Reserved, write `000')
SoftResRedir DisKen ForceA20m flushOnSmm smiact
index function modes
Restart selection.
This register selects which ports cause restart. position causes that range generate restart cycle. restart means that 4041 asserts during cycle, which recognizes restart SMI. then enters with status information allowing routine determine what resource being addressed. routine performs peripheral power-up re-initialization needed, then exits SMM, allowing re-execute same operation that caused SMI. This register should always `00h' Index `0'. Otherwise, cycle timing malfunction during enabled range. COM1 (3F8:3FF) COM2 (2F8:2FF) LPT2 (378:37F) Floppy hard disk (1F0:1F7, 3F0:3F1, 3F3:3F5, 170:177, 370:377) (3B0:3BB, 3C0:3DF) Keyboard Programmable range Programmable rang
function restart prog prog floppy/HD LPT(378) com2 com1
index
Port shadow register.
This register provides means reading back last value written port 70h, including enable bit, which would otherwise unreadable. This register read only. write this register. Port shadow read.
port70d7 port70d6 port70d5 port70d4 port70d3 port70d2 port70d1 port70d0
index function Shadow70
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Port Addresses
3.4. 84045 Port Addresses
Note: "Default" register values refer power-on hardware defaults established automatically following hardware reset, before alternate values have been written BIOS. "Typical" values refer typical settings normal system operation. Addr Bits Description
00-0F 20-21
controller DMA).
These ports contained megacell. controller will respond accesses 10-1F original 00-0F repeats 10-1F).
Interrupt Controller (IRQ0-7).
These ports contained megacell. Interrupt controller does respond ports 22-3F.
Configuration register Address Port.
Write only port which holds address Chips Technologies Index register accessed through port This register must written before each access port even same index register being accessed twice row.
Configuration register data.
Accessing this port accesses Configur ation register pointed port second access port without writing port between will ignored. Unless otherwise noted register descriptions, reserved undefined index registers should written reserved bits within defined index register should written zero written with same value previously read).
Configuration Register Address Port
Write only. address written here stored separately from port This register used config register index when port read written.
Configuration Register Data Port
Accessing this port accesses Configuration register pointed port second access port without writing port between will ignored. "accessed" separate port 26/27 22/23 windows.
40-43
Timer Chip (8254).
These ports contained megacell. timer does respond ports 44-4F.
Keyboard Mouse Interrupt Clear.
Reading from port resets keyboard mouse interrupt latches, IRQ1 IRQ12. other data read/write functions this port implemented 4041.
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Port Addresses
Addr
Bits
Description
"Port
This compatible port with miscellaneous information. Bits read/write. Bits read only. Only bits contained 4045 (bits there readback purposes only). remainder 4041. reads 4045 drives bits their proper values, bits Default 20h. Timer gate. This enables disables 1.19 clock input Timer output from Timer conjunction with below, provides signal speaker. this Timer enabled, programmed will produce square wave programmed frequency. When this below forced speaker output signal will high depending below. Speaker Data. This ANDed with output timer erted produce signal actually sent speaker. When gate (bit above) low, this gives direct software control speaker. speaker signal will high when this respectively. When speaker idle, bits normally will both speaker output signal will high. Enable Parity Check. enables local DRAM parity checking. disables local DRAM parity checking clears local parity error flip-flop. This inverted sent active preset flip-flop. output PCK# logic. parity error clocks flip-flop There also index register block local DRAM parity errors. prevents flip-flop from being clocked. flip-flop where Preset precedence Clear precedence Enable IOCHCK. enables IOCHCK interrupt. disables IOCHCK clears IOCHCK flip-flop. This inverted sent active clear flip-flop. IOCHCK# sent active Preset input. output logic. output sent this register. flip-flop ALS74 where Preset precedence Clear precedence Refresh Detect. This read only toggles each refresh. should toggle whenever timer produces pulse (about every 15us). This should done even refresh disabled. Some software uses this time delay. Timer output. Read only. This allows software monitor output timer which ANDed with this register inverted produce speaker signal. speaker signal when bits both either speaker output high. setting bits '01', software Timer without generating speaker output. (Channel Check latch). This 4045. contained 4041. indicates that IOCHCK# been activated. This output flip-flop mentioned this register. 4045 will drive this reads. (Parity Check latch). This 4045. contained 4041. indicates that local parity error occurred. output flip-flop mentioned this register. 4045 will drive this reads.
Port (Parity err) (CHCK) Detect chck enable parity enab spkr data tmr2 gate
Real Time Clock Address Port mask.
Real Time clock address. value written these bits becomes address RTC/CMOS which will read written through port (NMI Mask.) This 4045. used 4041. This inverted ANDed with sources (the several sources). result function CPU. This allows "Non-Maskable Interrupt" maskable externally.
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Port Addresses
Addr
Bits
Description
80-8F
Real Time Clock Data Port.
Reading writing this port will read write register pointed last write port
Page Registers
These ports contained megacell. They provide A16-23 8-bit accesses A17-23 16-bit DMA. Read/Write, used during normal system operation. This port written BIOS routines indicate BIOS status. pair segment LEDs often test boards display this information. Channel page register Channel page register Channel page register used. Channel page register used. Channel page register Channel page register Channel page register used. Refresh page register. Bits from this register define state SA17-19 during refresh. Since refresh hidden, 4045 access SA16 LA20-23 during refresh. bits used. bits read/write. Typical setting 00h.
84-86 8C-8E
Fast reset GATEA20.
Fast reset. transition activates reset. Fast GATEA20. ORed with other GATEA20 signals (from 8042, instance). Drive A20M- other A20M- sources low). Force A20M- high CPU, causing leave unmasked. (Reserved). Password Protect. Index writing this effect always reads Index writing this following effects: further reads writes CMOS locations 38:3F disabled, this remains (reads back cannot cleared except system reset (PWRGOOD cycling, causing SYSRESET cycle). (Reserved). read
Port passpro Fast gatea20 fast reset
A0-A1
Interrupt Controller (IRQ8-15).
These ports contained megacell. interrupt controller does respond ports A2-BF.
C0-DF
Controller DMA).
These ports cont ained megacell. Only even numbered ports used. Reads writes numbered ports will access same register corresponding even numbered port.
F0-F1
Error Reset.
Writing either causes error latch (which also generates IRQ13) cleared. data ignored.
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
3.5. 84045 Configuration Registers
Index Bits Description
WAIT STATE CONTROL. Default C0h. Typical setting 00h.
Index programming 4045 internal BUSCLK frequency. wait states. Controls number wait states (4045 internal BUSCLK cycles) added access port (00-0Fh, 20-21h, 22-23h, 40-43h, 71h, 80-8Fh, A0-A1h, C0-DFh). Port decoded outside megacell does have added wait states. 4045 pulls IOCHRDY needed insert wait states. wait state wait states Three wait states Four wait states 16-bit wait states. These bits control wait states (DMACLK cycles) inserted during 16-bit transfers. wait state (default) wait states Three wait states Four wait states 8-bit wait states. These bits control number wait states (DMACLK cycles) inserted during 8-bit transfers. wait state (default) wait states Three wait states Four wait states wait states defined DMACLK cycles (see Index 0Ah) added IOW# MEMW# command time. Minimum command time (one wait state) DMACLK cycles total. 4041 pull IOCHRDY needed additional wait states local timing. MEMR# signal extension. PC/AT, assertion MEMR# delayed DMACLK cycle compared IOR#. This desirable some systems. Delay MEMR# DMACLK (default, PC/AT compatible) MEMR# delayed; follows same timing IOR# DMACLK clock select. PC/AT)
DMACLK cycle 4045 BUSCLK cycles (default, DMACLK cycle 4045 BUSCLK cycle
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Addr
Bits
Description
Performance control Default Typical setting performance reduction, more DX-33 DX2-66 reduction equivalent performance. hold pulse width. These bits amount time which hold following each refresh. Once count set, mode must enabled separate register "Turbo" button (SLOW# pin). values below number 4045 internal BUSCLKs (see Index 0Ah) which kept hold. Normally this occurs about every 15uS. 000000 hold request (default) 000001 Minimum speed reduction (one 4045 BUSCLK) 111111 Maximum speed reduction (127 4045 BUSCLKs). programmed value should exceed time between refresh cycles. refresh rate 8.33 4045 BUSCLK, maximum usable value about (14.4 us). Values approaching (78h) needed reduce performance 486DX-33 DX2-66 systems equivalent. cache flush. flush cache during slow mode HOLD. flush cache during each slow mode hold request. Setting this prevents from executing from internal cache during slow mode hold, which generally will necessary successfully reduce performance DX-33 DX2-66 system equivalent.
function Pefrm cntl flush hold width6 hold width5 hold width4 hold width3 hold width2 hold width1 hold width0
index
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
4045 Misc Control Default Typical setting external keyboard controller,
internal controller. Deturbo (Performance Control Enable). This enables performance control programmed Register 08h, nothing with slow clock mode. This ORed with invert Turbo Switch (SLOW# input pin). Normal mode (default) Performance Control Enabled. Preemptive protocol LGNT#. Non-preemptive protocol. arbitration will take LGNT# inactive until LREQ# gone inactive (default). Preemptive protocol. arbitration logic will take LGNT# when controller requests bus. will wait LREQ# inactive before granting controller. This VL-Bus compatible. Refresh Request Enable. This blocks Timer Refresh request when disabled. This prevents reset problems, which occur when refresh request generated during reset sequence. 8254 timing disabled reset. Block Timer refresh requests. Enable Timer refresh requests. (Essential DRAM refresh.) refresh enable. Disable refreshes. Refresh request still sent 4041 4031, Master Refresh cycles still performed. Disabling refresh allow chip deleted systems that don't need refresh. Enable refresh. Needed full compatibility A20M# TEST# 4045 LOUT enable function. A20M# TEST# input, forcing 4045 into test mode when low. 4045 LOUT also floated allow 4041 used test mode control 4041. (Default). A20M# TEST# output, driving A20M#. test mode disabled. 4045 LOUT driven. 4041 should enabled (Index before setting this GATEA20 emulation disable. A20M# only Port GATEA20 signal (which after reset). (default). A20M# Port GATEA20 emulated 8042 GATEA20 information received across control link. Keyboard interrupt mode. IRQ1 received directly (from external 8042). IRQ1 received over control link from 4041 (internal KBC). Floating point error mode. Internal (486) mode. FERR# IGNNE# pins provided. IRQ13 generated internally (default). External mode. IRQ13 NTCLR pins provided. remainder logic provided externally. This mode used where IRQ13 required (such system with Weitek Coprocessor).
function misc fpintmode kbintmode 8042em ga20/test proto Deturbo
index
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
Clock selection. Default Typical setting 33.3 SCLK, SCLK. Clock select controllers. Also determines 4045 internal BUSCLK erformance control (Index 08h) wait states (Index 01h). optionally further divide this clock before sending controllers should programmed Index source clock SCLK, which clock, 14.3 MHz. resulting clock should about 8MHz, which megacell will then divide programmed Index used controllers. Higher clock rates used risk incompatibilities with devices. External BUSCLK comes from 4041 (Index 07h). 4045 internal BUSCLK doesn't need phase with 4041 external BUSCLK, although BUSCLKs normally will programmed same frequency. 0000 SCLK/10 SCLK) 0001 SCLK/8 (66.67 MHz) 0010 SCLK/6 SCLK) 0011 (Reserved) 0100 (Reserved) 0101 (Reserved) 0110 14.31818 divided (9.545 MHz) 0111 14.31818 divided (7.159 MHz)
1000 1001 1010 1011 1100 1101 1110 CLKIN/5 CLKIN/4 CLKIN/3 CLKIN/2.5 CLKIN/2 CLKIN/1.5 (Reserved) 1111 (40MHz SCLK) (33MHz SCLK) (25MHz SCLK) (20MHz SCLK) (16MHz SCLK)
clock 14.31818MHz divided (4.091 MHz)
(Reserved) External
function
Internal enable External RTC. 32KX1 becomes IRQ8# input.
clk3 clk2 clk1 clk0
index
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
Arbitration WBACK# control. Default xx00 0000 (the 'x's invert state DGNT# power Typical setting minimum system with CPU. Arbitration lock. Used prevent from going into HLDA while switching clock (required Intel S-Series CPUs). Normal operation HOLD will high. HOLD already high, arbitration logic will operate normally until HOLD goes back low. Write Back mode 4035 WBACK# mode (HOLD goes when WBACK# low) 4045 WBACK# mode (HOLD A8:9, A17:23 floated when WBACK# goes low). LREQ1# input enable. must this function work properly. LREQ1# input disabled. LREQ1# input enabled. LREQ1# LGNT1# Select SLOW# FLUSH# functions provided pins LREQ1# LGNT1# functions provided pins LREQ2# input enable. must 1for this function work properly. LREQ2# input disabled. LREQ2# input enabled. IOCS# input enable. must this function work properly. IOCS# input disabled. Internal decoded from A0:9 only. IOCS# input enabled. Internal conditioned with IOCS# low. SA17:19 function enable/disable. Default invert DGNT# power changed software. enable proper mode power-up (probably essential successful BIOS startup from ROM), DGNT# needs pull-up pull-down resistor. SA17:19 driven pins (DGNT# pulled up.) LREQ2# LGNT2# IOCS# (DGNT# pulled down.) SA17:19 indicator pin. This input INVERTED status DGNT# signal power cannot changed software. will also this value power actually determines functions SA17-19 pins. DGNT# high. System configured SA17:19 mode. DGNT# low. System configured LREQ2# LGNT2# IOCS# mode.
default function iocs enab lreq3# enab slo/flush func lreq1# enab mode lock
index function control
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
Configuration Registers
Index
Bits
Description
Port feature control. Typical setting external 8042, 4041
internal KBC. Port reset disable. Port causes restart. Port restart disabled. 4041 will handle port restarts causing SMI. Port Password protect enable. Disable Port password protect feature. Setting this will reenable accesses CMOS password area already been protected. Enable Port password protect feature. (Reserved) Reset Mode. Newer CPUs need HOLD before being reset. Reset only when HOLD. Reset only when HOLD. restart alternate code disable. Link code generates restart Link code does generate restart. Must this code used mouse interrupt. When used with 4041 always (for 4031 should IRQ12 output enable. Disabled. mouse interrupt flip flop drives IRQ12. open collector. (Reserved) Core Reset Disable. Prevents loss register contents during suspend (system powered down except 4045; also known "suspend disk"). Software should this before initiating suspend sequence, that registers will preserved during resume. When resuming, software should write this bit. This cleared PSRSTB# instead PWRGOOD. Reset core when PWRGOOD low. reset core when PWRGOOD low. guarantee core reset manufacturing test other reasons, PWRGOOD PSRSTB# must both same time. This condition will exist automatically main power (PWRGOOD low) system battery being changed connected first time (PSRSTB# momentarily low). PSRSTB# internally blocked (ignored) when PWRGOOD high.
function RTC, pt92 IRQ12 link code password pt92
index
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
System Level Functions
System Level Functions Cross References
This section describes each CHIPSet function from system standpoint. Each subsection lists basic features, board level implementation options, which chip(s) function contained detailed operation described individual chip specs, which follow this section. Extensive cross-references other sections have been provided locating applicable information given topic.
4.1. Clocks
Either clock provided 4041 CLKIN from oscillator. clock needed only highest speed DRAM mode (3-2-2-2 burst read), which used lower clock frequencies. oscillator goes through clock dividing switching logic, which allows power management system slow down system clock. This goes three clock outputs, produced skew with respect each other: CLK2OUT clock, back into 4041. Does stop. This clock clock provided CLKIN. SCLKOUT clock everything except CPU. Does stop. CPUCLK clock CPU. stopped stop-clock mode These clocks normally buffered with 74F244, distributed system, including being back into 4041 rest internal logic. Clock switching optionally done with clock generator chip. Some clock generator chips switch frequencies slowly enough remain locked. This allows power management with standard CPU. further information, Sections 6.2.
4.2. Reset GATEA20
reset GATEA20 logic contained 4045. 4045 receives reset (PWRGOOD) from power supply power clear logic. also receives restart commands from following sources: 8042 emulation 8042) across control link from 4041; port which internal 4045; config register reset. 4045 generates SYSRESET CPURESET. SYSRESET goes active only response PWRGOOD (due power pushing RESET button). CPURESET goes active soft restarts also. restarts redirected generate rather than reset avoid SRESET collision problems. Table 4.1: Chip Reset Signal Routing Type Standard with SRESET input SYSRESET signal RESET CPURESETsignal RESET SRESET
gated only. 4045 provides A20M#, which port GATEA20 GATEA20 from 4041, which sent across link. This consists 8042 GATEA20 (internal, emulated, external) GATEA20. further information, Sections 5.3, 6.3, 6.4. Control Link described Section 4.3.1.
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
System Level Functions
4.3. Arbitration
4045 contains most arbitration logic. arbitrates between CPU, local masters, DMA, masters. Refresh always hidden, occurs when either local master control bus. Local masters supported accordance VL-Bus standard. 4045 will preempt local master when unmasked request occurs. 4035 SIPC provided LREQ# LGNT# pairs, allowing more created external PAL. This default mode 4045, also configured provide LREQ# LGNT# pairs. SIPC arbitration logic locked prevent from going into HOLD when switching clock frequencies. S-series CPUs respond properly snoop cycles HOLD requests when internal frequency stabilized following change input clock frequency. further information, Sections 6.5.
4.3.1 Control Link
noted descriptions (Section simple control link used communication between 4041 4045. 4041 LOUT connected 4045 LIN, 4045 LOUT connected 4041 LIN. following events communicated from 4045 4041: Refresh Request (normal Master) Refresh Complete Address Strobe following events communicated from 4041 4045 using bit-serial event codes: Refresh request acknowledge Interrupt Acknowledge cycle Reset Request Keyboard controller Gate Keyboard mouse interrupts using internal keyboard/mouse controller)
4.4. Refresh
AT-compatible Timer 4045 generates refresh requests internally 4045. 4045 arbitrates refresh requests with reset requests, Master requests (DREQ# inputs), local master requests (LREQ# inputs). When 4045 ready refresh operation proceed, signals this 4041 control link (LIN LOUT signals). 4041 then arbitrates refresh request with activity (DRAM and/or accesses). When 4041 ready refresh proceed, acknowledges refresh request control link back 4045. 4041 performs DRAM refresh cycle 4045 performs refresh cycle. When 4045 completed refresh, 4045 signals this 4041 control link. DRAM refresh occur before, during, after refresh. During refresh, 4045 drives REFRESH#, MEMR# SA0:7. DRAM refresh always CAS-before-RAS external refresh address needed). addition, refresh always hidden, i.e., allowed continue running during refresh (HLDA inactive). long doesn't access local DRAM Bus, there conflict. particular, continue perform primary and/or secondary cache cycles local slave accesses while refresh operation progress. tries access local DRAM during refresh operation, READY# BRDY# withheld cycle delayed needed allow refresh complete. access local DRAM soon DRAM refresh cycle finished, even refresh still progress will usually case). further information, Sections 5.10.4 6.7.
Revision
2/10/95
Preliminary
CS4041
Subject change without notice
System Level Functions
4.5. Co-processor Logic
co-processor logic 4045 chip. pins FERR# IGNNE#. IRQ13 generated internally. write ports clears interrupt. FERR# IGNNE# pins converted IRQ13 INTCLR# respectively allow external coprocessor error logic used. further information, Section 6.12.
4.6. Features
local master accesses handled 4041 Chip. 4045 slave that time. 4045 contains controllers, becomes master cycles, provides arbitration masters. 4041 slave that time, converts cycles local cycles local DRAM, cache, local slaves. further information, Sections 5.5.1, 5.11, 6.8, 6.10. Other compatible features: Performance control using HOLD Section 6.6. Standard functions 4045 enhancements Section 6.9. 16-bit decoding Section 6.11. Port Speaker output Sections 3.2, 3.4, 6.14.
4.7. Local Support
CS4041 CHIPSet fully supports VL-Bus 2.0. Both local slaves masters supported with very little external logic. Below brief description VL-Bus support. Refer individual chip specs more details: 4041 Chip: Samples LDEV# start each cycle (either first second allows local slave capture cycle active. Translates master cycles local cycles when LDEV# active. Allows local masters access most system resources they CPU. Performs snooping write back cache when enabled. 4045 Chip: Provides sets LREQ# LGNT# signals local masters. Takes HOLD write back modified cache line. further information, Sections 4.3, 5.5, 5.11, 5.13.
4.8. DRAM controller
DRAM controller supports banks. This configured blocks which each contain banks. This allows double bank SIMMs installed. "bank" defined dword-wide physical memory controlled single signal. 4041 provides total lines, each bank. single four lines provides individual byte write control each bank. Each block programmable DRAM size, number banks installed starting address. This allows maximum flexibility DRAM installation, does require that banks installed particular physical order. Revision 2/10/95 Preliminary CS4041
Subject change without notice
System Level Functions
timing modes provided allow timing optimization based DRAM speed speed. separate, less aggressive timing mode selected masters since they less controlled system designer) variable timing equation, fast particular used system designer. timing modes are: Burst Reads: 3-2-2-2, 4-3-3-3, 5-4-4-4 timing modes Single writes: wait state. Burst Writes: 3-2-2-2, 4-3-3-3. timing: states (1.5 3-2-2-2 burst reads). pulse width refresh cycles: states. precharge: clocks 256K, deep DRAMs supported. Direct drive provided banks. Beyond that, buffering dependent capacitive load provided DRAM configuration. 12/10 addressing supported 4Mx4 DRAM. 13/11 addressing supported deep DRAMs using multifunction MA12. DRAMs placed local data directly buffered with F245s. buffer control signal provided multifunction pin. Throughout this document, term "local DRAM" means DRAM controlled directly RAS-CAS signals 4041, memory slaves residing utilizing LDEV# signal claim memory cycles. further information, Section 5.10.
4.9. Cache Controller
cache controller following features: Direct Mapped. Standard SRAMs External Internal comparator Operation 50MHz byte line size 64K, 128K, 256K, 512K, cache size Write back write through Single bank dual bank (word interleaved) cache. 2-1-1-1, 2-2-2-2, 3-2-2-2 reads. (2-2-2-2 mode single bank only) writes 2-1-1-1 3-2-2-2 burst writes. cache controller allows cost performance tradeoffs. Full speed modes supported performance, slower modes supported cost effective systems, especially with single bank caches higher speeds. Single bank 2-1-1-1 supported. system board easily upgradeable from single bank dual bank cache without jumpers data SRAMs. Some upgrade configurations require jumper RAMs since connect
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