VOLT ADVANCED+ BOOT BLOCK FLASH MEMORY 28F800C2, 28F160C2 (x16)

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VOLT ADVANCED+ BOOT BLOCK FLASH MEMORY
28F800C2, 28F160C2 (x16)
Flexible SmartVoltage Technology V-3.0 Read/Program/Erase Fast Production Programming High Performance V-3.0 Access Time V-3.0 Access Time Optimized Architecture Code Plus Data Storage Eight Kword Blocks, Bottom Locations Sixty-Three 32-Kword Blocks Fast Program Suspend Capability Fast Erase Suspend Capability Flexible Block Locking Lock/Unlock Block Full Protection Power-Up Hardware Block Protection Option Lockout Voltage Power Consumption Typical Read Power Typical Standby Power with Automatic Power Savings Feature Extended Temperature Operation
Improved Production Programming Faster Production Programming Additional System Logic 128-bit Protection Register 64-bit Unique Device Identifier 64-bit User Programmable Cells Extended Cycling Capability Minimum 100,000 Block Erase Cycles Supports Flash Data Integrator Software Flash Memory Manager System Interrupt Manager Supports Parameter Storage, Streaming Data (e.g., voice) Automated Word/Byte Program Block Erase Command User Interface Status Registers Cross-Compatible Command Support Intel Basic Command Common Flash Interface Various Applications 48-Ball µBGA* Package 48-Lead TSOP Package 0.25 ETOXVI Flash Technology
0.25 Volt Advanced+ Boot Block flash memory, manufactured Intel's latest 0.25 technology, represents feature-rich solution power applications. These flash memory devices incorporate voltage capability (2.4 read, program erase) with high-speed, low-power operation. Flexible block locking allows block independently locked unlocked. 128-bit protection register enhances customers' ability develop secure systems. this Intel-developed Flash Data Integrator (FDI) software have cost-effective, flexible, monolithic code plus data storage solution. Volt Advanced+ Boot Block products will available 48-lead TSOP 48-ball µBGA* packages. devices have 16-bit data bus. Additional information this product family obtained accessing Intel's Flash website:
June 1999
Order Number: 290647-002
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. 28F800C2 28F160C2 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O. 5937 Denver, 80217-9808 call 1-800-548-4725 visit Intel's website http:\\www.intel.com
COPYRIGHT INTEL CORPORATION 1998, 1999 *Other brands names property their respective owners. CG-041493
CONTENTS
PAGE INTRODUCTION.5 Volt Advanced+ Boot Block Flash Memory Enhancements.5 Product Overview PRODUCT DESCRIPTION Package Pinouts Block Organization 2.2.1 Parameter Blocks 2.2.2 Main Blocks PRINCIPLES OPERATION Operation 3.1.1 Read.10 3.1.2 Output Disable.10 3.1.3 Standby 3.1.4 Reset.11 3.1.5 Write.11 Modes Operation.11 3.2.1 Read Array 3.2.2 Read Configuration.12 3.2.3 Read Status Register.12 3.2.3.1 Clearing Status Register 3.2.4 Read Query 3.2.5 Program Mode.13 3.2.5.1 Suspending Resuming Program 3.2.6 Erase Mode 3.2.6.1 Suspending Resuming Erase.14 Flexible Block Locking.18 3.3.1 Locking Operation 3.3.2 Locked State 3.3.3 Unlocked State 3.3.4 Lock-Down State 3.3.5 Reading Block's Lock Status 3.3.6 Locking Operations during Erase Suspend 3.3.7 Status Register Error Checking
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PAGE 128-Bit Protection Register. 3.4.1 Reading Protection Register 3.4.2 Programming Protection Register 3.4.3 Locking Protection Register Program Erase Voltages. 3.5.1 Improved Operation Production Programming 3.5.2 VPPLK Complete Protection Power Consumption 3.6.1 Active Power (Program/Erase/Read) 3.6.2 Automatic Power Savings (APS). 3.6.3 Standby Power 3.6.4 Deep Power-Down Mode Power-Up/Down Operation. 3.7.1 Connected System Reset 3.7.2 VCC, Transitions Power Supply Decoupling. ELECTRICAL SPECIFICATIONS. Absolute Maximum Ratings Operating Conditions. Capacitance Characteristics. Characteristics-Read Operations- Extended Temperature Characteristics-Write Operations- Extended Temperature Erase Program Timings Reset Operations. ORDERING INFORMATION. ADDITIONAL INFORMATION APPENDIX Current/Next States APPENDIX Program/Erase Flowcharts APPENDIX Common Flash Interface Query Structure
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APPENDIX Architecture Block Diagram APPENDIX Word-Wide Memory Diagrams
APPENDIX Device Table APPENDIX Protection Register Addressing
REVISION HISTORY
Date Revision 11/17/98 06/11/99 Version -001 -002 Original version Removed references configurations Removed 32-Mbit offering Appendix Query Structure, tables updated Description
28F800C2, 28F160C2
INTRODUCTION
Volt Advanced+ Boot Block Flash Memory Enhancements
This document contains specifications Volt Advanced+ Boot Block flash memory family. These flash memories features which used enhance security systems: instant block locking protection register. Throughout this document, term "2.4 refers full voltage range V-3.0 (except where noted otherwise) "VPP refers ±5%. Sections provide overview flash memory family including applications, pinouts, descriptions memory organization. Section describes operation these products. Finally, Section contains operating specifications.
Volt Advanced+ Boot Block flash memory features: Zero-latency, flexible block locking 128-bit Protection Register Simple system implementation production programming with in-field programming Ultra-low power operation Minimum 100,000 block erase cycles Common Flash Interface software query device specs features
Table Volt Advanced+ Boot Block Feature Summary Feature Operating Voltage Voltage VCCQ Voltage Width Speed (ns) Blocking (top bottom) Mbit(1), Mbit Provides complete write protection with optional Fast Programming 16-bit 8/16 Mbit: 100, 4-Kword parameter 8-Mb: 32-Kword main 16-Mb: 32-Kword main Operating Temperature Program/Erase Cycling Packages Block Locking Protection Register Extended: 100,000 cycles 48-Lead TSOP 48-Ball µBGA* CSP(1) Flexible locking block with zero latency 64-bit unique device number, 64-bit user programmable Table Section Section Appendix Reference Table Table
Table Table Figures Section Section
NOTE: 8-Mbit density available µBGA* CSP.
28F800C2, 28F160C2
Product Overview
Intel provides secure voltage memory solutions with Advanced Boot Block family products. block locking feature allows instant locking/unlocking block with zero-latency. 128-bit protection register allows unique flash device identification. Discrete supply pins provide single voltage read, program, erase capability while also allowing faster production programming. Improved feature designed reduce external logic, simplifies board designs when combining production programming with in-field programming. Volt Advanced+ Boot Block flash memory products available packages following densities: (see Section Ordering Information) 8-Mbit (8,388,608 bit) flash memories organized either Kwords bits each. 16-Mbit (16,777,216 bit) flash memories organized either 1024 Kwords bits each.
status register indicates status signifying block erase word program completion status. Program erase automation allows program erase operations executed using industrystandard two-write command sequence CUI. Program operations performed word byte increments. Erase operations erase locations within block simultaneously. Both program erase operations suspended system software order read from other block. addition, data programmed another block during erase suspend. Volt Advanced+ Boot Block flash memories offer power savings features: Automatic Power Savings (APS) standby mode. device automatically enters mode following completion read cycle. Standby mode initiated when system deselects device driving inactive. Combined, these power savings features significantly reduce power consumption. device reset lowering GND. This provides CPU-memory reset synchronization additional protection against noise that occur during system reset power-up/down sequences (see Section 3.6). Refer Characteristics Section complete current voltage specifications. Refer Characteristics Sections 4.5, read write performance specifications. Program erase times shown Section 4.6.
Eight 4-Kword parameter blocks located either (denoted suffix) bottom suffix) address order accommodate different microprocessor protocols kernel code location. remaining memory grouped into 64-Kbyte main blocks. (See Appendix blocks locked unlocked instantly provide complete protection code data. (see Section details). Command User Interface (CUI) serves interface between microprocessor microcontroller internal operation flash memory. internal Write State Machine (WSM) automatically executes algorithms timings necessary program erase operations, including verification, thereby unburdening microprocessor microcontroller.
PRODUCT DESCRIPTION
This section provides device descriptions package pinouts Volt Advanced+ Boot Block flash memory family which available 48lead TSOP (x16), 48-ball µBGA packages (Figures respectively).
Package Pinouts
48-Lead TSOP VIEW
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DQ15
NOTE: Lower densities will have upper address pins. example, 8-Mbit device will have Pins
Figure 48-Lead TSOP Package Configurations
VCCQ
NOTES: Shaded connections indicate upgrade address connections. Lower density devices will have upper address solder balls. Routing recommended this area. upgrade address 16-Mbit device. 8-Mbit available µBGA* CSP.
Figure 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
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Table Volt Advanced+ Boot Block Descriptions Symbol A0-A21 Type INPUT Name Function
ADDRESS INPUTS: Memory addresses internally latched during program erase cycle. 8-Mbit: A[0-18], 16-Mbit: A[0-19] DATA INPUTS/OUTPUTS: Inputs array data second cycle during Program command. Inputs commands Command User Interface when active. Data internally latched. Outputs array, configuration status register data. data pins float tri-state when chip de-selected outputs disabled. DATA INPUTS/OUTPUTS: Inputs array data second cycle during Program command. Data internally latched. Outputs array configuration data. data pins float tri-state when chip de-selected. CHIP ENABLE: Activates internal control logic, input buffers, decoders sense amplifiers. active low. high de-selects memory device reduces power consumption standby levels. OUTPUT ENABLE: Enables device's outputs through data buffers during read operation. active low. WRITE ENABLE: Controls writes command register memory array. active low. Addresses data latched rising edge second pulse. RESET/DEEP POWER-DOWN: Uses voltage levels VIH) control reset/deep power-down mode. When logic low, device reset/deep power-down mode, which drives outputs High-Z, resets Write State Machine, minimizes current levels CCD). When logic high, device standard operation. When transitions from logic-low logic-high, device resets blocks locked defaults read array mode.
DQ0-DQ7
INPUT/OUTPUT
DQ8-DQ15
INPUT/OUTPUT
INPUT
INPUT INPUT
INPUT
INPUT
WRITE PROTECT: Controls lock-down function flexible Locking feature When logic low, lock-down mechanism enabled blocks marked lock-down cannot unlocked through software. When logic high, lock-down mechanism disabled blocks previously locked-down locked unlocked locked through software. After goes low, blocks previously marked lock-down revert that state. Section details block locking.
SUPPLY
DEVICE POWER SUPPLY: [2.4 V-3.0 Supplies power device operations.
Symbol VCCQ
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Table Volt Advanced+ Boot Block Descriptions (Continued) Type INPUT Name Function POWER SUPPLY: Supplies power input/output buffers. [2.4 V-3.0 This input should tied directly INPUT/ SUPPLY PROGRAM/ERASE POWER SUPPLY: [1.65 V-3.0 11.4 V-12.6 Operates input logic levels control complete device protection. Supplies power accelerated program erase operations range. This cannot left floating. Lower VPPLK, protect contents against Program Erase commands. in-system read, program erase operations. this configuration, drop 1.65 allow resistor diode drop from system supply. Note that driven logic signal, 1.65. That must remain above 1.65V perform insystem flash modifications. Raise faster program erase production environment. Applying only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Section details voltage configurations.
SUPPLY
GROUND: internal circuitry. ground inputs must connected. CONNECT: driven left floating.
Block Organization
2.2.1
PARAMETER BLOCKS
Volt Advanced+ Boot Block asymmetrically-blocked architecture that enables system integration code data within single flash device. Each block erased independently others 100,000 times. address locations each block, memory maps Appendix
Volt Advanced+ Boot Block flash memory architecture includes parameter blocks facilitate storage frequently updated small parameters (i.e., data that would normally stored EEPROM). Each device contains eight parameter blocks 4-Kwords (4,096 words). 2.2.2 MAIN BLOCKS
After parameter blocks, remainder array divided into 32-Kword (32,768 words) main blocks data code storage. Each 8-Mbit 16Mbit device contains main blocks, respectively.
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PRINCIPLES OPERATION
Volt Advanced+ Boot Block flash memory family utilizes automated algorithms simplify program erase operations. allows 100% CMOS-level control inputs fixed power supplies during erasure programming. internal completely automates program erase operations while signals start operation status register reports status. handles interface data address latches, well system status requests during operation.
voltage. appropriate read mode command must issued enter corresponding mode. Upon initial device power-up after exit from reset, device automatically defaults read array mode. must driven active obtain data outputs. device selection control; when active enables flash memory device. data output control drives selected memory data onto bus. read modes, must VIH. Figure illustrates read cycle. 3.1.2 OUTPUT DISABL
Operation
Volt Advanced+ Boot Block flash memory devices read, program erase in-system local microcontroller. cycles from flash memory conform standard microcontroller cycles. Four control pins dictate data flow flash component: CE#, OE#, RP#. These operations summarized Table 3.1.1 READ
With logic-high level (VIH), device outputs disabled. Output pins placed high-impedance state. 3.1.3 STANDBY
flash memory four read modes available: read array, read configuration, read status read query. These modes accessible independent Table Operations(1) Mode Read (Array, Status, Configuration, Query) Output Disable Standby Reset Write Note 2,5-7
Deselecting device bringing logichigh level (VIH) places device standby mode, which substantially reduces device power consumption without latency subsequent read accesses. standby, outputs placed high-impedance state independent OE#. deselected during program erase operation, device continues consume active power until program erase operation complete.
DQ0-7 DOUT High High High
DQ8-15 DOUT High High High
NOTES: 8-bit devices only [0:7], 16-bit devices [0:15] must VIL, control pins addresses. Characteristics VPPLK, VPP1, VPP2, VPP3, voltages. Manufacturer device codes also accessed read configuration mode (A1-A20 Table Refer Table valid during write operation. program erase lockable blocks, hold VIH. must meet maximum deep power-down current specified.
3.1.4
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addressable memory location. address data buses latched rising edge second pulse, whichever occurs first. Figure illustrates program erase operation. available commands shown Table Appendix provides detailed information moving between different modes operation using commands. There commands that modify array data: Program (40H) Erase (20H). Writing either these commands internal Command User Interface (CUI) initiates sequence internallytimed functions that culminate completion requested task (unless that operation aborted either being driven tPLRH appropriate suspend command).
RESET
From read mode, time tPLPH deselects memory, places output drivers high-impedance state, turns internal circuits. After return from reset, time tPHQV required until initial read access outputs valid. delay (tPHWL tPHEL) required after return from reset before write initiated. After this wake-up interval, normal operation restored. resets read array mode, status register 80H, blocks locked. This case shown Figure taken time tPLPH during program erase operation, operation will aborted memory contents aborted location (for program) block (for erase) longer valid, since data partially erased written. abort process goes through following sequence: When goes low, device shuts down operation progress, process which takes time tPLRH complete. After this time tPLRH, part will either reset read array mode gone high during tPLRH, Figure enter reset mode still logic after tPLRH, Figure 9C). both cases, after returning from aborted operation, relevant time tPHQV tPHWL/tPHEL must waited before read write operation initiated, discussed previous paragraph. However, this case, these delays referenced tPLRH rather than when goes high. with automated device, important assert during system reset. When system comes reset, processor expects read from flash memory. Automated flash memories provide status information when read during program block erase operations. reset occurs with flash memory reset, proper initialization occur because flash memory providing status information instead array data. Intel's flash memories allow proper initialization following system reset through input. this application, controlled same RESET# signal that resets system CPU. 3.1.5 WRIT
Modes Operation
flash memory four read modes write modes. read modes read array, read configuration, read status, read query. write modes program erase. Three additional modes (erase suspend program, erase suspend read program suspend read) available only during suspended operations. These modes reached using commands summarized Tables comprehensive chart showing state transitions Appendix 3.2.1 READ ARRAY
When transitions from (reset) VIH, device defaults read array mode will respond read control inputs (CE#, address inputs, OE#) without additional commands. When device read array mode, four control signals control data output: must logic high (VIH) must logic (VIL) must logic (VIL) must logic high (VIH)
write takes place when both high. Commands written Command User Interface (CUI) using standard microprocessor write timings control flash operations. does occupy
addition, address desired location must applied address pins. device read array mode, would case after program erase operation, Read Array command (FFH) must written before array reads take place.
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3.2.2 READ CONFIGURATION
read configuration mode outputs manufacturer/device identifier. device switched this mode writing read configuration command (90H). Once this mode, read cycles from addresses shown Table retrieve specified information. return read array mode, write Read Array command (FFH). Read Configuration mode outputs three types information: manufacturer/device identifier, block locking status, protection register. device switched this mode writing Read Configuration command (90H). Once this mode, read cycles from addresses shown Table retrieve specified information. return read array mode, write Read Array command (FFH). Table Read Configuration Table Item Manufacturer Code (x16) Device (See Appendix Block Lock Configuration2 Block Unlocked Block Locked Block Locked-Down Protection Register Lock3 Protection Register (x16) 81-88 Address 00000 00001 XX002(1) Data 0089 LOCK PR-LK
command causes subsequent reads output data from status register until another command issued. return reading from array, issue Read Array (FFH) command. status register bits output DQ0-DQ7. upper byte, DQ8-DQ15, outputs during Read Status Register command. contents status register latched falling edge CE#, whichever occurs last. This prevents possible errors which might occur status register contents change while being read. must toggled with each subsequent status read, status register will indicate completion program erase operation. When active, SR.7 will indicate status WSM; remaining bits status register indicate whether successful performing desired operation (see Table 3.2.3.1 Clearing Status Register
NOTES: "XX" specifies block address lock configuration being read. Section 3.3.4 valid lock status outputs. Section protection register information. Other locations within configuration address space reserved Intel future use.
sets status bits through "1," clears bits "0," cannot clear status bits through "0." Because bits indicate various error conditions, these bits only cleared through Clear Status Register (50H) command. allowing system software control resetting these bits, several operations performed (such cumulatively programming several addresses erasing multiple blocks sequence) before reading status register determine error occurred during that series. Clear status register before beginning another command sequence. Note that Read Array command must issued before data read from memory array. Resetting device also clears status register. 3.2.4 READ QUERY
3.2.3
READ STATUS REGISTER
status register indicates status device operations, success/failure that operation. Read Status Register (70H)
read query mode outputs Common Flash Interface (CFI) data when device read. This accessed writing Read Query Command (98H). data structure contains information such block size, density, command electrical specifications. Once this mode, read cycles from addresses shown Appendix retrieve specified information. return read array mode, write Read Array command (FFH).
3.2.5
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Read Array command written read data from blocks other than that which suspended. only other valid commands, while program suspended, Read Status Register, Read Configuration, Read Query, Program Resume. After Program Resume command written flash memory, will continue with programming process status register bits SR.2 SR.7 will automatically cleared. device automatically outputs status register data when read (see Figure Appendix Program Suspend/Resume Flowchart) after Program Resume command written. must remain same level used program while program suspend mode. must also remain VIH. 3.2.6 ERASE
PROGRAM
Programming executed using two-write sequence. Program Setup command (40H) written followed second write which specifies address data programmed. will execute sequence internally timed events program desired bits addressed location, then verify bits sufficiently programmed. Programming memory results specific bits within address location being changed "0." user attempts program "1"s, memory cell contents change error occurs. status register indicates programming status: while program sequence executes, status "0." status register polled toggling either OE#. While programming, only valid commands Read Status Register, Program Suspend, Program Resume. When programming complete, program status bits should checked. programming operation unsuccessful, SR.4 status register indicate program failure. SR.3 then within acceptable limits, execute program command. SR.1 set, program operation attempted locked block operation aborted. status register should cleared before attempting next operation. instruction follow after programming completed; however, prevent inadvertent status register reads, sure reset read array mode. 3.2.5.1 Suspending Resuming Program
erase block, write Erase Set-up Erase Confirm commands CUI, along with address identifying block erased. This address latched internally when Erase Confirm command issued. Block erasure results bits within block being "1." Only block erased time. will execute sequence internally timed events program bits within block "0," erase bits within block "1," then verify that bits within block sufficiently erased. While erase executes, status "0." When status register indicates that erasure complete, check erase status verify that erase operation successful. Erase operation unsuccessful, SR.5 status register will "1," indicating erase failure. within acceptable limits after Erase Confirm command issued, will execute erase sequence; instead, SR.5 status register indicate erase error, SR.3 identify that supply voltage within acceptable limits. After erase operation, clear status register (50H) before attempting next operation. instruction follow after erasure completed; however, prevent inadvertent status register reads, advisable place flash read array mode after erase complete.
Program Suspend command halts inprogress program operation that data read from other locations memory. Once programming process starts, writing Program Suspend command requests that suspend program sequence predetermined points program algorithm). device continues output status register data after Program Suspend command written. Polling status register bits SR.7 SR.2 will determine when program operation been suspended (both will "1"). tWHRH1/tEHRH1 specify program suspend latency.
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3.2.6.1 Suspending Resuming Erase
Since erase operation requires order seconds complete, Erase Suspend command provided allow erase-sequence interruption order read data from program data another block memory. Once erase sequence started, writing Erase Suspend command suspends erase sequence predetermined point erase algorithm. status register will indicate if/when erase operation been suspended. Erase suspend latency specified WHRH2/tEHRH2.
Read Array/Program command written read/program data from/to blocks other than that which suspended. This nested Program command subsequently suspended read another location. only valid commands while erase suspended Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume, Erase Resume, Lock Block, Unlock Block Lock-Down Block. During erase suspend mode, chip placed pseudo-standby mode taking VIH. This reduces active current consumption. Erase Resume continues erase sequence when VIL. with standard erase operation, status register must read cleared before next instruction issued.
Table Command Definitions First Cycle Command Read Array Read Configuration Read Query Read Status Register Clear Status Register Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Program Don't Care Status Reg. Data Notes Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Addr Data 40H/10H Write Write Write Write Write Write Read Read Read Second Cycle Oper Addr Data
Prog Addr Block Addr Prog Data
Identifier Addr. Identifier Data
Query Addr. Query Data
NOTES: operations defined Table Following Read Configuration Read Query commands, read operations output device configuration query information, respectively. Section 3.2.2 3.2.4. Either command valid, Intel standard 40H. When writing commands, upper data [DQ8-DQ15] should either VIH, minimize current draw.
Table Command Codes Descriptions Code Device Mode Read Array Program Set-Up Description Erase Set-Up Erase Confirm
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Places device read array mode, such that array data will output data pins. This two-cycle command. first cycle prepares program operation. second cycle latches addresses data information initiates execute Program algorithm. flash outputs status register data when toggled. Read Array command required after programming read array data. Section 3.2.5. Prepares Erase Confirm command. next command Erase Confirm command, then will both SR.4 SR.5 status register "1," place device into read status register mode, wait another command. Section 3.2.6. previous command Erase Set-Up command, then will close address data latches, begin erasing block indicated address pins. During program/erase, device will respond only Read Status Register, Program Suspend Erase Suspend commands will output status register data when toggled. program erase operation previously suspended, this command will resume that operation. previous command Configuration Set-Up, will latch address unlock block indicated address pins. block been previously Lock-Down, this operation will have effect. (Sect. 3.3) Issuing this command will begin suspend currently executing program/erase operation. status register will indicate when operation been successfully suspended setting either program suspend (SR.2) erase suspend (SR.6) status (SR.7) (ready). will continue idle SUSPEND state, regardless state input control pins except RP#, which will immediately shut down remainder chip driven Sections 3.2.5.1 3.2.6.1. This command places device into read status register mode. Reading device will output contents status register, regardless address presented device. device automatically enters this mode after program erase operation been initiated. Section 3.2.3. block lock status (SR.1) Status (SR.3), program status (SR.4), erase status (SR.5) bits status register "1," cannot clear them "0." Issuing this command clears those bits "0." Puts device into read configuration mode, that reading device will output manufacturer/device codes block lock status. Section 3.2.2. Prepares changes device configuration, such block locking changes. next command Block Unlock, Block Lock, Block LockDown, then will both program erase status register bits indicate command sequence error. Section 3.3. previous command Configuration Set-Up, will latch address lock block indicated address pins. (Section 3.3)
Program/Erase Resume Unlock Block
Program Suspend Erase Suspend
Read Status Register
Clear Status Register Read Configuration Configuration Set-Up
Lock-Block
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Table Command Codes Descriptions (Continued) Code Device Mode Lock-Down Description
previous command Configuration Set-Up command, will latch address lock-down block indicated address pins. (Section 3.3) Puts device into read query mode, that reading device will output Common Flash Interface information. Section 3.2.4 Appendix This two-cycle command. first cycle prepares program operation protection register. second cycle latches addresses data information initiates execute Protection Program algorithm protection register. flash outputs status register data when toggled. Read Array command required after programming read array data. Section 3.4.
Read Query Protection Program Setup
Alt. Prog Set-Up Operates same Program Set-up command. (See 40H/Program Set-Up) Invalid/ Reserved Unassigned commands that should used. Intel reserves right redefine these codes future functions.
NOTE: Appendix mode transition information.
WSMS SR.5 ERASE STATUS (ES) Error Block Erase Successful Block Erase
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Table Status Register Definition VPPS NOTES:
SR.7 WRITE STATE MACHINE STATUS Ready (WSMS) Busy SR.6 ERASE-SUSPEND STATUS (ESS) Erase Suspended Erase Progress/Completed
Check Write State Machine first determine Word Program Block Erase completion, before checking Program Erase Status bits. When Erase Suspend issued, halts execution sets both WSMS bits "1." remains until Erase Resume command issued. When this "1," applied max. number erase pulses block still unable verify successful block erasure. When this "1," attempted failed program word/byte. status does provide continuous indication level. interrogates level only after Program Erase command sequences have been entered, informs system been switched also checked before operation verified WSM. status guaranteed report accurate feedback between VPPLK VPP1Min. When Program Suspend issued, halts execution sets both WSMS bits "1." remains until Program Resume command issued. program erase operation attempted locked blocks, this WSM. operation specified aborted device returned read status mode. This reserved future should masked when polling status register.
SR.4 PROGRAM STATUS (PS) Error Programming Successful Programming SR.3 STATUS (VPPS) Detect, Operation Abort
SR.2 PROGRAM SUSPEND STATUS (PSS) Program Suspended Program Progress/Completed SR.1 BLOCK LOCK STATUS Prog/Erase attempted locked block; Operation aborted. operation locked blocks SR.0 RESERVED FUTURE ENHANCEMENTS
NOTES: Command Sequence Error indicated when both SR.4 SR.5 SR.7 set.
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Flexible Block Locking
3.3.2
LOCKED STAT
Intel® Volt Advanced+ Boot Block products offer instant, individual block locking scheme that allows block locked unlocked with latency, enabling instant code data protection. This locking scheme offers levels protection. first level allows software-only control block locking (useful data blocks that change frequently), while second level requires hardware interaction before locking changed (useful code blocks that change infrequently). following sections will discuss operation locking system. term "state [XYZ]" will used specify locking states; e.g., "state [001]," where value WP#, Block Lock status register, Block Lock status register. Table defines these possible locking states. 3.3.1 LOCKING OPERATION
default status blocks upon power-up reset locked (states [001] [101]). Locked blocks fully protected from alteration. program erase operations attempted locked block will return error SR.1 status register. status locked block changed Unlocked Lock-Down using appropriate software commands. Unlocked block locked writing Lock command sequence, followed 01H. 3.3.3 UNLOCKED STAT
Unlocked blocks (states [000], [100], [110]) programmed erased. unlocked blocks return Locked state when device reset powered down. status unlocked block changed Locked Locked-Down using appropriate software commands. Locked block unlocked writing Unlock command sequence, followed D0H. 3.3.4 LOCK-DOWN STAT
following concisely summarizes locking functionality. blocks power-up locked, then unlocked locked with Unlock Lock commands. Lock-Down command locks block prevents from being unlocked when When Lock-Down overridden commands unlock/lock lockeddown blocks. When returns locked-down blocks return Lock-Down. Lock-Down cleared only when device reset powered-down. locking status each block Locked, Unlocked, Lock-Down, each which will described following sections. comprehensive state table locking functions shown Table flowchart locking operations shown Figure
Blocks that Locked-Down (state [011]) protected from program erase operations (just like Locked blocks), their protection status cannot changed using software commands alone. Locked Unlocked block Lockeddown writing Lock-Down command sequence, followed 2FH. Locked-Down blocks revert Locked state when device reset powered down. Lock-Down function dependent input pin. When blocks Lock-Down [011] protected from program, erase, lock status changes. When Lock-Down function disabled ([111]) locked-down blocks individually unlocked software command [110] state, where they erased programmed. These blocks then relocked [111] unlocked [110] desired while remains high. When goes low, blocks that were previously locked-down return Lock-Down state [011] regardless changes made while high. Device reset powerdown resets blocks, including those LockDown, Locked state.
3.3.5
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lock status will changed. After completing desired lock, read, program operations, resume erase operation with Erase Resume command (D0H). block locked locked-down during suspended erase same block, locking status bits will changed immediately, when erase resumed, erase operation will complete. Locking operations cannot performed during program suspend. Refer Appendix detailed information which commands valid during erase suspend. 3.3.7 STATUS REGISTER ERROR CHECKING
READING BLOCK'S LOCK STATUS
lock status every block read configuration read mode device. enter this mode, write device. Subsequent reads Block Address 00002 will output lock status that block. lock status represented lowest output pins, DQ1. indicates Block Lock/Unlock status Lock command cleared Unlock command. also automatically when entering Lock-Down. indicates Lock-Down status Lock-Down command. cannot cleared software, only device reset powerdown. Table Block Lock Status Item Block Lock Configuration Block Unlocked Block Locked Block Locked-Down 3.3.6 Address XX002 Data LOCK
Using nested locking program command sequences during erase suspend introduce ambiguity into status register results. Since locking changes performed using cycle command sequence, e.g., followed lock block, following Configuration Setup command (60H) with invalid command will produce lock command error (SR.4 SR.5 will status register. lock command error occurs during erase suspend, SR.4 SR.5 will will remain after erase resumed. When erase complete, possible error during erase cannot detected status register because previous locking command error. similar situation happens error occurs during program operation error nested within erase suspend.
LOCKING OPERATIONS DURING ERASE SUSPEND
Changes block lock status performed during erase suspend using standard locking command sequences unlock, lock, lock-down block. This useful case when another block needs updated while erase operation progress. change block locking during erase operation, first write erase suspend command (B0H), then check status register until indicates that erase operation been suspended. Next write desired lock command sequence block
28F800C2, 28F160C2
Table Block Locking State Transitions Erase/Prog Name "Unlocked" "Locked" (Default) "Locked-Down" "Unlocked" "Locked" Lock-Down Disabled Lock-Down Disabled Allowed? Lock Command Input Result [Next State] Lock Goes [001] Change Change Goes [101] Change Goes [111] Change Unlock Change Lock-Down Goes [011] Goes [000] Goes [011] Change Change Change Goes [111] Goes [100] Goes [111] Change Goes [110] Goes [111] Change
Current State
NOTES: this table, notation [XYZ] denotes locking state block, where WP#, DQ1, DQ0. current locking state block defined state bits block lock status DQ1). indicates block locked unlocked (0). indicates block been locked-down (0). power-up device reset, blocks default Locked state [001] Holding recommended default. "Erase/Program Allowed?" column shows whether erase program operations enabled (Yes) disabled (No) that block's current locking state. "Lock Command Input Result [Next State]" column shows result writing three locking commands (Lock, Unlock, Lock-Down) current locking state. example, "Goes [001]" would mean that writing command block current locking state would change [001].
128-Bit Protection Register
3.4.1
READING PROTECTION REGISTER
Advanced+ Boot Block architecture includes 128-bit protection register than used increase security system design. example, number contained protection register used "mate" flash component with other system components such ASIC, preventing device substitution. Additional application information found Intel application note AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture 128-bits protection register divided into 64-bit segments. segments programmed Intel factory with unique 64-bit number, which unchangeable. other segment left blank customer designs program desired. Once customer segment programmed, locked prevent reprogramming.
protection register read configuration read mode. device switched this mode writing Read Configuration command (90H). Once this mode, read cycles from addresses shown Appendix retrieve specified information. return read array mode, write Read Array command (FFH). 3.4.2 PROGRAMMING PROTECTION REGISTER
protection register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time word-wide parts eight bits time bytewide parts. First write Protection Program Setup command, C0H. next write device will latch address data program specified location. allowable addresses shown Appendix Figure Protection Register Programming Flowchart.
3.4.3
28F800C2, 28F160C2
Attempts address Protection Program commands outside defined protection register address space should attempted. This space reserved future use. Attempting program previously locked protection register segment will result status register error (program error SR.4 lock error SR.1 will LOCKING PROTECTION REGISTER
Program Erase Voltages
Intel's Volt Advanced+ Boot Block products provide in-system programming erase 1.65 V-3.0 range. fast production programming, also includes low-cost, backwardcompatible programming feature. 3.5.1 IMPROVED OPERATION PRODUCTION PROGRAMMING
user-programmable segment protection register lockable programming PR-LOCK location this location programmed Intel factory protect unique device number. This using Protection Program command program "FFFD" PR-LOCK location. After these bits have been programmed, further changes made values stored protection register. Protection Program commands locked section will result status register error (program error SR.4 Lock Error SR.1 will Protection register lockout state reversible.
When between 1.65 program erase current drawn through pin. Note that driven logic signal, 1.65 That must remain above 1.65 perform in-system flash modifications. When connected power supply, device draws program erase current directly from pin. This eliminates need external switching transistor control voltage VPP. Figure shows examples flash power supplies configured various usage models. mode enhances programming performance during short period time typically found manufacturing processes; however, intended extended use. applied during program erase operations maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Stressing device beyond these limits cause permanent damage. 3.5.2 VPPLK COMPLETE PROTECTION
Words User Programmed Words Factory Programmed PR-LOCK
0645_05
Figure Protection Register Memory
addition flexible block locking, programming voltage held absolute hardware write protection blocks flash device. When below VPPLK, program erase operation will result error, prompting corresponding status register (SR.3) set.
28F800C2, 28F160C2
System Supply
System Supply Supply
Prot# (Logic Signal)
Fast Programming Absolute Write Protection With VPPLK System Supply
(Note
Low-Voltage Programming Absolute Write Protection Logic Signal System Supply
Low-Voltage Programming
0645_06
Supply Voltage Fast Programming
NOTE: resistor used supply sink adequate current based resistor value. AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture details.
Figure Example Power Supply Configurations
Power Consumption
3.6.2
AUTOMATIC POWER SAVINGS (APS)
Intel's flash devices have tiered approach power savings that significantly reduce overall system power consumption. Automatic Power Savings (APS) feature reduces power consumption when device selected idle. deasserted, flash enters standby mode, where current consumption even lower. combination these features minimize memory power consumption, therefore, overall system power consumption. 3.6.1 ACTIVE POWER (Program/Erase/Read)
Automatic Power Savings provides low-power operation during read mode. After data read from memory array address lines quiescent, circuitry places device mode where typical current comparable ICCS. flash stays this static state with outputs valid until location read. 3.6.3 STANDBY POWER
With logic-low level logichigh level, device active mode. Refer Characteristic tables current values. Active power largest contributor overall system power consumption. Minimizing active current could have profound effect system power consumption, especially battery-operated devices.
With logic-high level (VIH) device read mode, flash memory standby mode, which disables much device's circuitry substantially reduces power consumption. Outputs placed high-impedance state independent status signal. transitions logic-high level during erase program operations, device will continue perform operation consume corresponding active power until operation completed.
System engineers should analyze breakdown standby time versus active time quantify respective power consumption each mode their specific application. This will provide more accurate measure application-specific power energy requirements. 3.6.4 DEEP POWER-DOWN
28F800C2, 28F160C2
System designers must guard against spurious writes when voltages above VLKO. Since both must command write, driving either signal will inhibit writes device. architecture provides additional protection since alteration memory contents only occur after successful completion twostep command sequences. device also disabled until brought VIH, regardless state control inputs. holding device reset (RP# connected system PowerGood) during power-up/down, invalid conditions during power-up masked, providing another level memory protection. 3.7.2 VCC, TRANSITIONS
deep power-down mode activated when (GND During read modes, going de-selects memory places outputs high impedance state. Recovery from deep power-down requires minimum time tPHQV read operations tPHWL/tPHEL write operations. During program erase modes, transitioning will abort in-progress operation. memory contents address being programmed block being erased longer valid data integrity been compromised abort. During deep power-down, internal circuits switched power savings mode (RP# transitioning turning power device clears status register).
latches commands issued system software altered transitions actions. default state upon power-up, after exit from reset mode after transitions above VLKO (Lockout voltage), read array mode. After program block erase operation complete (even after transitions down VPPLK), must reset read array mode Read Array command access flash memory array desired.
Power-Up/Down Operation
device protected against accidental block erasure programming during power transitions. Power supply sequencing required, since device indifferent which power supply, VCC, powers-up first. 3.7.1 CONNECTED SYSTEM RESET
Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling. System designers should consider three supply current issues: Standby current levels (ICCS) Read current levels (ICCR) Transient peaks produced falling rising edges CE#. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have ceramic capacitor connected between each GND, between GND. These highfrequency, inherently low-inductance capacitors should placed close possible package leads.
during system reset important with automated program/erase devices since system expects read from flash memory when comes reset. reset occurs without flash memory reset, proper initialization will occur because flash memory providing status information instead array data. Intel recommends connecting system RESET# signal allow proper CPU/flash initialization following system reset.
28F800C2, 28F160C2
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings*
Extended Operating Temperature During Read During Block Erase Program. Temperature Under Bias. Storage Temperature. +125 Voltage (except VPP) with Respect -0.5 +3.7 Voltage (for Block Erase Program) with Respect .-0.5 +13.5 V1,2,4 VCCQ Supply Voltage with Respect -0.2 +3.0 Output Short Circuit Current.
NOTICE: This datasheet contains preliminary information products production. finalize design with this information. Revised information will published when product available. Verify with your local Intel Sales office that have latest datasheet before finalizing design.
WARNING: Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" effect device reliability.
NOTES:
Minimum voltage -0.5 input/output pins. During transitions, this level undershoot -2.0 periods Maximum voltage input/output pins which, during transitions, overshoot periods Maximum voltage overshoot +14.0 periods Output shorted more than second. more than output shorted time. voltage normally 1.65 V-3.0 Connection supply 11.4 V-12.6 only done 1000 cycles main blocks 2500 cycles parameter blocks during program/erase. connected total hours maximum. Section details.
Operating Conditions
Table Temperature Voltage Operating Conditions
Symbol VCC1 VCC2 VCCQ1 VPP1 VPP2 Cycling
Parameter Operating Temperature Supply Voltage
Notes
12.6
Units Volts
1.65 11.4 100,000
Supply Voltage Supply Voltage
Volts Volts Volts Cycles
Block Erase Cycling
NOTES: VCCQ must share same supply when they VCC1 range. Applying 11.4 V-12.6 during program/erase only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Section details.
COUT
28F800C2, 28F160C2
Capacitance
Parameter Input Capacitance Output Capacitance Notes Units VOUT Conditions
NOTE: Sampled, 100% tested.
Characteristics
VCCQ V-3.0 V-3.0 Unit Test Conditions VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQ VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQMax MHz, IOUT Inputs VPP1 Program Progress VPP2 Program Progress VPP1 Erase Progress VPP2 Erase Progress
Parameter Input Load Current
Note
Output Leakage Current
ICCS
Standby Current
ICCD
Deep Power-Down Current
ICCR
Read Current
1,5,7
ICCW
Program Current
Erase Current
28F800C2, 28F160C2
Characteristics (Continued)
VCCQ V-3.0 V-3.0 Unit
Test Conditions VIH, Erase Suspend Progress VIH, Program Suspend Progress 0.05 =VPP1 Program Progress VPP2 Program Progress VPP1 Program Progress VPP2 Program Progress VPP1 Erase Suspend Progress VPP2 Erase Suspend Progress VPP1 Program Suspend Progress VPP2 Program Suspend Progress
ICCES ICCWS IPPD
Parameter Erase Suspend Current Program Suspend Current Deep Power-Down Current Standby Current Read Current
Note 1,2,4 1,2,4
IPPS IPPR
IPPW
Program Current
Erase Current
0.05
IPPES
Erase Suspend Current
IPPWS
Program Suspend Current
28F800C2, 28F160C2
Characteristics (Continued)
VCCQ Parameter Input Voltage Input High Voltage Output Voltage Note V-3.0 V-3.0 -0.4 -0.10 *0.22 VCCQ +0.3 0.10 Unit VCCMin VCCQ VCCQMin VCCMin VCCQ VCCQMin -100 Complete Write Protection Test Conditions
Output High Voltage
VCCQ 1.65 11.4 12.6
VPPLK VPP1 VPP2 VLKO VLKO2
Lock-Out Voltage during Program Erase Operations Prog/Erase Lock Voltage VCCQ Prog/Erase Lock Voltage
NOTES: currents unless otherwise noted. Typical values nominal VCC, ICCES ICCWS specified with device de-selected. device read while erase suspend, current draw ICCES ICCR. device read while program suspend, current draw ICCR. Erase Program inhibited when VPPLK guaranteed outside valid ranges VPP1 VPP2. Sampled, 100% tested. Automatic Power Savings (APS) reduces ICCR approximately standby levels static operation (CMOS inputs). Applying 11.4 V-12.6 during program/erase only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Section details. test conditions VCCMax, VCCQMax, VCCMin, VCCQMin refer maximum minimum VCCQ voltage listed each column.
28F800C2, 28F160C2
VCCQ TEST POINTS VCCQ OUTPUT
0645_07
VCCQ INPUT
Figure Input/Output Reference Waveform
Test Configuration Component Values Table Test Configuration VCCQ Device Under Test
0645_08
(pF)
V-3.0 Standard Test
NOTE: includes capacitance.
Figure Test Configuration
Density Product tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ Parameter Read Cycle Time Address Output Delay Output Delay Output Delay Output Delay Output Output Output High Output High Output Hold from Address, CE#, Change, Whichever Occurs First Note -100 V-3.0 V-3.0 8/16 Mbit
28F800C2, 28F160C2
Characteristics-Read Operations(1,4)-Extended Temperature
-120 V-3.0 V-3.0 Unit
NOTES: Figure Waveform: Read Operations. delayed tELQV-tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Figure Input/Output Reference Waveform timing measurements maximum allowable input slew rate.
28F800C2, 28F160C2
Device Address Selection Address Stable Data Valid Standby High Valid Output High
ADDRESSES DATA (D/Q) RP#(P)
Figure Waveform: Read Operations
tPHEL tELWL/ tWLEL tELEH
28F800C2, 28F160C2
Characteristics-Write Operations(1,5,6)-Extended Temperature
Density Product Parameter High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold Time from (CE#) High Data Hold Time from (CE#) High Address Hold Time from (CE#) High (CE#) Pulse Width High Setup (CE#) Going High Hold from Valid Setup (CE#) Going High Hold from Valid Note -100 8/16 Mbit -120 Unit
tPHWL/
tWLWH/ tDVWH/ tDVEH tAVWH/ tAVEH tEHWH/ tWHEH tWHDX/ tEHDX tWHAX/ tEHAX tWHWL/ tEHEL tVPWH/ tVPEH tQVVL tBHWH tBHEH
tQVBL
28F800C2, 28F160C2
NOTES: Write timing characteristics during erase suspend same during write-only operations. Refer Table valid DIN. Sampled, 100% tested. Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, Write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. Figure Input/Output Reference Waveform timing measurements maximum allowable input slew rate. Figure Waveform: Program Erase Operations.
Unit
Erase Program Timings(1)
Symbol Parameter 4-KW Parameter Block Word Program Time 32-KW Main Block Word Program Time Word Program Time 4-KW Parameter Block Erase Time 32-KW Main Block Erase Time Program Suspend Latency Erase Suspend Latency Note 1.65 V-3.0 Typ(1) 0.10 0.30 11.4 V-12.6 Typ(1) 0.03 0.24 0.12
tBWPB tBWMB tWHQV1 tEHQV1 tWHQV2 tEHQV2 tWHQV3 tEHQV3 tWHRH1 tEHRH1 tWHRH2 tEHRH2
NOTES: Typical values measured nominal voltages. Excludes external system-level overhead. Sampled, 100% tested.
(WE#) [E(W)] (CE) [W(E)]
High (Note
28F800C2, 28F160C2
ADDRESSES
(Note
DATA [D/Q]
Valid
VPPH2 VPPLK
NOTES: must toggled when reading Status Register Data. must inactive (high) when reading Status Register Data. Power-Up Standby. Write Program Erase Setup Command. Write Valid Address Data (for Program) Erase Confirm Command. Automated Program Erase Delay. Read Status Register Data (SRD): reflects completed program/erase operation. Write Read Array Command.
Figure Waveform: Program Erase Operations
28F800C2, 28F160C2
Reset Operations
PLPH Reset during Read Mode
PHQV PHWL PHEL
Abort Complete
PLRH
PHQV PHWL PHEL
PLPH Reset during Program Block Erase, PLPH PLRH
Abort Deep Complete PowerDown
PLRH
PHQV PHWL PHEL
PLPH
Reset Program Block Erase, PLPH PLRH
Figure Waveform: Reset Operation Table Reset Specifications(1) V-3.0 Symbol tPLPH Parameter Reset during Read tied VCC, this specification applicable) Reset during Block Erase Reset during Program Notes Unit
tPLRH1 tPLRH2
NOTES: Section 3.1.4 full description these conditions. tPLPH device still reset this guaranteed. asserted while block erase word program operation executing, reset will complete within Sampled, 100% tested.
28F800C2, 28F160C2
ORDERING INFORMATION
Package 48-Lead TSOP 48-Ball µBGA* Product line designator Intel® Flash products
Access Speed (ns) 8/16 Mbit =100, Blocking Bottom Blocking Product Family Advanced+ Boot Block 1.65 11.4
Device Density Mbit) Mbit)
VALID COMBINATIONS (All Extended Temperature) Extended TE28F160C2TA100 TE28F160C2BA100 TE28F160C2TA120 TE28F160C2BA120 Extended TE28F800C2TA100 TE28F800C2BA100 TE28F800C2TA120 TE28F800C2BA120
NOTE: second line 48-ball µBGA package side mark specifies assembly codes. samples only, first character signifies either engineering samples silicon daisy chain samples. other assembly codes without first character production units.
GT28F160C2TA100 GT28F160C2BA100 GT28F160C2TA120 GT28F160C2BA120
28F800C2, 28F160C2
ADDITIONAL INFORMATION(1,2)
Order Number 298006 210830 297645 292216 292215 Contact your Intel Representative 297874 Document/Tool
Volt Advanced+ Boot Block Flash Memory Specification Update Flash Memory Databook Volt Advanced+ Boot Block Flash Memory; 28F800C3, 28F160C3, 28F320C3 datasheet AP-658 Designing Upgrade Advanced+ Boot Block Flash Memory AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture Flash Data Integrator (FDI) Software Developer's Interactive: Play with Intel's Flash Data Integrator Your
NOTES: Please call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. Visit Intel's World Wide home page http://www.Intel.com http://developer.intel.com technica documentation tools.
Current State Read Array Read Status Read Config. Read Query Lock Setup Lock Cmd. Error Lock Oper. (Done) Prot. Prog. Setup Prot. Prog. (Not Done) Prot. Prog. (Done) Prog. Setup Program (Not Done) Prog. Susp. Status Prog. Susp. Read Array Prog. Susp. Read Config Prog. Susp. Read Query Program (Done) Erase Setup Erase Cmd. Error Erase (Not Done) Ers. Susp. Status Erase Susp. Array Ers. Susp. Read Config Ers. Susp. Read Query Erase (Done) Status Status Status Status Array Config Status SR.7 Data When Read Array Status Config Status Status Status Status Status Status Status Status Status Array Config Status
28F800C2, 28F160C2
APPENDIX CURRENT/NEXT STATES
Command Input (and Next State) Read Array (FFH) Read Array Read Array Read Array Read Array Program Setup (10/40H) Program Setup Program Setup Program Setup Program Setup Erase Setup (20H) Erase Setup Erase Setup Erase Setup Erase Setup Lock (Done) Erase Setup Erase Setup Erase Confirm (D0H) Prog/Ers Suspend (B0H) Read Array Read Array Read Array Read Array Lock Cmd. Error Read Array Read Array Protection Register Program Protection Register Program (Not Done) Read Array Program Setup Erase Setup Read Array Program Program (Not Done) Prog. Sus. Read Array Prog. Sus. Read Array Prog. Sus. Read Array Prog. Sus. Read Array Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Setup Erase Setup Erase (Not Done) Erase Setup Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Prog. Sus. Status Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Read Array Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Prog. Sus. Status Prog. Sus. Status Prog. Sus. Status Prog. Sus. Status Read Status Erase (Not Done) Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Read Array Read Status Read Array Lock (Done) Prog/Ers Resume (D0) Read Status (70H) Read Status Read Status Read Status Read Status Clear Status (50H) Read Array Read Array Read Array Read Array
Lock Command Error Read Array Read Array Program Setup Program Setup
Lock Cmd. Error Read Status Read Status Read Array Read Array
Erase Command Error Read Array Program Setup
Erase Cmd. Error Read Array Erase Sus. Status
Erase Command Error Read Status Read Array
Erase (Not Done) Erase Sus. Read Array Erase Sus. Read Array Erase Sus. Read Array Erase Sus. Read Array Read Array Program Setup Program Setup Program Setup Program Setup Program Setup Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Erase Setup Erase Erase Erase Erase
Erase (Not Done) Erase Erase Erase Erase Erase Sus. Status Erase Sus. Status Erase Sus. Status Erase Sus. Status Read Status Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Read Array
Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Read Array
28F800C2, 28F160C2
APPENDIX CURRENT/NEXT STATES (Continued)
Command Input (and Next State) Current State Read Config (90H) Read Config. Read Config. Read Config. Read Config. Read Query (98H) Read Query Read Query Read Query Read Query Lock Setup (60H) Lock Setup Lock Setup Lock Setup Lock Setup Prot. Prog. Setup (C0H) Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Lock Confirm (01H) Lock Down Confirm (2FH) Read Array Read Array Read Array Read Array
Unlock Confirm (D0H)
Read Array Read Status Read Config. Read Query Lock Setup Lock Cmd. Error Lock Operation (Done) Prot. Prog. Setup Prot. Prog. (Not Done) Prot. Prog. (Done) Prog. Setup Program (Not Done) Prog. Susp. Status Prog. Susp. Read Array Prog. Susp. Read Config. Prog. Susp. Read Query. Program (Done) Erase Setup Erase Cmd. Error Erase (Not Done) Erase Suspend Status Erase Suspend Array Eras Sus. Read Config Eras Sus. Read Query Ers.(Done)
Locking Command Error Read Config. Read Config. Read Query Read Query Lock Setup Lock Setup Prot. Prog. Setup Prot. Prog. Setup
Lock Operation (Done) Read Array Read Array
Protection Register Program Protection Register Program (Not Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Program Program (Not Done) Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Config. Read Config. Prog. Susp. Read Query Prog. Susp. Read Query Prog. Susp. Read Query Prog. Susp. Read Query Read Query Lock Setup Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Prot. Prog. Setup Read Array Erase (Not Done) Read Array Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Read Array
Erase Command Error Read Config. Read Query Lock Setup Prot. Prog. Setup Erase (Not Done) Erase Suspend Read Config. Erase Suspend Read Config. Erase Suspend Read Config. Erase Suspend Read Config. Read Config. Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Read Query Lock Setup Lock Setup Lock Setup Lock Setup Lock Setup Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Prot. Prog. Setup Read Array
Erase (Not Done) Erase (Not Done) Erase (Not Done) Erase (Not Done)
Start Write
28F800C2, 28F160C2
APPENDIX PROGRAM/ERASE FLOWCHARTS
Operation Write Write
Command Program Setup Program
Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Program Address/Data
Read
Read Status Register
Standby
SR.7 Full Status Check Desired
Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4 SR.1 Program Successful
error detected, clear status register before attempting retry other error recovery.
Operation Standby
Command
Comments Check SR.3 Detect Check SR.4 Program Error Check SR.1 Attempted Program Locked Block Program Aborted
Range Error Programming Error
Standby
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine.
Attempted Program Locked Block Aborted
SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases where multiple bytes programmed before full status checked.
Figure Automated Word Programming Flowchart
28F800C2, 28F160C2
Operation Write Command Program Suspend Read Status Comments Data Addr Data=70H Addr=X Status Register Data Toggle Update Status Register Data Addr Check SR.7 Ready Busy Check SR.2 Program Suspended Program Completed Read Array Data Addr Read array data from block other than being programmed. Program Resume Data Addr Write Read Standby Standby Write
Start
Write
Write
Read Status Register
SR.7 SR.2
Program Completed
Read
Write
Write
Read Array Data
Done Reading Write
Write
Program Resumed
Read Array Data
Figure Program Suspend/Resume Flowchart
Start
Operation Command
28F800C2, 28F160C2
Comments Data Addr Within Block Erased Data Addr Within Block Erased Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write
Write
Erase Setup
Write Block Address
Write
Erase Confirm
Read
Read Status Register
Suspend Erase Loop Suspend Erase
Standby
SR.7 Full Status Check Desired
Repeat subsequent block erasures. Full Status Check done after each block erase after sequence block erasures. Write after last write operation reset device read array mode.
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.5 SR.1 Block Erase Successful Attempted Erase Locked Block Aborted
SR.1, only cleared Clear Staus Register Command, cases where multiple bytes erased before full status checked. error detected, clear status register before attempting retry other error recovery. Operation Standby Command Comments Check SR.3 Detect Check SR.4,5 Both Command Sequence Error Check SR.5 Block Erase Error Check SR.1 Attempted Erase Locked Block Erase Aborted
Range Error
Standby
Command Sequence Error
Standby
Standby
Block Erase Error
MUST cleared, during erase attempt, before further attempts allowed Write State Machine.
Figure Automated Block Erase Flowchart
28F800C2, 28F160C2
Operation Write Command Erase Suspend Read Status Comments Data Addr Data=70H Addr=X Status Register Data Toggle Update Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Erase Suspended Erase Completed Read Array Data Addr Read array data from block other than being erased. Erase Resume Data Addr Write Read Standby Standby Write
Start
Write
Write
Read Status Register
SR.7 SR.6
Erase Completed
Read
Write
Write
Read Array Data
Done Reading Write
Write
Erase Resumed
Read Array Data
Figure Erase Suspend/Resume Flowchart
Start
Operation Write Command Config. Setup
28F800C2, 28F160C2
Comments Data Addr Data= (Lock Block) (Unlock Block) (Lockdown Block) Addr=Within block lock Data Addr Block Lock Status Data Addr Second addr block Confirm Locking Change DQ1, DQ0. (See Block Locking State Table valid combinations.)
Write (Configuration Setup) Write 01H, D0H,
Write
Lock, Unlock, Lockdown Read Configuration Block Lock Status
Write (Optional) Read (Optional) Standby (Optional)
Write (Read Configuration)
Optional
Read Block Lock Status
Locking Change Confirmed? Write (Read Array)
Locking Change Complete
Figure Locking Operations Flowchart
28F800C2, 28F160C2
Operation Write Write Command Protection Program Setup Protection Program Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy Read Standby
Start
Write (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read Status Register
SR.7 Full Status Check Desired
Protection Program operations only addressed within protection register address space. Addresses outside defined space will return error. Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3, SR.4 Range Error SR.1, SR.4
Standby Operation Standby Command Comments SR.1 SR.3 SR.4 Prot. Reg. Prog. Error Register Locked: Aborted
Protection Register Programming Error Attempted Program Locked Register Aborted
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine.
SR.1, SR.4
SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases multiple protection register program operations before full status checked. error detected, clear status register before attempting retry other error recovery.
Program Successful
Figure Protection Register Programming Flowchart
28F800C2, 28F160C2
APPENDIX COMMON FLASH INTERFACE QUERY STRUCTUR
This appendix defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component. Query part overall specification multiple command control interface descriptions called Common Flash Interface, CFI. QUERY STRUCTURE OUTPUT
Query "database" allows system software gain information controlling flash component. This section describes device's CFI-compliant interface that allows host system access Query data. Query data always presented lowest-order data outputs (DQ0-7) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16) device, first bytes Query structure, ASCII, appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. Thus, device outputs ASCII byte (DQ0-7) high byte (DQ8-15). Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address. following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have upper byte this mode. Table Summary Query Structure Output Function Device Mode Device Device Addresses Offset Code ASCII Value
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Byte Addressing Value D15-D0 Offset A7-A0 PrVendor PrVendor TblAdr AltVendor P_IDLO P_IDLO P_IDHI Code D7-D0 PrVendor Value
Table Example Query Structure Output Devices Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0051 0052 0059 P_IDLO P_IDHI A_IDLO A_IDHI Code
QUERY STRUCTURE OVERVIEW
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." structure sub-sections address locations summarized below. Table Query Structure(1) Offset (BA+2)h(2) 04-0Fh P(3) Block Status Register Sub-Section Name Description Manufacturer Code Device Code Block-Specific Information
Reserved
Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table
Reserved Vendor-Specific Information
Command Vendor Data Offset Device Timing Voltage Information Flash Device Layout Vendor-Defined Additional Information Specific Primary Vendor Algorithm
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. beginning location Block Address (e.g., 08000h beginning location block when block size Kword). Offset defines which points Primary Intel-specific Extended Query Table.
Offset (BA+2)h
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BLOCK LOCK STATUS REGISTER
Block Status Register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations Block Erase Status (BSR.1) allows system software determine success last block erase operation. BSR.1 used just after power-up verify that supply accidentally removed during erase operation. This only reset issuing another erase operation block. Block Status Register accessed from word address within each block. Table Block Status Register Length Description Block Lock Status Register BSR.0 Block Lock Status Unlocked Locked BSR.1 Block Lock-Down Status locked down Locked down 2-7: Reserved future Add. BA+2: BA+2: Value (bit
BA+2:
(bit
BA+2:
(bit 2-7):
NOTES: beginning location Block Address (i.e., 008000h block (64KB block) beginning location word mode).
QUERY IDENTIFICATION STRING
Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s). Table Identification Offset Length Description Query-unique ASCII string "QRY" Add.
Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code. 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
28F800C2, 28F160C2
Offset SYSTEM INTERFACE INFORMATION Table System Interface Information Length Description logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical
Add. Code Value 11.4 12.6
Offset
28F800C2, 28F160C2
DEVICE GEOMETRY DEFINITION Table Device Geometry Definition Length Description such that device size number bytes Flash device interface: async async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 such that maximum number bytes write buffer Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks. Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Code Table below
Device Geometry Definition Address Mbit Mbit
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INTEL-SPECIFIC EXTENDED QUERY TABLE Table Primary-Vendor Specific Extended Query Description (Optional flash features commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0." then another field optional features follows bit-30 field. Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant individual block locking supported Protection bits supported Page mode read supported Synchronous read supported Supported functions after suspend: Read Array, Status, Query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend Block status register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status register active Block Lock-Down Status active logic supply highest performance program/erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts Add.
Code Value
Offset(1) Length (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h
(P+9)h
(P+A)h (P+B)h
(P+C)h
(P+D)h
12.0
Table Protection Register Information Offset(1) Length (P+E)h (P+F)h (P+10)h (P+11)h (P+12)h Description (Optional flash features commands) Number Protection register fields JEDEC space. "00h," indicates that protection bytes available Protection Field Protection Description This field describes user-available Time Programmable (OTP) Protection register bytes. Some preprogrammed with device-unique serial numbers. Others user programmable. Bits 0-15 point Protection register Lock byte, section's first byte. following bytes factory pre-programmed user-programmable. bits Lock/bytes Jedec-plane physical address bits 8-15 Lock/bytes Jedec-plane physical high address bits 16-23 such that factory pre-programmed bytes bits 24-31 such that user programmable bytes Reserved future
28F800C2, 28F160C2
Add.
Code
Value byte byte
(P+13)h
NOTES: variable pointer which defined offset 15h.
28F800C2, 28F160C2
APPENDIX ARCHITECTURE BLOCK DIAGRAM
Logic
DQ0-DQ15
VCCQ Output Buffer Input Buffer
Output Multiplexer
Status Register
Data Register
Identifier Register
Power Reduction Control A0-A19 Y-Decoder Input Buffer 4-KWord Parameter Block
Data Comparator
Command User Interface
Y-Gating/Sensing 4-KWord Parameter Block 32-KWord Main Block
Write State Machine 32-KWord Main Block
Program/Erase Voltage Switch
Address Latch Address Counter
X-Decoder
Size (KW)
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APPENDIX WORD-WIDE MEMORY DIAGRAMS
8-Mbit 16-Mbit Word-Wide Memory Addressing Boot 7F000-7FFFF 7E000-7EFFF 7D000-7DFFF 7C000-7CFFF 7B000-7BFFF 7A000-7AFFF 79000-79FFF 78000-78FFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF Size (KW) This column continues next page Bottom Boot
This column continues next page
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8-Mbit 16-Mbit Word-Wide Memory Addressing (Continued) Boot Size (KW) 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF Size (KW) Bottom Boot
F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
APPENDIX DEVICE TABLRead Configuration Addresses Data Item Manufacturer Code Device Code 8-Mbit 16-T 8-Mbit 16-B 16-Mbit 16-T 16-Mbit 16-B 00001 00001 00001 00001 88C0 88C1 88C2 88C3 Address 00000 Data 0089
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NOTE: Other locations within configuration address space reserved Intel future use.
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APPENDIX PROTECTION REGISTER ADDRESSING
Word-Wide Protection Register Addressing Word LOCK Both Factory Factory Factory Factory User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e.,

VOLT ADVANCED+ BOOT BLOCK FLASH MEMORY 28F800C2, 28F160C2 (x16)

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