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Datasheet October 2000 Document Reference Number: 290690-001


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82807AA Video Controller (VCH)
Datasheet October 2000
Document Reference Number: 290690-001
82807AA
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® 82807AA contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. 2-wire communications bus/protocol developed Philips. SMBus subset bus/protocol developed Intel. Implementations bus/protocol require licenses from various entities, including Philips Electronics N.V. North American Philips Corporation. Alert result Intel-IBM Advanced Manageability Alliance trademark Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation www.intel.com call 1-800-548-4725 *Third-party brands names property their respective owners. Copyright Intel Corporation 2000
Datasheet
82807AA
Contents
Introduction Product Features. Description 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. 3.9. 3.10. 3.11. 4.1. Notation Interface Signals DVOr Interface Signals. CMOS Interface Signals. LVDS Interface Signals GMBus Signals. Signals. Mvssiscellaneous Signals. 82807AA Core Power Ground States 82807AA 4.1.1. Connection 4.1.2. Data Format 4.1.3. Timing Controls 4.1.4. Differential Clocking 4.1.5. Stalling DVOr Interface LVDS Interface. 4.3.1. Clock Pair 4.3.2. Data Pair 82807AA Display Modes 5.1.1. Normal Mode. 5.1.2. 82815EM Centering 5.1.3. 82815EM Panning. 5.1.4. Panel-fitting Mode 5.1.5. Bypass Mode. GMBus Interface 5.2.1. Base Address 5.2.2. Index Address 5.2.3. Transfer Format Register Description 6.1.1. Header 6.1.1.1. VR00 82807AA Revision GMbus Base Address 6.1.1.2. VR01 82807AA Functionality Enable 6.1.2. Interfaces
Interface Description
4.2. 4.3.
82807AA Basic Operation 5.1.
5.2.
Register Description. 6.1.
Datasheet
82807AA
6.1.3.
6.1.4.
6.1.5.
6.1.6. 6.1.7.
6.1.8.
6.1.2.1. VR10 Interface Format 6.1.2.2. VR11 CMOS Output Control 6.1.2.3. VR12 LVDS Output Control 6.1.3.1. VR18 clock select 6.1.3.2. VR19 clock divisor 6.1.3.3. VR1A clock divisor.40 Flat Panel Timing.41 6.1.4.1. VR22 Horizontal Start Delay 6.1.4.2. VR23 Horizontal Delay 6.1.4.3. VR24 Horizontal Start Delay.41 6.1.4.4. VR25 Horizontal Delay 6.1.4.5. VR26 Vertical Start Delay 6.1.4.6. VR27 Vertical Delay Power Sequencing Panel Protection 6.1.5.1. VR30 Panel Power Shut Down Status 6.1.5.2. VR31 Tpon Panel Power-on Sequencing Delay 6.1.5.3. VR32 Tpoff Panel Power-off Sequencing Delay 6.1.5.4. VR33 Tstay Panel Power-off Stay Down Delay 6.1.5.5. VR34 Maximum Pulse Interval 6.1.5.6. VR35 Maximum Pulse Interval Panel Fitting 6.1.6.1. VR40 Panel Fitting Controls GPIO 6.1.7.1. VR80 GPIO0 Control.47 6.1.7.2. VR81 GPIO1 Control.47 6.1.7.3. VR82 GPIO Control.48 6.1.7.4. VR83 GPIO Control.48 6.1.7.5. VR84 GPIO Control.48 6.1.7.6. VR85 GPIO Control.49 6.1.7.7. VR86 GPIO Control.50 6.1.7.8. VR87 GPIO Control.51 6.1.7.9. VR88 GPIO Control.51 Graphics BIOS Scratch Space 6.1.8.1. VR8E Video BIOS Scratch Register 6.1.8.2. VR8F Video BIOS Scratch Register 1.52
Functional Description 7.1. Timing Control.53 7.1.1. Timing Reference Point Generation 7.1.1.1. Flat Panel Timing Diagram Scaling.55 7.2.1. Scaling Algorithm 7.2.1.1. Bi-Linear Interpolation 7.2.1.2. Multiple Segmented High Order Curve Interpolation LVDS Transmitter 7.3.1. 7.3.1.1. Serializer With Control Panel Protection Power Sequencing.57 7.4.1. Panel Protection.57 7.4.1.1. Panel Power Sequencing Bypassing.57 7.5.1. DVOrRCOM.58 7.5.2. DVOr Electrical Isolation
7.2.
7.3.
7.4.
7.5.
Datasheet
82807AA
7.6.
7.5.3. Spread-Spectrum Clocking Support. Power Supply. 7.6.1. System Connection 82807AA Pinout Physical Dimensions Related Documents References Electrical Characteristics 9.2.1. Absolute Maximum Ratings 9.2.2. Signal Groups. 9.2.3. Characteristics 9.2.4. Characteristics 9.2.4.1. Phase Lock Loop Clock Input Timing. 9.2.4.2. Digital Video Out(DVO) Port Interface Timing 9.2.5. 82807AA LVDS Switching Characteristics 9.2.5.1. CMOS Panel Interface Timing. 82807AA Timing Diagrams. 9.3.1. 82807AA LVDS Timing Diagrams Power/Thermal Characteristics 9.4.1. Power Characteristics 9.4.2. Thermal Management Introduction 9.4.3. Importance Thermal Management. 9.4.3.1. Thermal Specifications 9.4.3.2. Case Temperature. 9.4.3.3. Measurements Thermal Specifications 9.4.3.4. Case Temperature Measurements. CMOS Interface Pixel Data Mapping LVDS Interface Pixel Data Serial Mapping.
Pinout Package Information 8.1. 8.2.
External Timing Specifications 9.1. 9.2.
9.3. 9.4.
Appendix 10.1. 10.2.
Datasheet
82807AA
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Simplified Block Diagram 1.8V Interface 1.5V Interface Clock Data Control Diagram Timing Diagram Stalling Timing Diagram LVDS Signaling LVDS Clock Data Diagram Example Format Consecutive Register Accessing.34 With respect H_TRP.53 With Respect V_TRP, H_TRP, V_DE With Respect V_TRP, H_TRP, Bi-Linear Interpolation Diagram Panel Sequencing Diagram Power Plane Diagram 82807AA Ball (Top View-Left Side) 82807AA Ball (Top View-Right Side) Physical Dimensions Diagram View Side View.66 Physical Diagrams Dimensions Bottom View.67 3.3V Clocking Interface 3.3V Clock Duty Cycle.77 CMOS Panel Timing.77 Source Synchronous Digital Video Timings Channel-to-Channel Skew LVDS Output Pulse Position Measurements Technique Measuring TCASE With Angle Attachment Technique Measuring TCASE With Angle Attachment
Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Single Data Format Single pixel Data Format Single Port System Display Configurations Alphabetical Assignment.64 82807AA Signal Groups Characteristics LVDS Characteristics.72 Clock Timing.72 Port Input Timing: Panel Mode (20-112 MHz).73 Port Input Timing: Mode DVOr Port: Timings Data Setup Hold Times from DVO.74 LVDS Interface Timing Parameters CMOS interface Output Timing.76 Power Characteristics Thermal Design Power Characteristics.80 Thermal Characteristics CMOS Flat Panel LVDS Conventional Data Mapping 1x18 Interface LVDS Conventional Data Mapping 2x18 Interface
Datasheet
82807AA
Table Table Table
LVDS Conventional Data Mapping 1x24 Interface. LVDS Conventional Data Mapping 2x24 Interface. LVDS Non-Conventional Conventional Data Mapping
Datasheet
82807AA
Revision History
Rev. -001 Initial Release Description Date October 2000
Datasheet
82807AA
Introduction
This document provides design specifications 82807AA VCH. describes interfaces, registers, functionality chip. This document also includes timing thermal specifications 82807AA VCH. companion chip 82815EM, 82807AA used order interface internal used notebook
Datasheet
82807AA
Datasheet
82807AA
Product Features
Display
Supports panel sizes from SVGA (800x600) SXGA+ (1400x1050) dual channel LVDS interface with Non-Conventional Conventional formats 1x18 1x24 panels with single LVDS channel 2x18 2x24 panels with dual LVDS channels bit, 3.3v CMOS interface with formats 1x18 1x24 (Single Pixel shift clock) 2x18 (Two Pixel shift clock) Up-scaling panel fitting with selectable algorithms Bi-Linear interpolation Multiple segmented high order curve approximation interpolation LVDS transmitter meets TIA/EIA LVDS standard Spread spectrum clocking Panel protection during mode switching Panel power sequencing Supports bypass 82807AA replication port enable:
monitor displaying with external transmitter displaying with external encoder Intel® Digital Video Output (DVO) port specification compliant ACPI specification compliant pBGA package
Datasheet
82807AA
Figure Simplified Block Diagram
System Memory Interface GMBus
Moon docking CardBus
GMCH
Encoder and/or
Monitor
DVOr LVDS CMOS ICH2-m
(Phy) Audio Modem Blue Tooth
Link
815EM/VCH Platform
Swap
Smart Battery
NOTE:
above diagram depicts 82807AA used 815EM platform (single port), other platforms this diagram might apply.
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82807AA
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82807AA
Overview 82807AA receives display images pixel format from 82815EM through port. display image then converted selected panel interface format. formatted data then accessed from LVDS interface CMOS interface. needed, 82807AA also capable passing display image from port through 82807AA external encoder displaying, external transmitter Display support. registers 82807AA programmed through 82815EM GMBus, where 82807AA viewed child device graphics controller 82815EM.
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82807AA
Description
This section provides detailed description 82807AA signals. signals arranged functional groups according their associated interfaces.
3.1.
Notation
symbol signal name indicates that active, asserted state occurs when signal voltage level. When present after signal name, signal asserted high voltage level. following notations describe signal type: I/OD Input Output Bi-directional Input/Output Open Drain output pin. This requires pull-up VCC. Input Open Drain Output pin. This requires pull-up VCC.
CMOS buffers used signals, except LVDS outputs. Signal swing voltage also specified.
3.2.
Interface Signals
Signal Name DVOSTALL/ DVOCLKOUT Type Voltage 1.8v Description display mode, panel fitting enabled, this stalls 82815EM display pipe line-by-line base. panel fitting disabled, this driven low. bypassing mode, this sends clock received from external encoder 82815EM. maximum frequency depending NTSC modes, over scan compensation values encoder. worst case duty cycle requirement input 82815EM. 82807AA driven 1.5-V port this (drives 1.8v signaling) will require voltage *level shifter/or voltage divider comply with 1.5v STALL input. *See appropriate platform guideline more information. DVOHSYNC DVOVSYNC DVOBLANK# DVOCLKIN[1:0] DVODATA[11:0] 1.8v 1.5v 1.8v 1.5v 1.8v 1.5v 1.8v 1.5v 1.8v 1.5v horizontal sync input. vertical sync input. blank input. differential clock inputs. Maximum frequency MHz. data bus.
Datasheet
82807AA
3.3.
DVOr Interface Signals
Signal Name DVOrCLKIN Type Voltage Description bypassing mode, device DVOr encoder, master mode, 82807AA receives clock from external encoder. DVOrCLKIN maximum frequency MHz. worst case duty cycle 40%. display mode, this input isolated. DVOrHSYNC bypassing mode, 82807AA passes DVOHSYNC from 82815EM external device DVOr. display mode, this output driven low. DVOrVSYNC bypassing mode, 82807AA passes DVOVSYNC from 82815EM external device DVOr. display mode, this output driven low. DVOrBLANK# bypassing mode, 82807AA passes DVOBLANK# from 82815EM external device DVOr. display mode, this output driven low. DVOrCLKOUT [1:0] DVOrDATA [11:0] DVOrRCOM bypassing mode, 82807AA passes CLKOUT[1:0] from 82815EM external device DVOr. display mode, these outputs driven low. bypassing mode, 82807AA passes DVODATA[11:0] from 82815EM external device DVOr. display mode, these outputs driven low. DVOr impedance compensation. Please specific platform design guide resistor values routing guidelines.
3.4.
CMOS Interface Signals
Signal Name P[35:0] SHFCLK Type Voltage Description pixel data output. Pixel mapping different types panels described tables Pixel Mapping section. shift clock. First line mark (equivalent VSYNC). Latch pulse (equivalent HSYNC) display enable BLANK#.
Datasheet
82807AA
3.5.
LVDS Interface Signals
Signal Name CLKAp CLKAm YA0p YA0m YA1p YA1m YA2p YA2m YA3p YA3m CLKBp CLKBm YB0p YB0m YB1p YB1m YB2p YB2m YB3p YB3m VREF_HI VREF_LO Type Voltage 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 1.372-1.028 Description Channel differential clock pair output (true). 245-800 MHz. Channel differential clock pair output (compliment). 245-800 MHz. Channel differential data pair output (true). 245-800 MHz. Channel differential data pair output (compliment). 245-800 MHz. Channel differential data pair output (true). 245-800 MHz. Channel differential data pair output (compliment). 245-800 MHz. Channel differential data pair output (true). 245-800 MHz. Channel differential data pair output (compliment). 245-800 MHz. Channel differential data pair output (true). 245-800 MHz. Channel differential data pair output (compliment). 245-800 MHz. Channel differential clock pair output (true). 245-800 MHz. Channel differential clock pair output (compliment). 245-800 MHz. Channel differential data pair output (true). 245-800 MHz. Channel differential data pair output (compliment). 245-800 MHz. Channel differential data pair output (true). 245-800 MHz. Channel differential data pair output (compliment). 245-800 MHz. Channel differential data pair output (true). 245-800 MHz. Channel differential data pair output (compliment). 245-800 MHz. Channel differential data pair output (true). 245-800 MHz. Channel differential data pair output (compliment). 245-800 MHz. Test Pin. Needs pulled high 1.8_VCC. Test Pin. Needs pulled VSS.
3.6.
GMBus Signals
Signal Name GMCK GMDA Type Voltage GMBus serial clock GMBus serial data Description
Datasheet
82807AA
3.7.
Signal Name Type Voltage Description Core clock reference input. external clock source from system clock generator with selectable clock frequencies: either with Spread Spectrum Clocking (SSC), without SSC.
3.8.
Signals
Signal Name GPIO [8:7] Type Voltage Description Software programmable input/output. GPIO[8:7] defaulted GPIs with their internal pull downs connected internal pull disconnected. GPIO[8:7] used 82807AA GMBus base address strapping: VR00[6] value GPIO[8] de-assertion edge PCIRST#. VR00[5] value GPIO[7] de-assertion edge PCIRST#. GPIO Software programmable input/output. GPIO[6] defaulted with internal pull down connected internal pull disconnected. GPIO[6] de-assertion edge PCIRST#, 82807AA normal operation mode. GPIO [5:2] GPIO [1:0] Software programmable input/output. GPIO[5:2] defaulted GPIs with their internal pull downs connected internal pull disconnected. Software programmable input/output. GPIO[1:0] defaulted GPOs.
3.9.
Mvssiscellaneous Signals
Signal Name ENAVDD ENEXBUF ENABKL TESTIN PCIRST# Type Voltage Description Power sequencing control driver electronics voltage VDD. LVDS other data interface enable Power sequencing control backlight. Test input. When asserted, 82807AA Test mode. Reset 82807AA VCH. internal registers logic reset PCIRST#. BIOS shall re-initialize 82807AA interface internal 82807AA registers every PCIRST#.
Datasheet
82807AA
3.10.
82807AA Core Power Ground
Signal Name PLL_VCC PLL_VSS LVDSpll_VCC LVDSpll-VSS LVDSDC_VCC LVDSDC_VSS VCC_3.3 VCC_1.8 LCD_VREF Type Voltage 3.3v 0.9v 0.75v Core power. Core ground LVDS power LVDS ground LVDS analog circuitry power LVDS analog circuitry ground buffer power Core power Core ground input buffer voltage reference. Please specific platform design guide resistor values routing guidelines. Description
Datasheet
82807AA
3.11.
States
Signal Name DVOSTALL/ DVOCLKOUT DVOHSYNC DVOVSYNC DVOBLANK# DVOREF Power Plane 1.5v 1.5v 1.5v Reset After Reset driven driven driven 0.9V S4/S5 output input input input input driven driven driven 0.9V FR100 driven driven driven 0.9V Driven( Driven( Driven( 0.9V
DVOrCLKIN DVOrHSYNC DVOrVSYNC DVOrBLANK# DVOrCLKOUT [1:0] DVOrDATA[11:0] DVOrRCOM
input output output output output output output
Gateoff driven driven driven driven driven driven
Gateoff driven driven driven driven driven driven
VR10 VR10 VR10 VR10 VR10 VR10 driven
driven driven driven driven driven Driven
P[35:0] SHFCLK ENAVDD ENEXBUF ENABKL
output output output output output output output output
VR10 VR10 VR10 VR10 VR10 VR10 VR10 VR10
GMBSCL GMBSDA GPIO[8:2] GPIO [1:0] TESTIN PCIRST# LVDSpllVCC LVDSdcVCC PLLVCC VCC_1.8
Input Input
Driven Driven (low) driven
Driven Driven (low) high driven
Driven Driven I/OD I/OD high driven
Driven Driven I/OD I/OD high
Power Power
Power Power
Datasheet
82807AA
Signal Name VCC_3.3
Power Plane
Reset
After Reset
S4/S5
Datasheet
82807AA
4.1.
Interface Description
82807AA
transfers display streams from 82815EM 82807AA VCH.
4.1.1.
Connection
following diagram indicates connection between 82815EM 82807AA VCH.
Figure 1.8V Interface
DVOSTALL/DVICLKIN (TVCLKIN/INT#) DVOSTALL/DVICLKOUT
DVOCLKOUT[1:0] (LTVCLKOUT) DVODATA[11:0] (LTVDATA) DVOHSYNC (LTVHSYNC) DVOVSYNC (LTVVSYNC) DVOBLANK# (LTVBLANK)
DVOCLKIN[1:0] DVODATA[11:0] DVOHSYNC DVOVSYNC DVOBLANK# DVOVREF
GMBSDA GMBSCL
GMBSDA GMBSCL
GMCH
GMBus
Datasheet
82807AA
Figure 1.5V Interface
DVOSTALL/ DV0_FIELD *Level Shifter/ voltage divider DVOSTALL/DVICLKOUT
DVOCLKOUT[1:0] DVODATA[11:0] DVOHSYNC DVOVSYNC DVOBLANK#
DVOCLKIN[1:0] DVODATA[11:0] DVOHSYNC DVOVSYNC DVOBLANK# DVOVREF
GMBSDA GMBSCL
GMBSDA GMBSCL
GMCH
GMBus
*See appropriate platform guidelines more details
4.1.2.
Data Format
82807AA accepts DVO, 12-bit, double-pumped, data format where half pixel precedes high half pixel displays.
Table Single Data Format
Packet half pixel High half pixel Rising Edge Falling Edge Clock Edge DVODATA[11:0] Green[3:0], Blue[7:0] Red[7:0], Green[7:4]
Datasheet
82807AA
following table below maps pixel data DVODATA[11:0] bus. Table Single pixel Data Format
Name DVODATA[0] DVODATA[1] DVODATA[2] DVODATA[3] DVODATA[4] DVODATA[5] DVODATA[6] DVODATA[7] DVODATA[8] DVODATA[9] DVODATA[10] DVODATA[11] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] G[0] G[1] G[2] G[3] Rising edge CLKIN[0] G[4] G[5] G[6] G[7] R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] Rising edge CLKIN[1]
Other data formats supported 82815EM pass from DVOr without modification. They used 82807AA displays.
Datasheet
82807AA
4.1.3.
Timing Controls
DVOBLANK# de-assertion indicates valid pixel data display line. following diagram example display line with 1024 pixels.
Figure Clock Data Control Diagram
DVOCLKIN[0] DVOCLKIN[1]
Invalid
DVOBLANK#
DVODATA[11:0]
P1022
P1022
P1023
P1023
Invalid
DVOHSYNC signals beginning display line. number clocks between adjacent DVOHSYNC pulses indicates H_total display line. DVOVSYNC signals beginning display frame. number DVOHSYNC pulses between adjacent DVOVSYNC pulses indicates V_total display frame. number clocks each DVOBLANK# de-asserted period indicates H_active display line. number DVOBLANK# de-assertions between adjacent DVOVSYNC pulses indicates V_active display frame. following diagram example DVOBLANK#, DVOHSYNC, DVOVSYNC display frame 1024x768 resolution with V_total, including lines vertical back-porch blanking lines vertical front-porch blanking.
Datasheet
82807AA
Figure Timing Diagram
H_active H_blank (back porch) H_blank (front porch) H_total
DVOBLANK#
line line line line line line line line line line
line line line line line line
DVOHSYNC
DVOVSYNC
V_blank back porch
V_active V_total
V_blank front porch
Frame
Frame
Frame
4.1.4.
Differential Clocking
DVOCLK[1:0] differential clocks with source synchronous timings. 82807AA uses crossover point between DVOCLK[0] DVOCLK[1] timing reference latching incoming data.
4.1.5.
Stalling
DVOSTALL used 82807AA signal 82815EM stopping incoming display stream line line base. Stalling stream requirement order support 82807AA up-scaling panel fitting algorithm (see Section 5.1.4).
Datasheet
82807AA
Figure Stalling Timing Diagram
H-total DVOHSYNC H-active DVOBLANK#
Tstall setul
Tstall Hold
DVOSTALL
DVODATA
line
invalid
line
4.2.
DVOr Interface
DVOr interfaces discrete encoder, discrete transmitter, integrated encoder transmitter. DVOr protocol timings specified "Intel® Digital Video (DVO) Port" specification.
4.3.
LVDS Interface
There LVDS transmitter channels (channel channel 82807AA LVDS interface. Each channel contains clock pair data pairs voltage differential swing signals. following diagram shows pair LVDS their associated swing voltage.
Datasheet
82807AA
Figure LVDS Signaling
RL=100
1.425V 1.372V 1.325V 1.20V 1.075V 1.028V 0.975V
450mV 344mV 250mV 0.0mV 250mV 344mV 450mV
NOTE:
That represent differential voltage between pair signals.
VR12[1] enables disables LVDS interface. When LVDS interface disabled, output LVDS pairs. When LVDS interface enabled, CMOS interface must disabled. following timing diagram shows relative relation between LVDS signals internal SHFCLK pixel data. Figure LVDS Clock Data Diagram
LVDS Clock Pair
LVDS Data Pair
data
data
data
data
data
data
data
data
data
4.3.1.
Clock Pair
SHFCLK frequency limited range from MHz. serial pattern "1100011" represents cycle SHFCLK.
4.3.2.
Data Pair
data pair transfers pixel data timing control signals. serial data mapping specified tables section 10-1 LVDS Interface Pixel Mapping.
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82807AA
5.1.
5.1.1.
82807AA Basic Operation
82807AA Display Modes
Normal Mode
When display size (H_active V_active) equal installed panel size, 82807AA normal operation mode. 82815EM enabled simultaneously with 82807AA normal mode. Panning centering 82815EM used enable flexibility various user display resolutions (size display image stored frame buffer), which often different from installed panel size.
5.1.2.
82815EM Centering
With centering, display timings port (and enabled), including clock (dot clock CRT) frequency, according VESA standard resolution installed panel size, instead user display resolution. (and enabled) refresh rate according installed panel specification (mostly Vsync=60 Hz). correct timing setting responsibility display driver video BIOS. Centering intended applying modes necessity Window booting. case legacy application changes registers without involvement display driver, stabilized display size timings must remain unchanged. unstable period during mode switching comprehended 82807AA panel protection function.
5.1.3.
82815EM Panning
When user display resolution larger than installed panel size, panning 82815EM used equalize display size installed panel size fetching portion display image from frame buffer with size equal installed panel size. simultaneous display enabled, display image panned both LCD. With panning, display timings (and enabled), including clock (dot clock CRT) frequency, according VESA standard resolution installed panel size, instead user display resolution. (and enabled) refresh rate according installed panel specification (mostly Hz). correct timing setting responsibility display driver. Panning intended applying modes installed panel size likely smaller than that size.
Datasheet
82807AA
5.1.4.
Panel-fitting Mode
When display size smaller than installed panel size, panel-fitting function enabled, 82807AA panel fitting mode. displaying 82815EM must disabled when panel fitting enabled. Interpolation used scaling with selectable algorithms either bi-linear multiple segmented high order curve approximation. Horizontal vertical scaling ratios calculated based installed panel size display size. ratios used interpolation weight generation, well line stalling generation. line based stalling used panel-fitting mode throttle incoming stream. DVOSTALL signal multiplexed with DVOCLKOUT 82807AA interface.
5.1.5.
Bypass Mode
point-to-point bus. there only 82815EM, occupied 82807AA displaying mobile platform. order able support displaying, 82807AA DVOr replicates 82815EM provide path from 82815EM discrete encoder, discrete transmitter, integrated encoder transmitter. integrated encoder transmitter expected operate simultaneously, enabled time. DVOr enabled when 82807AA bypassing enabled. 82807AA display must disabled prior enabling bypassing. 82807AA used generate clock. clock used DVOr output place clock edge middle data. 82807AA also capable passing clock from external encoder 82815EM.
Table Single Port System Display Configurations
82807AA LVDS CMOS Panel Normal Mode Normal Mode Panel Fitting 82807AA Bypass (DVOr)
Normal Mode Normal Mode Normal Mode
Configurations Normal Mode Normal Mode
NOTES: Normal Mode includes GMCH Centering Panning. Multiple ports, System Display Configurations different, platform guidelines more details.
Datasheet
82807AA
5.2.
GMBus Interface
GMBus used 82807AA register space accessing. 82807AA GMBus interface supports Kbit/S mode. 82815EM only master this bus. 82807AA operates slaved mode only.
5.2.1.
Base Address
7-bit GMBus base address field 82807AA revision, GMBus base address register (VR00) determines base address 82807AA GMBus. 82807AA GMBus controller will only respond GMBus transfer which base address matches value GMBus base address field VR00. user ability strap 82807AA GPIO[8:7] pins order select four possible GMBus base addresses (see VR00 register more description).
5.2.2.
Index Address
8-bit index address defines locations 82807AA register space. Each location contains 16-bit data. Below some examples index address corresponding register symbols:
addressing register VR00 addressing register VR01 addressing register VR02 addressing register VR1A addressing register VRFF Note: Each VRxx register bits bytes data.
Datasheet
82807AA
5.2.3.
Transfer Format
register Write:
Base address [6:0] index address [7:0] Data[7:0] VRindex Data[15:8] VRindex Data[7:0] VRindex+1 Data[15:8] VRindex+1
Figure Example Format Consecutive Register Accessing
register Read:
Base address [6:0] index address [7:0] Data[7:0] VRindex Data[15:8] VRindex
Data[7:0] VRindex+n-1
Data[15:8] VRindex+n-1
Data[7:0] VRindex+1
Data[15:8] VRindex+1
Data[7:0] VRindex+n-1
Data[15:8] VRindex+n-1
START
Read
Write
ACKnowledge
STOP
ACKnowledge
Datasheet
82807AA
6.1.
6.1.1.
6.1.1.1.
Register Description
Register Description
Header
VR00 82807AA Revision GMbus Base Address
Address offset: Default: Access:
15:12 11:8
0002h Read only
Description 82807AA identification 82807AA 82807AA revision number first revision 82807AA Reserved 82807AA GMBus base address Possible base addresses 62h, 42h, depending GPIO[8:7] strapping. VR00[6] strapping value GPIO[8] VR00[5] strapping value GPIO[7] VR00[4:0] 00010b
Datasheet
82807AA
6.1.1.2.
VR01 82807AA Functionality Enable
Address offset: Default: Access:
15:5 Reserved Reserved Panel Fitting enabled. This enables disables (bypassing) 82807AA panel fitting function when display enabled. disabled enabled display enabled. This enables disables 82807AA display function. disabled enabled This only VR01[1] there only either display bypassing. bypassing enable. This enables disables 82807AA DVOr port. disabled enabled When DVOr enabled, repeats signaling DVO. When disabled, DVOr outputs driven low, DVOr inputs ignored. This only VR01[2] there only either display bypassing. enable. This controls functions clock domain gating clock 82807AA clock domain. disabled enabled
0000h Read/Write
Description
Datasheet
82807AA
6.1.2.
6.1.2.1.
Interfaces
VR10 Interface Format
Address offset: Default: Access:
15:5 Reserved interface select. LVDS disabled, CMOS enabled. LVDS enabled, CMOS disabled. Note: there desire split this into bits driving panels same time. Panel interface data width. 00.1x18 LVDS 1x24 LVDS CMOS (CMOS 1x18 same MSB's 1x24 mapping) 2x18 LVDS CMOS 2x24 LVDS Reserved Reserved Reserved
0000h Read/Write
Description
Panel type.
Datasheet
82807AA
6.1.2.2.
VR11 CMOS Output Control
Address offset: Default: Access:
Reserved Shift clock mask. Allows shift clock output toggle outside display enable interval. Force shift clock output outside display enable interval. Force during vertical blank. active during vertical blank time. inactive during vertical blank time. Force during vertical blank. inactive during vertical blank time. active during vertical blank time. 11:10 Reserved panel interface group: P[35:0] signals group) inversion invert sense signal panel interface group: SHFCLK signal inversion invert sense signal panel interface group: signal inversion invert sense signal panel interface group: signal inversion invert sense signal panel interface group: signal inversion invert sense signal Reserved timing controls clock (FLM, SHFCLK) output buffer strength. lower drive higher drive data (P[35:0]) output buffer strength. lower drive higher drive NOTE: Regardless value VR82, P[35:0], SHFCLK, FLM, will driven when ENEXBUF asserted.
0000h Read/Write
Description
Datasheet
82807AA
6.1.2.3.
VR12 LVDS Output Control
Address offset: Default: Access:
15:8 Reserved LVDS frequency range (Pllrange[1:0]) Reserved Data serialization mode Conventional mode Non-Conventional mode Second clock pair output control. (En2ndclk) Disabled Enabled Software reset LVDS block. normal operation reset LVDS block LVDS power down control. (drvenslct) LVDS pairs powered Powered down. pairs will powered down.
0080h Read/Write
Description
6.1.3.
three registers Read/Write with double buffered registers. There copies each three registers. copy accessing, other copy operation. contents three registers only transferred from copy accessing copy operation when VR1A written. required that these registers programmed order VE18, VR19, VR1A. purpose double buffering panel protection.
Datasheet
82807AA
6.1.3.1.
VR18 clock select
Address offset: Default: Access:
15:0 Reserved
0010h Read/Write with double buffered
Description
6.1.3.2.
VR19 clock divisor
Address offset: Default: Access:
15:0 Reserved
Read/Write with double buffered
Description
6.1.3.3.
VR1A clock divisor
Address offset: Default: Access:
15:0 Reserved
Read/Write with double buffered
Description
Datasheet
82807AA
6.1.4.
6.1.4.1.
Flat Panel Timing
VR22 Horizontal Start Delay
Address offset: Default: Access:
15:12 11:0 Reserved Horizontal Timing Reference Point start delay clocks.
0000h Read/Write
Description
6.1.4.2.
VR23 Horizontal Delay
Address offset: Default: Access:
15:0 11:0 Reserved Horizontal Timing Reference Point delay clocks.
0000h Read/Write
Description
6.1.4.3.
VR24 Horizontal Start Delay
Address offset: Default: Access:
15:12 11:0 Reserved Horizontal Timing Reference Point Start delay clocks.
0000h Read/Write
Description
6.1.4.4.
VR25 Horizontal Delay
Address offset: Default: Access:
15:12 11:0 Reserved Horizontal Timing Reference Point delay clocks.
0000h Read/Write
Description
Datasheet
82807AA
6.1.4.5.
VR26 Vertical Start Delay
Address offset: Default: Access:
15:12 11:0 Reserved Vertical Timing Reference Point Start delay display lines. This register specifies number lines between V_TRP Start vertical direction. horizontal direction, always asserted same time pulse assertion. other words, defined units display lines, assertion defines starting point current display line.
0000h Read/Write
Description
6.1.4.6.
VR27 Vertical Delay
Address offset: Default: Access:
15:12 11:0 Reserved Vertical Timing Reference Point delay display lines. This register specifies number lines between V_TRP vertical direction. horizontal direction, always de-asserted same time pulse assertion. other words, defined units display lines, assertion also defines ending point previous display line.
0000h Read/Write
Description
Datasheet
82807AA
6.1.5.
6.1.5.1.
Power Sequencing Panel Protection
VR30 Panel Power Shut Down Status
Address offset: Default: Access:
15:15
0000h Read only [15], Read/write rest
Description safe program panel timing registers 82807AA VCH. also indicates panel powered down sequencing completed setting VR01[2] "0". unsafe program panel timing registers 82807AA VCH. Note: This read only. This when VR01[2] "1". Software responsible enable display writing VR01[2] after panel timing registers programmed. This cleared (set "0") only when VR01[2] been panel power down sequencing completed. also responsibility check this before panel timing registers programming.
14:0
Reserved
6.1.5.2.
VR31 Tpon Panel Power-on Sequencing Delay
Address offset: Default: Access: 0200h Read/Write
This register controls panel sequencing delays. clock source power sequencing logic count down MHz.
15:12 11:0 Reserved Power delay: Tpon. Programmable value panel power sequencing delay during power This value programmed ~256 milliseconds increments millisecond (0.98304 actual). value undefined/implementation specific should avoided programmers. Description
Datasheet
82807AA
6.1.5.3.
VR32 Tpoff Panel Power-off Sequencing Delay
Address offset: Default: Access: 0200h Read/Write
This register controls panel sequencing delays. clock source power sequencing logic count down MHz.
15:12 11:0 Description Reserved Power down delay: Tpoff. Programmable value panel power sequencing delay during power down. This value programmed ~256 milliseconds increments millisecond (0.98304 actual). value undefined/implementation specific should avoided programmers.
6.1.5.4.
VR33 Tstay Panel Power-off Stay Down Delay
Address offset: Default: Access: 0000h Read/Write
This register controls long panel remains power condition. panels limit fast panel sequence VRom down again. Typically this .5-1.5 seconds. This register forces panel stay off. clock source power sequencing logic count down MHz.
15:5 Reserved Power down delay: Tstay. Programmable value time panel must remain powered down state. This value programmed seconds increments seconds. value delay. Description
Datasheet
82807AA
6.1.5.5.
VR34 Maximum Pulse Interval
Address offset: Default: Access:
14:0 Reserved. Maximum pulse interval display lines. generated from FPtg when maximum pulse interval reached, 82807AA panel protection state machine generates automatically. This register normally programmed value, which less than close maximum allowance installed panel
0001h Read/Write
Description
6.1.5.6.
VR35 Maximum Pulse Interval
Default: Access:
14:0 Reserved. Maximum pulse interval clocks. not, generated from FPtg when maximum pulse interval reached, 82807AA panel protection state machine generates automatically. This register normally programmed value, which less than close maximum allowance installed panel.
Read/Write
Description
Datasheet
82807AA
6.1.6.
6.1.6.1.
Panel Fitting
VR40 Panel Fitting Controls
Address offset: Default: Access:
15:14 Reserved Stall output enable disable enable Vertical interpolation enable disable enable Enhanced panel fitting mode enable disable enable Horizontal interpolation enable disable enable Ratio enable disable enable Panel fitting clock gating enable clock gating disabled (panel fitting enabled) clock gating enabled (panel fitting disabled) Reserved
0000h Read/Write
Description
Datasheet
82807AA
6.1.7.
6.1.7.1.
GPIO
VR80 GPIO0 Control
Address offset: Default: Access: 80h, 0000h Read/Write
6.1.7.2.
VR81 GPIO1 Control
Address offset: Default: Access:
15:6 Reserved Output inversion output inverted output inverted Pull control pull 100-Kohm pull 3.3V Pull down control pull down 100-Kohm pull down ground GPIO drive definition CMOS totem pole outputs open drain GPIO direction controls output input GPIO data =high
81h, 0000h Read/Write
VR80,VR81 Description
Datasheet
82807AA
6.1.7.3.
VR82 GPIO Control
Address offset: Default: Access: 0002h Read/Write
6.1.7.4.
VR83 GPIO Control
Address offset: Default: Access: 0002h Read/Write
6.1.7.5.
VR84 GPIO Control
Address offset: Default: Access: 0002h Read/Write
Datasheet
82807AA
6.1.7.6.
VR85 GPIO Control
Address offset: Default: Access: 0002h Read/Write
GPIO[5:2] default with internal pull down connected power reset. Suggested strapping usage GPIO[5:2] would Panel I.D., with pins used strapping allow possible panel types.
15:6 Reserved Output inversion output inverted output inverted Pull control pull 100-Kohm pull 3.3V Pull down control pull down 100-Kohm pull down ground GPIO drive definition CMOS totem pole outputs open drain GPIO direction controls output input GPIO data =high VR82,VR83,VR84, VR85 Description
Datasheet
82807AA
6.1.7.7.
VR86 GPIO Control
Address offset: Default: Access: 0002h Read/Write
GPIO[6] default with internal pull down connected power reset.
Note:
82807AA normal operation mode, GPIO6 must read low(0) de-assertion edge PCIRST#.
15:6 Reserved Output inversion output inverted output inverted Pull control pull 100-Kohm pull 3.3V Pull down control pull down 100-Kohm pull down ground GPIO drive definition CMOS totem pole outputs open drain GPIO direction controls output input GPIO data =high VR86 Description
Datasheet
82807AA
6.1.7.8.
VR87 GPIO Control
Address offset: Default: Access: 0002h Read/Write
6.1.7.9.
VR88 GPIO Control
Address offset: Default: Access: 0002h Read/Write
GPIO[8;7] default with internal pull down connected power reset. default GPIO[8:7] used 82807AA GMBus base address (VR00[6:5]) strapping follows: GPIO7=0 de-assertion edge PCIRST#, 82807AA GMBus base address (VR00[5]) GPIO7=1 de-assertion edge PCIRST#, 82807AA GMBus base address (VR00[5]) GPIO8=0 de-assertion edge PCIRST#, 82807AA GMBus base address (VR00[6]) GPIO8=1 de-assertion edge PCIRST#, 82807AA GMBus base address (VR00[6])
15:6 Reserved Output inversion output inverted output inverted Pull control pull 100-Kohm pull 3.3V Pull down control pull down 100-Kohm pull down ground GPIO drive definition CMOS totem pole outputs open drain GPIO direction controls output input GPIO data =high VR87,VR88 Description
Datasheet
82807AA
6.1.8.
6.1.8.1.
Graphics BIOS Scratch Space
VR8E Video BIOS Scratch Register
Address offset: Default: Access:
15:0 Graphics BIOS scratch bits
0000h Read/Write
Description
6.1.8.2.
VR8F Video BIOS Scratch Register
Address offset: Default: Access:
15:0 Graphics BIOS scratch bits
0000h Read/Write
Description
Datasheet
82807AA
7.1.
7.1.1.
Functional Description
Timing Control
Timing Reference Point Generation
timing tracks coordinates display frames, generates horizontal vertical Timing Reference Point (TRP) according coordinates. timing also generates vertical display enable (V_DE) monitoring DVOBLANK#. horizontal vertical TRP, well V_DE, then synchronized clock domain timing.
7.1.1.1.
Flat Panel Timing Diagram
Figure With respect H_TRP
H_TRP
VR22 VR23 VR24 VR25
Datasheet
82807AA
Figure With Respect V_TRP, H_TRP, V_DE
V_TRP
H_TRP
V_DE
Figure With Respect V_TRP, H_TRP,
V_total VR27 VR26 VR22 V_TRP
H_TRP
Datasheet
82807AA
7.2.
7.2.1.
Scaling
left aligned scaling supported.
Scaling Algorithm
Selectable Bi-linear interpolation multiple-segmented high order curve interpolation scaling algorithms used scaling function.
7.2.1.1.
Bi-Linear Interpolation
Bi-linear interpolation calculate distance-weighted average four neighboring pixels linearly:
Po(X,Y) (1-dy) [(1-dx) Pi(x,y) Pi(x+1,y)] [(1-dx) Pi(x,y+1) Pi(x+1,y+1)]
Where: Po(X,Y) calculated pixel output value (X,Y) coordinates Pi(x,y) input pixel value (x,y) coordinates (X,Y) output coordinates (x,y) input coordinates normalized distance from output coordinates nearest left input pixel horizontal direction normalized distance from output coordinates nearest upper input pixel vertical direction Figure Bi-Linear Interpolation Diagram
Pi(x,y)
1-dx Pi(x+1,y)
Po(X,Y)
1-dy
Pi(x,y+1)
Pi(x+1,y+1)
Datasheet
82807AA
7.2.1.2.
Multiple Segmented High Order Curve Interpolation
Scaling with higher order curve algorithm provides better visual quality deep contrast contents, such text, graphics, video image with sharp edges, etc. This because high frequency feature display image requires higher order algorithms reconstruct. However, higher order algorithm requires complicated expensive hardware realize.
7.3.
LVDS Transmitter
LVDS (Low Voltage Differential Swing) flat panels takes parallel converts high bandwidth serial data streams. Depending configuration mode, take bits data plus bits control output them three differential outputs; take bits data plus bits control output four differential outputs. LVDS supports transmit clock frequency ranges from MHz, which provides throughput Mbps Mbps. phase locked transmit clock transmitted parallel with data over additional LVDS channel. LVDS flat panel displays compatible with ANSI/TIA/EIA -644-1995 specification.
7.3.1.
block synthesizes speed clock required high speed serial outputs data rate transmitters. must also output synchronized clock input clock rate transmission over serial clock line. frequency high speed clock always it's input. Since input clock operate over range MHz, operation require range switch least more than bits ranges). There specific frequencies operation that will likely LVDS applications. Those frequencies MHz, MHz, MHz. More research needed determine correctness this information. desired that common frequencies operation fall within center ranges best jitter reduction.
7.3.1.1.
Serializer With Control
serializer block converts bits parallel data from graphic controller output into serial data streams output LVDS drivers. total four 7-bit wide shift registers used. data shifted using clock generated PLL. registers load parallel data from load ports using clock (also generated PLL) that synchronizes with clock. state machine synchronized serial clock generates load signal. uses WAIT state while looks rising/falling edges transmit clock transit WAIT state. time interval LOAD State determined desired setup/hold time requirement. Upon exiting LOAD State, load signal asserted clock cycle SHIFT State starts. state machine reenters WAIT state after cycles looks again edge transmit clock.
Datasheet
82807AA
7.4.
7.4.1.
Panel Protection Power Sequencing
Panel Protection
When panel powered, panel timing signals (FLM toggle after specified maximum pulse intervals panel damaged. prevent this from happening 82807AA ability assert without H-sync V-sync. 82807AA VCH, signals generated from horizontal vertical TRPs, which generated from H-sync V-sync. When behaves abnormally syncs longer toggling, 82807AA panel protection state machine will automatically assert Maximum pulse interval register (VR34) Maximum pulse interval register (VR35) specify intervals that asserted panel protection function.
7.4.1.1.
Panel Power Sequencing
diagram below shows timing panel power down sequencing.
Figure Panel Sequencing Diagram
Tpon Tpoff Tpoff
PLL_valid ENAVDD ENEXBUF ENABKL Panel Signal (Data,CLK Control)
Panel Signaling
Where "Tpon" "Tpoff" controlled value programmed VR31 VR32. Tpon Tpoff must satisfy panel specifications.
7.5.
Bypassing
When 82807AA Functionality Enable register VR01[1] VR01[2] bypassing mode enabled.
Datasheet
82807AA
7.5.1.
DVOrRCOM
Please specific platform design guide resistor values routing guidelines each interface mode.
7.5.2.
DVOr Electrical Isolation
82807AA also provides electrical isolation from 82815EM external encoder external transmitter. When bypassing enabled, display must disabled. circuitry display powered down after panel power-down sequence. When bypassing disabled, outputs DVOr driven low, inputs DVOr isolated.
7.5.3.
Spread-Spectrum Clocking Support
82807AA capable locking onto spread-spectrum referencing clock from system clock generator with 0.6% down spreading, while reflecting spread spectrum output. Please note that output means both LVDS Panel signaling. section (OSC) description more information.
7.6.
7.6.1.
Power Supply
System Connection
82807AA multiple 3.3V 1.8V power pins. Externally, 3.3V pins connect single 3.3V supply point, 1.8V pins connect single 1.8v supply point. reason multiple dedicated power pins provide noise immunity. separate power pins used shutting parts chip. system, 3.3V 1.8V wells 82807AA connected power plane. variant this connection that separate 3.3V regulator lower noise.
Datasheet
82807AA
Figure Power Plane Diagram
battery/AC adapter Unregulated 12-18v (off only during mechanical off)
1.8v Regulater
3.3v Regulater
SLP_S3#
1.8v power plane 3.3v power plane
SLP_S3#
LVDS
CMOS Interface
Interface
Interface
GMCH
Core
Interface
DVOr Interface
power planes powered during ACPI power states S0-S2. S3-S5, power removed. dedicated voltage levels 82807AA connected power plane mobile platform, powered down during
Datasheet
82807AA
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Datasheet
82807AA
8.1.
Pinout Package Information
82807AA Pinout
82807AA information contained Figure Figure
Datasheet
82807AA
Figure 82807AA Ball (Top View-Left Side)
ENEXBUF VCC3.3 ENABKL YA0p YA0m ENAVDD SHFCLK YA1p YA1m VCC3.3 VCC3.3 VCC1.8 VCC3.3 VCC3.3 VCC3.3 VCC3.3 YA2p YA2m VCC1.8 VCC1.8 VCC1.8 CLKAp CLKAm VCC3.3 VCC3.3 VCC3.3 DATA11 DATA10 YA3p YA3m LVDSDC VREF_LO VCC1.8 DATA9 DATA8 DATA7
Datasheet
82807AA
Figure 82807AA Ball (Top View-Right Side)
YB0p YB0m LVDSDC VREF_HI VCC1.8 VCC1.8 DVOCLKIN0 DVOCLKIN1 DATA6 YB1p YB1m VCC3.3 VCC3.3 VCC1.8 DATA5 DVOr ZCOM DATA4 YB2p YB2m LVDSpll VCC1.8 PLL_VCC DATA3 DATA2 DATA1 YB3p YB3m LVDSpll VCC1.8 VCC3.3 VCC1.8 VCC1.8 VCC1.8 VCC1.8 PLL_VSS DATA0 DVOBLK# CLKBp CLKBm GPIO0 GMBSCL GPIO4 GPIO6 DVOr BLANK# DVOr DATA2 DVOr CLKOUT1 DVOr DATA6 DVOr DATA9 VSYNC VCC3.3 GPIO2 GPIO3 GMBSDA GPIO5 GPIO8 TESTIN GPIO1 PCIRST GPIO7
DVOr CLKIN
DVOr HSYNC DVOr VSYNC DVOr DATA1 DVOr CLKOUT0 DVOr DATA5 DVOr DATA8 DVOr DATA0 DVOr DATA3 DVOr DATA4 DVOr DATA7
DVOrDATA11 DVOrDATA10 VCC1.8 VREF
HSYNC CLKOUT
Datasheet
82807AA
Table Alphabetical Assignment
Signal Name
CLKAm CLKAp CLKBm CLKBp LVDSDC_VCC LVDSDC_VSS DVOBLK DVOCLKIN0 DVOCLKIN1 DVOCLKOUT DVODATA0 DVODATA1 DVODATA10 DVODATA11 DVODATA2 DVODATA3 DVODATA4 DVODATA5 DVODATA6 DVODATA7 DVODATA8 DVODATA9 DVOHSYNC DVOrBLANK# DVOrCLKIN DVOrCLKOUT0 DVOrCLKOUT1 DVOrDATA0 DVOrDATA1 DVOrDATA10 DVOrDATA11 DVOrDATA2
Ball
Signal Name
DVOrDATA3 DVOrDATA4 DVOrDATA5 DVOrDATA6 DVOrDATA7 DVOrDATA8 DVOrDATA9 DVOrHSYNC DVOrVSYC DVOrZCOM VREF_LO VREF_HI DVOVSYNC ENABKL ENAVDD ENEXBUF GPIO0 GPIO1 GMBSDA GMBSCL GPIO5 GPIO4 LCDVREF GPIO2 GPIO6 GPIO3 LVDSpll_VCC LVDSpll_VSS
Ball
Signal Name
Ball
Datasheet
82807AA
Table Alphabetical Assignment (cont.)
Signal Name
PCIRST PLL_VCC PLL_VSS GPIO7 SHFCLK GPIO8 TESTIN VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3
Ball
Signal Name
VCC3.3 VCC3.3 VCC3.3 VCC3.3
Ball
Signal Name
YA0m YA0p YA1m YA1p YA2m YA2p YA3m YA3p YB0m YB0p YB1m YB1p YB2m YB2p YB3m YB3p
Ball
Datasheet
82807AA
8.2.
Physical Dimensions
Figure Physical Dimensions Diagram View Side View
Datasheet
82807AA
Figure Physical Diagrams Dimensions Bottom View
Datasheet
82807AA
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Datasheet
82807AA
External Timing Specifications
8.3.
Related Documents References
Intel® 815EM Design Guide other appropriate Design Guide) Document Reference Number: 298241 Intel® 815EM Chipset: 82815EM Graphics Memory Controller (GMCH2-M) Datasheet other appropriate Datasheet) -Document Reference Number: 290689
8.4.
Electrical Characteristics
Unused active 3.3V tolerant inputs should connected 3.3V. Unused active high inputs should connected ground (VSS).
8.4.1.
Absolute Maximum Ratings
Storage Temperature -55oC +150oC 3.3V Supply Voltage with Respect (VCC) -0.3V 3.8V 1.8V Supply Voltage with Respect -0.3V 2.1V
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operating beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect reliability.
Datasheet
82807AA
8.4.2.
Signal Groups
ease discussion characteristics, signals 82807AA have been combined into groups with similar characteristics. These signal groups referenced throughout this document.
Table 82807AA Signal Groups
Signal Group Signal Type LVDS Output Signals CLKAp, CLKAm, YA0p, YA0m, YA1p, YA1m, YA2p, YA2m, YA3p, YA3m, CLKBp, CLKBm, YB0p, YB0m, YB1p, YB1m, YB2p, YB2m, YB3p, YB3m
CMOS (3.3V) Input CMOS (3.3V) Panel Output
OSC, TESTIN, PCIRST# P[35:0], SHFCLK, FLM, ENAVDD, ENEXBUF, ENABKL
Digital Video Output Port Reference Voltage CMOS (1.8V) CMOS (1.8V) Input CMOS (1.8V) Output
LCD_VREF DVOrRCOMP DVOBLANK#, DVODATA[11:0], DVOVSYNC, DVOHSYNC, DVOCLKIN[1:0], DVOrCLKIN DVOrCLKOUT[1:0], DVOrBLANK#, DVOrDATA[11:0], DVOrVSYNC, DVOrHSYNC, DVOSTALL/DVOCLKOUT
CMOS (3.3V) CMOS I/OD
GMBSCL, GMBSDA GPIO[8:0]
Datasheet
82807AA
8.4.3.
Characteristics
Functional Operating Range (Vcc_1.8 LVDSspll_Vcc 1.80V ±5%, Vcc_3.3 3.3V ±5%; TCASE 0°95oC).
Table Characteristics
Symbol Sig.Group Parameter Unit Notes 3.3V CMOS Signal Characteristics VIL_3.3 VIH_3.3 VOL_3.3 VOH_3.3 IOL_3.3 ILEAK_3.3 (b,h) (b,h) (c,h) (c,h) (c,h) (c,h) VIL_1.8 VIH_1.8 VOL_1.8 VOH_1.8 IOL_1.8 IOH_1.8 LCD_VREF ILEAK_1.8 VIL_I/OD VIH_I/OD VOL_I/OD VOH_I/OD IOL_I/OD ILEAK_I/OD CMOS Input Voltage CMOS Input High Voltage CMOS Output Voltage CMOS Output High Voltage CMOS Output Current Leakage Current CMOS Output High Current CMOS Input Voltage CMOS Input High Voltage CMOS Output Voltage CMOS Output High Voltage CMOS Output Current CMOS Output High Current HUBREF voltage reference Leakage Current CMOS I/OD Signal Characteristics CMOS I/OD Input Voltage CMOS I/OD Input High Voltage CMOS I/OD Output Voltage CMOS I/OD Output High Voltage CMOS I/OD Output Current Leakage Current ±100 Vsus_3.3+ -1.0 0.48(Vcc_1.8) 0.52(Vcc_1.8) 0.9(Vcc_1.8) -2.0 -0.3 0.6(Vcc_1.8) 0.4(Vcc_1.8) (Vcc_1.8) 0.1(Vcc_1.8) 1.8V CMOS Characteristics -0.3 Vsus_3.3+0.3
Datasheet
82807AA
Functional Operating Range (Vcc_1.8 LVDSspll_Vcc 1.80V ±5%, Vcc_3.3 3.3V ±5%; TCASE =0°95oC). Table LVDS Characteristics
Symbol Sig.Group Parameter Unit Notes LVDS Driver Characteristics VCM_LVDS VCM_LVDS VOD_LVDS VOD_LVDS C_LVDS NOTE: RLOAD=100. LVDS Common mode Voltage LVDS Delta VCM_LVDS LVDS Differential Output Voltage LVDS Delta VOD_LVDS LVDS input capacitance 1.125 1.25 1.375
8.4.4.
8.4.4.1.
Characteristics
Phase Lock Loop Clock Input Timing
Functional Operating Range (Vcc_1.8 1.80V ±5%, Vcc_3.3 3.3V ±5%; TCASE =0°- 95oC).
Table Clock Timing
Symbol Parameter (Core clock input) Period 20.83 Jitter High Time Time Slew Rate Duty Cycle 15.15 Unit Notes
8.4.4.2.
Digital Video Out(DVO) Port Interface Timing
timings nanoseconds (ns), unless otherwise specified. addition, clock-to-output values specified into 0-pF load, unless otherwise specified. Functional Operating Range (Vcc_1.8 1.80V ±5%, Vcc_3.3 3.3V ±5%; TCASE =0°- 95oC).
Datasheet
82807AA
Table Port Input Timing: Panel Mode (20-112 MHz)
Symbol Parameter DVODATA[11:0], DVOBLANK#, DVOVSYNC, DVOHSYNC valid before DVOCLKIN[1:0], tTDVb DVODATA[11:0], DVOBLANK#, DVOVSYNC, DVOHSYNC valid after DVOCLKIN[1:0], tTDVa Units Figure Notes
Functional Operating Range (Vcc_1.8 1.80V ±5%, Vcc_3.3 3.3V ±5%; TCASE =0°- 95oC). Table Port Input Timing: Mode
Symbol Parameter DVODATA[11:0], DVOBLANK#, DVOVSYNC, DVOHSYNC valid before DVOCLKIN[1:0], tTDVb DVODATA[11:0], DVOBLANK#, DVOVSYNC, DVOHSYNC valid after DVOCLKIN[1:0], tTDVa Units Figure Notes
Functional Operating Range (Vcc_1.8 1.80V ±5%, Vcc_3.3 3.3V ±5%; TCASE =0°- 95oC). Table DVOr Port: Timings
Symbol Parameter Units Figure Notes DVOrDATA[11:0], DVOrBLANK#, DVOrVSYNC, DVOrHSYNC valid Table before DVOrCLKOUT[1:0], tTDvb DVOrDATA[11:0], DVOrBLANK#, DVOrVSYNC, DVOrHSYNC valid Table after DVOrCLKOUT[1:0], tTDva Input Timing DVOrCLKIN DVOrCLKIN Period DVVOrCLKIN Jitter DVOrCLKIN High Time DVOrCLKIN Time DVOrCLKIN Rise Time DVOrCLKIN Fall Time 0.35 0.35 11.75 ±250
output valid delay measured into 60-ohm transmission line load frequency dependent.
Datasheet
82807AA
Table Data Setup Hold Times from
DVOrCLKOUT (MHz) tTDvb (min) (ns) 10.75 8.40 6.85 5.74 4.90 4.25 3.73 3.30 2.95 2.65 2.39 2.16 2.01 1.80 1.71 1.58 1.45 1.34 1.24 1.20 TTDva (min) (ns) 10.95 8.60 7.05 5.94 5.10 4.45 3.93 3.50 3.15 2.85 2.59 2.36 2.21 2.00 1.91 1.78 1.65 1.54 1.44 1.40
Datasheet
82807AA
8.4.5.
82807AA LVDS Switching Characteristics
Functional Operating Range (Vcc_1.8 1.80V ±5%, Vcc_3.3 3.3V ±5%; TCASE =0°- 95oC).
Table LVDS Interface Timing Parameters
Symbol NOTE: Frequency MHz. Parameter Channel Channel Skew Output Skew Delay time serial position Delay time serial position Delay time serial position Delay time serial position Delay time serial position Delay time serial position Power Down Delay Cycle Cycle Transmitter Jitter F=112 F=65 F=40 F=32.5 -200 Units Notes
1.076 1.276 1.476 2.351 2.551 2.751 3.626 3.826 4.026 4.902 5.102 5.302 6.178 6.378 6.578 7.453 7.653 7.853
Datasheet
82807AA
8.4.5.1.
CMOS Panel Interface Timing
timings nanoseconds (ns), unless otherwise specified. addition, clock-to-output values specified into load, unless otherwise specified. Functional Operating Range (VCC_1.8 1.8V ±5%, VCC_3.3 VSUS_3.3 3.3V ±5%; TCASE =0°- 95oC)
Table CMOS interface Output Timing
Symbol t10a t10b t10c Parameter Valid Delay from SFHCLK Rising Valid Delay from SFHCLK Rising P[35:0] Valid Delay from SFHCLK Rising SHFCLK Timings t10d t10e t10f SFHCLK Jitter SFHCLK Slew Rate SFHCLK Duty Cycle V/ns Units Figure Notes
8.5.
82807AA Timing Diagrams
Figure 3.3V Clocking Interface
Period High Time SCLK/DVOrCLKIN DCLKREF 2.0V 1.5V 0.8V 0.8V 2.0V 2.0V 1.5V 0.8V Time Fall Time Rise Time
Datasheet
82807AA
Figure 3.3V Clock Duty Cycle
Duty Cycle Duty Cycle
Clock (3.3V)
1.5V
1.5V
Figure CMOS Panel Timing
SHFCLK
Valid Delay (t10a-c)
P[35:0]
Datasheet
82807AA
Figure Source Synchronous Digital Video Timings
CLKOUT1 CLKOUT0 TDVb DVODATA[11:0] DVOBLANK DVOSYNC(H/V) TDVa
8.5.1.
82807AA LVDS Timing Diagrams
Figure Channel-to-Channel Skew
(A/B)
Y1(A/B)
(A/B)
Va-Vb=0
(A/B)
(A/B)
Datasheet
82807AA
Figure LVDS Output Pulse Position Measurements
CLK(A/B)
Tclk
Y(A/B)
Datasheet
82807AA
8.6.
8.6.1.
Power/Thermal Characteristics
Power Characteristics
Symbol Vcc_1.8 Vcc_3.3 Vcc_LVDS_DC_1.8 PLL_vcc LVDSpll_vcc Icc_1.8 Icc_3.3 Icc_LVDS_DC1.8 Icc_core_PLL Icc_LVDSpll Parameter 1.8V Core Supply Voltage 3.3V Buffer Supply Voltage 1.8V LVDS Supply Voltage Core Supply Voltage LVDS Supply Voltage 1.8V Core Supply Current 3.3V Buffer Supply Current 1.8V LVDS Supply Current Core Supply Current LVDS 1.8V supply Current 1.71 3.15 1.71 1.71 1.71 1.89 3.45 1.89 1.89 1.89 Unit Notes
Table Power Characteristics
NOTES: maximum values currents should used calculate maximum power consumption, since they occur same time.
Table Thermal Design Power Characteristics
Symbol TDPTyp Configuration LVDS mode Unit Notes
NOTES: TDPTyp estimated based configurations listed. TDPTyp recommended design power. This number generated from power estimation, tested silicon. Therefore, subjected change.
8.6.2.
Thermal Management Introduction
system environment, chipset temperature function both system component thermal characteristics. system level thermal constraints consist local ambient temperature component, airflow over component surrounding board well physical constraints above surrounding component. component's case temperature depends component power dissipation, size packaging materials (effective thermal conductivity), type interconnection substrate motherboard, presence thermal cooling solution, thermal conductivity, power density substrate, nearby components motherboard.
8.6.3.
Importance Thermal Management
objective thermal management ensure that temperatures components system maintained within functional limits. functional temperature limit range within which electrical circuits expected meet specified performance requirements. Operation outside functional limit degrade system performance, cause logic errors cause component and/or system damage. Temperatures exceeding maximum operating limits result irreversible changes operating characteristics component.
Datasheet
82807AA
8.6.3.1.
Thermal Specifications
ensure proper operation reliability Intel® 815EM chipset platform, thermal solution must maintain case temperature (TCASE) below specified value. Considering power dissipation levels typical system ambient environments 82807AA case temperature exceeds maximum case temperature listed Table 3-3, system component level thermal enhancements will required dissipate generated heat. general, systems should designed dissipate highest possible thermal power.
Table Thermal Characteristics
Symbol TCASE Parameter Case Temperature Unit Notes
NOTE: TCASE defined maximum case temperature without thermal enhancement package.
8.6.3.2.
Case Temperature
case temperature function local ambient temperature internal temperatures Intel® 815EM Chipset platform. local ambient temperature specified Intel® 815EM Chipset platform, only restriction that maximum case temperature (TCASE) exceeded. Note that increasing heat flow through case increases difference temperature between junction case, that reduces maximum allowable case temperature.
8.6.3.3.
Measurements Thermal Specifications
Proper measurements must made appropriately determine thermal properties system. Section 8.6.3.4 provides guidelines accurately measure case temperature Intel® 815EM Chipset platform.
8.6.3.4.
Case Temperature Measurements
ensure functionality reliability, Intel® 815EM Chipset platform specified proper operation when TCASE maintained below maximum case temperature listed Table surface temperature case geometric center mold measured. Special care required when measuring TCASE ensure accurate temperature measurement. Thermocouples often used measure TCASE. Before temperature measurements made, thermocouples must calibrated. When surface temperature measurement differs from surrounding local ambient temperature, errors could introduced measurements. These measurement errors result from having poor thermal contact between thermocouple junction surface package, heat loss radiation, convection, conduction through thermocouple leads, contact between thermocouple cement heat-sink base heat-sink solutions. minimize these measurement errors, following approach recommended: Attaching Thermocouple:
gauge smaller diameter type thermocouples. Ensure that thermocouple been properly calibrated.
Datasheet
82807AA
Attach thermocouple bead junction surface package (case) center mold-cap using high thermal conductivity cements. alternative tape attaches users tape itself mount thermocouple. Critical that thermocouple closely connected across entire moldcap. thermocouple should attached angle there interference with thermocouple attaches location leads. This preferred method recommended with both unenhanced packages well packages employing Thermal Enhancements. Figure Technique Measuring TCASE With Angle Attachment
thermocouple cannot attached, thermocouple attached angle. hole size through heat sink base route thermocouple wires should smaller than 0.150" diameter. Make sure there contact between thermocouple cement heat sink base. This contact will affect thermocouple reading. Figure Technique Measuring TCASE With Angle Attachment
Datasheet
82807AA
9.1.
Appendix
CMOS Interface Pixel Data Mapping
Table specifies various data formats panels.
Table CMOS Flat Panel
Name Bn[0] Bn[1] Bn[2] Bn[3] Bn[4] Bn[5] Bn[6] Bn[7] Gn[0] Gn[1] Gn[2] Gn[3] Gn[4] Gn[5] Gn[6] Gn[7] Rn[0] Rn[1] Rn[2] Rn[3] Rn[4] Rn[5] Rn[6] Rn[7] 1x24 Bn[0] Bn[1] Bn[2] Bn[3] Bn[4] Bn[5] Bn+1[0] Bn+1[1] Bn+1[2] Bn+1[3] Bn+1[4] Bn+1[5] Gn[0] Gn[1] Gn[2] Gn[3] Gn[4] Gn[5] Gn+1[0] Gn+1[1] Gn+1[2] Gn+1[3] Gn+1[4] Gn+1[5] Rn[0] Rn[1] Rn[2] Rn[3] Rn[4] Rn[5] Rn+1[0] Rn[0] Rn[1] Rn[2] Rn[3] Rn[4] Rn[5] Gn[0] Gn[1] Gn[2] Gn[3] Gn[4] Gn[5] 2x18 Bn[0] Bn[1] Bn[2] Bn[3] Bn[4] Bn[5] 1x18
Datasheet
82807AA
Name
1x24 Rn+1[1] Rn+1[2] Rn+1[3] Rn+1[4]
2x18
1x18
Rn+1[5] NOTES: denotes pixel data. denote red, green, blue color elements pixel LSB.
9.2.
LVDS Interface Pixel Data Serial Mapping
LVDS Pair CLKA CLKB Gn[0] Bn[1] Disabled Disabled Disabled Disabled Disabled Disabled Data Rn[5] Bn[0] Data Rn[4] Gn[5] Data Rn[3] Gn[4] Bn[5] Data Rn[2] Gn[3] Bn[4] Data Rn[1] Gn[2] Bn[3] Data Rn[0] Gn[1] Bn[2] Data
Table LVDS Conventional Data Mapping 1x18 Interface
Table LVDS Conventional Data Mapping 2x18 Interface
LVDS Pair CLKA CLKB Gn[0] Bn[1] Disabled Gn+1[0] Bn+1[1] Rn+1[5] Bn+1[0] Rn+1[4] Gn+1[5] Rn+1[3] Gn+1[4] Rn+1[2] Gn+1[3] Rn+1[1] Gn+1[2] Rn+1[0] Gn+1[1] Data Rn[5] Bn[0] Data Rn[4] Gn[5] Data Rn[3] Gn[4] Bn[5] Data Rn[2] Gn[3] Bn[4] Data Rn[1] Gn[2] Bn[3] Data Rn[0] Gn[1] Bn[2] Data
Disabled
Bn+1[5]
Bn+1[4]
Bn+1[3]
Bn+1[2]
NOTES: denotes pixel data. denote red, green, blue color elements pixel. Based naming conventions, mapped follows, each color element gray scale.
Datasheet
82807AA
Table LVDS Conventional Data Mapping 1x24 Interface
LVDS Pair CLKA CLKB Gn[2] Bn[3] Disabled Disabled Disabled Disabled Disabled Data Rn[7] Bn[2] Bn[1] Data Rn[6] Gn[7] Bn[0] Data Rn[5] Gn[6] Bn[7] Gn[1] Data Rn[4] Gn[5] Bn[6] Gn[0] Data Rn[3] Gn[4] Bn[5] Rn[1] Data Rn[2] Gn[3] Bn[4] Rn[0] Data
Datasheet
82807AA
Table LVDS Conventional Data Mapping 2x24 Interface
LVDS Pair CLKA CLKB Gn[2] Bn[3] Gn+1[2] Bn+1[3] Data Rn[7] Bn[2] Bn[1] Rn+1[7] Bn+1[2] Bn+1[1] Data Rn[6] Gn[7] Bn[0] Rn+1[6] Gn+1[7] Bn+1[0] Data Rn[5] Gn[6] Bn[7] Gn[1] Rn+1[5] Gn+1[6] Bn+1[7] Gn+1[1] Data Rn[4] Gn[5] Bn[6] Gn[0] Rn+1[4] Gn+1[5] Bn+1[6] Gn+1[0] Data Rn[3] Gn[4] Bn[5] Rn[1] Rn+1[3] Gn+1[4] Bn+1[5] Rn+1[1] Data Rn[2] Gn[3] Bn[4] Rn[0] Rn+1[2] Gn+1[3] Bn+1[4] Rn+1[0] Data
Table LVDS Non-Conventional Conventional Data Mapping
Signal Name CONV Channel (YA0) Channel (YA1) NCON Color Name CONV NCON CONV NCON CONV NCON
Channel (YA2)
Datasheet
82807AA
Signal Name CONV Channel (YA3) Channel (YB0) Channel (YB1) NCON
Color Name CONV NCON CONV NCON CONV NCON
Channel (YB2) Channel (YB3) CNTLF CNTLE
Datasheet
82807AA
Signal Name CONV NCON
Color Name CONV NCON CONV NCON CONV NCON
NOTES: CONV Conventional. NCon Non-Conventional.
Datasheet

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