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PENTIUM® PROCESSOR iCOMP® INDEX 610\75
Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit with 64-Bit Data Superscalar Architecture Pipelined Integer Units Capable Instructions/Clock Pipelined Floating Point Unit Separate Code Data Caches Code, Writeback Data MESI Cache Protocol Advanced Design Features Branch Prediction Virtual Mode Extensions
3.3V BiCMOS Silicon Technology Pages Increased Rate IEEE 1149.1 Boundary Scan Internal Error Detection Features Enhanced Power Management Features System Management Mode Clock Control Fractional Operation 75-MHz Core 50-MHz
Pentium® processor fully compatible with entire installed base applications DOS*, Windows*, OS/2*, UNIX*, other software that runs earlier Intel 8086 family product. Pentium processor's superscalar architecture execute instructions clock cycle. Branch prediction separate caches also increase performance. pipelined floating-point unit delivers workstation level performance. Separate code data caches reduce cache conflicts while remaining software transparent. Pentium processor (610\75) million transistors, built Intel's advanced 3.3V BiCMOS silicon technology, full Enhanced power management features, including System Management Mode (SMM) clock control. additional Enhanced features, 3.3V operation, package, which available Pentium processor (510\60, 567\66), make Pentium processor (610\75) ideal enabling mobile Pentium processor designs. Pentium processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available upon request.
June 1997
Order Number 242323-004
PENTIUM PROCESSOR (610\75)
CONTENTS
1.0. INTRODUCTION.2 1.1. Pentium® Processor (610\75) SPGA Specifications Differences from Package.2 2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW 2.1. Pentium® Processor Family Architecture.4 3.0. PINOUT.7 3.1. Pinout Descriptions.7 3.1.1. Pentium® Processor (610\75) PINOUT 3.1.2. CROSS REFERENCE TABLE Pentium® Processor (610\75) TCP.8 3.2. Design Notes.10 3.3. Quick Reference.10 3.4. Reference Tables.19 3.5. Grouping According Function.22 4.0. Pentium® Processor (610\75) ELECTRICAL SPECIFICATIONS.23 4.1. Maximum Ratings.23 4.2. Specifications.23
4.3. Specifications.25 4.3.1. POWER GROUND.25 4.3.2. DECOUPLING RECOMMENDATIONS25 4.3.3. CONNECTION SPECIFICATIONS 4.3.4. TIMINGS 50-MHZ BUS.26 4.4. Buffer Models.35 4.4.1. BUFFER MODEL PARAMETERS.38 4.4.2. SIGNAL QUALITY SPECIFICATIONS 4.4.2.1. Ringback.40 4.4.2.2. Settling Time.40 5.0. Pentium® Processor (610\75) MECHANICAL SPECIFICATIONS.42 5.1. Package Mechanical Diagrams.42 6.0. Pentium® Processor (610\75) THERMAL SPECIFICATIONS.47 6.1. Measuring Thermal Values.47 6.2. Thermal Equations.47 6.3. Thermal Characteristics 6.4. Board Enhancements 6.4.1. STANDARD TEST BOARD CONFIGURATION
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O. 7641 Prospect 60056-7641 call 1-800-879-4683 visit Intel's website http:\\www.intel.com Copyright Intel Corporation 1996, 1997. Third-party brands names property their respective owners.
PENTIUM PROCESSOR (610\75)
1.0. INTRODUCTION
Intel manufacturing latest version Pentium® processor family that designed specifically mobile systems, with core frequency frequency MHz. Pentium processor (610\75) provided (Tape Carrier Package) SPGA packages, advanced features Pentium processor (735\90, 815\100) Pentium processor (610\75) package several features which allow highperformance notebooks designed with Pentium processor, including following: package dimensions ideal small form-factor designs. package resistance characteristics. superior thermal
List related documents: Pentium® Processor Family Developer' Manual, Vol. (Order Number: 241428) Pentium® Processor Family Developer' Manual, Vol. Architecture Programming Manual (Order Number: 241430)
1.1. Pentium Processor (610\75) SPGA Specifications Differences from Package
This section provides references Pentium processor (610\75) SPGA specifications describes major differences between Pentium processor (610\75) SPGA packages. Pentium processor (610\75) SPGA specifications, with exception power consumption, identical Pentium processor (735\90, 815\100) specifications provided Pentium® Processor Family Developer' Manual, Volume Tables section Pentium processor (610\75) SPGA power specifications. following features have been eliminated Pentium processor (610\75) TCP: Upgrade feature, Dual Processing (DP) feature, Master/Checker functional redundancy feature. Table lists corresponding pins which exist Pentium processor (610\75) SPGA have been removed Pentium processor (610\75) TCP.
3.3V reduces power consumption half both SPGA packages). Enhanced feature set, which initially implemented Intel486CPU. architecture internal features Pentium processor (610\75) SPGA packages identical those Pentium processor (735\90, 815\100), although several features have been eliminated Pentium processor (610\75) TCP, described section 1.1. This document should used conjunction with Pentium processor documents listed below.
PENTIUM PROCESSOR (610\75)
Table SPGA Signals Removed Signal ADSC# Function Additional Address Status. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Additional Burst Ready. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Type. This signal used dual processing systems. Dual/Primary processor identification. This signal only used Upgrade processor. Functional Redundancy Checking. This signal only used error detection processor redundancy, requires Pentium processors (master/checker). Private Grant. This signal only used dual processing systems. Private Request. This signal used only dual processing systems. Private Hit. This signal only used dual processing systems. Private Modified Hit. This signal only used dual processing systems. processor (610\75)" will used this document refer Pentium processor iCOMP rating 610\75 MHz. "Pentium Processor" will used this document refer entire Pentium processor family general. Pentium processor family architecture contains features Intel486 family, provides significant enhancements additions including following: Superscalar Architecture Dynamic Branch Prediction Pipelined Floating-Point Unit Improved Instruction Execution Time Separate Code Data Caches Writeback MESI Protocol Data Cache 64-Bit Data Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode
BRDYC#
CPUTYP D/P# FRCMC#
PBGNT# PBREQ# PHIT# PHITM#
buffer models provided section this document apply both Pentium processor (610\75) SPGA packages, although capacitance (Cp) inductance (Lp) parameter values differ between packages. Also, thermal parameters, TCASE differ between SPGA packages. Pentium processor (610\75) SPGA values, refer Chapters Pentium® Processor Family Developer' Manual, Volume
2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW
Pentium processor iCOMP® rating 610\75 extends Intel Pentium family microprocessors. compatible with 8086/88, 80286, Intel386DX CPU, Intel386 CPU, Intel486DX CPU, Intel486 CPU, Intel486 CPUs, Pentium processor iCOMP Index 510\60 iCOMP Index 567\66 MHz, Pentium processor iCOMP Index 735\90 iCOMP Index 815\100 MHz. Pentium processor family consists Pentium processor iCOMP rating 610\75 MHz, described this document, original Pentium processor (510\60, 567\66), Pentium processor (735\90, 815\100). name "Pentium
PENTIUM PROCESSOR (610\75)
Virtual Mode Extensions writeback writethrough line-by-line basis follows MESI protocol. data cache tags triple ported support data transfers inquire cycle same clock. code cache inherently write-protected cache. code cache tags also triple ported support snooping split line accesses. Individual pages configured cacheable non-cacheable software hardware. caches enabled disabled software hardware. Pentium processors have increased data bits improve data transfer rate. Burst read burst writeback cycles supported Pentium processors. addition, cycle pipelining been added allow cycles progress simultaneously. Pentium processors' Memory Management Unit contains optional extensions architecture which allow 2-Mbyte 4-Mbyte page sizes. Pentium processors have added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking, internal parity checking features have been added along with exception, chine check exception. more more functions integrated chip, complexity board level testing increased. address this, Pentium processors have increased test debug capability. Pentium processors implement IEEE Boundary Scan (Standard 1149.1). addition, Pentium processors have specified breakpoint pins that correspond each debug registers externally indicate breakpoint match. Execution tracing provides external indications when instruction completed execution either internal pipelines, when branch been taken. System Management Mode (SMM) been implemented along with some extensions architecture. Enhancements virtual 8086 mode have been made increase performance reducing number times necessary trap tual 8086 monitor.
2.1. Pentium Processor Family Architecture
application instruction Pentium processor family includes complete Intel486 family instruction with extensions accommodate some additional functionality Pentium processors. application software written Intel386 Intel486 family microprocessors will Pentium processors without modification. on-chip memory management unit (MMU) completely compatible with Intel386 family Intel486 family CPUs. Pentium processors implement several enhancements increase performance. instruction pipelines floating-point unit Pentium processors capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating point instruction (under certain circumstances, floating-point instructions) clock. Branch prediction implemented Pentium processors. support this, Pentium processors implement prefetch buffers, prefetch code linear fashion, that prefetches code according needed code almost always prefetched before needed execution. floating-point unit been completely redesigned over Intel486 CPU. Faster algorithms provide speed-up common operations including add, multiply, load. Pentium processors include separate code data caches integrated on-chip meet performance goals. Each cache Kbytes size, with 32-byte line size 2-way associative. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable
PENTIUM PROCESSOR (610\75)
Figure Pentium Processor Block Diagram
PENTIUM PROCESSOR (610\75)
block diagram shows instruction pipelines, pipe pipe. u-pipe execute integer floating point instructions. v-pipe execute simple integer instructions FXCH floating-point instructions. separate caches shown, code cache data cache. data cache ports, each pipes (the tags triple ported allow simultaneous inquire cycles). data cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses used data cache. code cache, branch target buffer prefetch buffers responsible getting instructions into execution units Pentium processor. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache. decode unit decodes prefetched instructions Pentium processor execute instruction. control contains microcode which controls sequence operations that must performed implement Pentium processor architecture. control unit direct control over both pipelines. Pentium processors contain pipelined floating-point unit that provides significant floating-point performance advantage over previous generations processors. architectural features introduced this section more fully described Pentium® Processor Family Developer' Manual
PENTIUM PROCESSOR (610\75)
3.0. PINOUT 3.1. Pinout Desc riptions
3.1.1. Pentium Processor (610\75) PINOUT
Figure Pentium Processor (610\75) Pinout
PENTIUM PROCESSOR (610\75)
3.1.2. CROSS REFERENCE TABLE Pentium Processor (610\75) Table Cross Reference Name Address Data
PENTIUM PROCESSOR (610\75)
Table Cross Reference Name (Contd.) Control A20M# ADS# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY# BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR# FLUSH# HIT# APIC PICCLK PICD0 [DPEN#] PICD1 [APICEN] HITM# HLDA HOLD IERR# IGNNE# INIT INTR/LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK# PEN# PM0/BP0 Clock Control STPCLK# PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# W/R# WB/WT#
PENTIUM PROCESSOR (610\75)
Table Cross Reference Name (Contd.) 111* 153* 157* 165* 168* 170* 172* 174* 177* 180* 183* 188* 190* 195* 217* 225* 232* 240* 243* 249* 257* 260* 266* 268* 304* 309* 317*
NOTE: *These pins 3.3V supplies Pentium processor (610\75) will lower voltage pins future offerings this microprocessor family. other pins will remain 3.3V.
3.2. Design Notes
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected Vcc. Unused active HIGH inputs should connected (Vss).
Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with processor steppings.
3.3. Quick Reference
This section gives brief functional description each pins. detailed description, "Hardware Interface" chapter Pentium® Processor Family Developer' Manual Volume
PENTIUM PROCESSOR (610\75)
Note that input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active, asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level.
Table Quick Reference Symbol A20M# Type Name Function When address mask asserted, Pentium processor (610\75) emulates address wraparound Mbyte which occurs 8086. When A20M# asserted, Pentium processor (610\75) masks physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address status indicates that valid cycle currently being driven Pentium processor (610\75) response assertion address hold Pentium processor (610\75) will stop driving address lines (A31-A3), next clock. rest will remain active data returned driven previously issued cycles. Address parity driven Pentium processor (610\75) with even parity information Pentium processor (610\75) generated cycles same clock that address driven. Even parity must driven back Pentium processor (610\75) during inquire cycles this same clock EADS# ensure that correct parity check status indicated Pentium processor (610\75). address parity check status asserted clocks after EADS# sampled active Pentium processor (610\75) detected parity error address during inquire cycles. APCHK# will remain active clock each time parity error detected. Advanced Programmable Interrupt Controller Enable enables disables on-chip APIC interrupt controller. sampled high falling edge RESET, APIC enabled. APICEN shares with Programmable Interrupt Controller Data signal. byte enable pins used determine which bytes must written external memory, which bytes were requested current cycle. byte enables driven same clock address lines (A31-3). lower four byte enables (BE3#-BE0#) used Pentium processor (610\75) APIC inputs sampled RESET.
A31-A3
ADS# AHOLD
APCHK#
[APICEN] PICD1
BE7#-BE5# BE4#-BE0#
PENTIUM PROCESSOR (610\75)
Table Quick Reference (Contd.) Symbol [BF] Type Name Function Frequency determines -to-core frequency ratio. sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, must change values while RESET active. proper operation Pentium processor (610\75) this should strapped high low. When strapped processor will operate bus/core frequency ratio. When strapped processor will operate bus/core frequency ratio. left floating, Pentium processor (610\75) defaults ratio. Note Pentium processor (610\75) will operate bus/core frequency ratio. backoff input used abort outstanding cycles that have completed. response BOFF#, Pentium processor (610\75) will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time Pentium processor (610\75) restarts aborted cycle(s) their entirety. breakpoint pins (BP3-0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. BRDY# burst ready input indicates that external system presented valid data data pins response read that external system accepted Pentium processor (610\75) data response write request. This signal sampled states. request output indicates external system that Pentium processor (610\75) internally generated request. This signal always driven whether Pentium processor (610\75) driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, Pentium processor (610\75) will latch address control signals machine check registers. addition, set, Pentium processor (610\75) will vector machine check exception. Pentium processor (610\75) -initiated cycles cache indicates internal cacheability cycle read), indicates burst writeback cycle write). this driven inactive during read cycle, Pentium processor (610\75) will cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle).
BOFF#
BP[3:2] PM/BP[1:0]
BREQ
BUSCHK#
CACHE#
PENTIUM PROCESSOR (610\75)
Table Quick Reference (Contd.) Symbol Type Name Function clock input provides fundamental timing Pentium processor (610\75). frequency operating frequency Pentium processor (610\75) external requires levels. external timing parameters except TDI, TDO, TMS, TRST#, PICD0-1 specified with respect rising edge CLK. data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When driving data lines, they driven during T12, clocks that cycle. During reads, samples data when BRDY# returned. These data parity pins processor. There each byte data bus. They driven Pentium processor (610\75) with even parity information writes same clock write data. Even parity information must driven back Pentium processor (610\75) these pins same clock data ensure that correct parity check status indicated Pentium processor (610\75) applies D63-D56; applies D7-D0. Dual processing enable output Dual processor input Primary processor. Dual processor drives DPEN# Primary processor RESET indicate that Primary processor should enable dual processor mode. Since dual processing feature supported Pentium processor (610\75) package, DPEN# should never asserted (low) RESET. DPEN# shares with PICD0. This signal indicates that valid external address been driven onto Pentium processor (610\75) address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When Pentium processor (610\75) generates write, EWBE# sampled inactive, Pentium processor (610\75) will hold subsequent writes M-state lines data cache until write cycles have completed, indicated EWBE# being active. floating point error driven active when unmasked floating point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using DOS-type floating point error reporting.
D/C#
D63-D0
DP7-DP0
[DPEN#] PICD0
EADS# EWBE#
FERR#
PENTIUM PROCESSOR (610\75)
Table Quick Reference (Contd.) Symbol FLUSH# Type Name Function When asserted, cache flush input forces Pentium processor (610\75) write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated Pentium processor (610\75) indicating completion writeback invalidation. FLUSH# sampled when RESET transitions from high low, tristate test mode entered. HIT# indication driven reflect outcome inquire cycle. inquire cycle hits valid line either Pentium processor (610\75) data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses Pentium processor (610\75) cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that Pentium processor (610\75) floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive Pentium processor (610\75) will resume driving bus. Pentium processor (610\75) cycle pending, will driven same clock that HLDA de-asserted. response hold request Pentium processor (610\75) will float most output input/output pins assert HLDA after completing outstanding cycles. Pentium processor (610\75) will maintain this state until HOLD de-asserted. HOLD recognized during LOCK cycles. Pentium processor (610\75) will recognize HOLD during reset. internal error used indicate internal parity errors. parity error occurs read from internal array, Pentium processor (610\75) will assert IERR# clock then shutdown. This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, Pentium processor (610\75) will ignore pending unmasked numeric exception continue executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, Pentium processor (610\75) will execute instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, Pentium processor (610\75) will stop execution wait external interrupt.
HITM#
HLDA
HOLD
IERR#
IGNNE#
PENTIUM PROCESSOR (610\75)
Table Quick Reference (Contd.) Symbol INIT Type Name Function Pentium processor (610\75) initialization input forces Pentium processor (610\75) begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating point registers retain values they prior INIT. INIT used lieu RESET after power INIT sampled high when RESET transitions from high low, Pentium processor (610\75) will perform built-in self test prior start program execution. INTR LINT0 active maskable interrupt input indicates that external interrupt been generated. EFLAGS register set, Pentium processor (610\75) will generate locked interrupt acknowledge cycles vector interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated assure that interrupt recognized. local APIC enabled, this becomes local interrupt invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When Pentium processor (610\75) generates cycle that cached (CACHE# asserted) KEN# active, cycle will transformed into burst line fill cycle. APIC enabled, this local interrupt APIC disabled, this interrupt. APIC enabled, this local interrupt APIC disabled, this non-maskable interrupt lock indicates that current cycle locked. Pentium processor (610\75) will allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed de-asserted least clock between back-to-back locked cycles. memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles.
KEN#
LINT0/INTR LINT1/NMI LOCK#
M/IO#
PENTIUM PROCESSOR (610\75)
Table Quick Reference (Contd.) Symbol Type Name Function active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. Pentium processor (610\75) will issue ADS# pending cycle clocks after asserted. Pentium processor (610\75) supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. local APIC enabled, this becomes local interrupt page cache disable reflects state CR3, Page Directory Entry, Page Table Entry. purpose provide external cacheability indication page-by-page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned. parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. this sampled active clock data parity error detected, Pentium processor (610\75) will latch address control signals cycle with parity error machine check registers. addition, machine check enable "1", Pentium processor (610\75) will vector machine check exception before beginning next instruction. APIC interrupt controller serial data clock driven into programmable interrupt controller clock input Pentium processor (610\75). Programmable interrupt controller data lines Pentium processor (610\75) comprise data portion APIC 3-wire bus. They opendrain outputs that require external pull-up resistors. These signals share pins with DPEN# APICEN. These pins function part performance monitoring feature. breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. PRDY probe ready output indicates that processor stopped normal execution response R/S# going active, Probe Mode being entered. page writethrough reflects state CR3, page directory entry, page table entry. used provide external writeback indication page-by-page basis.
NMI/LINT1
PCHK#
PEN#
PICCLK
PICD0-1 [DPEN#] [APICEN] PM/BP[1:0]
PENTIUM PROCESSOR (610\75)
Table Quick Reference (Contd.) Symbol R/S# Type Name Function stop input asynchronous, edge-sensitive interrupt used stop normal execution processor place into idle state. high transition R/S# will interrupt processor cause stop execution next instruction boundary. RESET forces Pentium processor (610\75) begin execution known state. Pentium processor (610\75) internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine tristate test mode will entered, BIST will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock Pentium processor (610\75) thereby causing core consume less power. When recognizes STPCLK#, processor will stop execution next instruction boundary, unless superseded higher priority interrupt, generate Stop Grant Acknowledge cycle. When STPCLK# asserted, Pentium processor (610\75) will still pond external snoop requests. testability clock input provides clocking function Pentium processor (610\75) boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into Pentium processor (610\75) during boundary scan. test data input serial input test logic. instructions data shifted into Pentium processor (610\75) rising edge when controller appropriate state. test data output serial output test logic. instructions data shifted Pentium processor (610\75) TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized.
RESET
SCYC
SMI#
SMIACT# STPCLK#
TRST#
PENTIUM PROCESSOR (610\75)
Table Quick Reference (Contd.) Symbol W/R# Type Name Function Pentium processor (610\75) 3.3V power inputs. Pentium processor (610\75) ground inputs. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. writeback/writethrough input allows data cache line defined writeback writethrough line-by-line basis. result, determines whether cache line initially state data cache.
WB/WT#
3.4. Reference Tables
Table Output Pins Name ADS# APCHK# BE7#-BE5# BREQ CACHE# FERR# HIT# HITM# HLDA IERR# LOCK# M/IO#, D/C#, W/R# PCHK# BP3-2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC SMIACT# High High High High High High states except Shift-DR Shift-IR Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Active Level When Floated Hold, BOFF#
NOTE: output input/output pins floated during tristate test mode (except TDO).
PENTIUM PROCESSOR (610\75)
Table Input Pins Name A20M# AHOLD BOFF# BRDY# BUSCHK# EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR KEN# PEN# PICCLK R/S# RESET SMI# STPCLK# TRST# WB/WT# Active Level High High High High High High High High High Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY#/NA# Pullup Pullup BRDY# EADS# First BRDY#/NA# State T2,TD,T2P BRDY# Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous Synchronous Synchronous Pullup State T12, BRDY# Pullup Internal resistor Qualified
PENTIUM PROCESSOR (610\75)
Table Input/Output Pins Name A31-A3 BE4#-BE0# D63-D0 DP7-DP0 PICD0[DPEN#] PICD1[APICEN]
NOTES: output input/output pins floated during tristate test mode (except TDO). *BE3#-BE0# have pulldowns during RESET only.
Active Level
When Floated Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF#
Qualified (when input) EADS# EADS# RESET BRDY# BRDY#
Internal Resistor
Pulldown*
Pullup Pulldown
PENTIUM PROCESSOR (610\75)
3.5. Grouping According Function
Table organizes pins with respect their function. Table Functional Grouping Function Clock Initialization Address Address Mask Data Address Parity APIC Support Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Interrupts Floating Point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Clock Control Probe Mode RESET, INIT A31-A3, BE7# BE0# A20M# D63-D0 APCHK# PICCLK, PICD0-1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-2 STPCLK# R/S#, PRDY Pins
PENTIUM PROCESSOR (610\75)
4.0. Pentium Processor (610\75) ELECTRICAL SPECIFICATIONS 4.1. Maximum Ratings
following values stress ratings only. Functional operation maximum ratings implied guaranteed. Functional operating conditions given specification tables. Extended exposure maximum ratings affect device reliability. Furthermore, although Pentium processor (610\75) contains protective circuitry resist damage from static electric discharge, always take precautions avoid high static voltages electric fields. Case temperature under bias -65° 110° Storage temperature. -65° 150° Supply voltage with respect -0.5V +4.6V Only Buffer Input Voltage -0.5V 0.5; exceed 4.6V Safe Buffer Input Voltage .-0.5V 6.5V
NOTES: Applies PICCLK. Applies Pentium processor (610\75) inputs except PICCLK. Table
WARNING Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
4.2. Specifications
Tables list specifications which apply Pentium processor (610\75). Pentium processor (610\75) 3.3V part internally. PICCLK inputs 3.3V inputs. Since 3.3V safe) input levels defined Table same levels, PICCLK inputs compatible with existing clock drivers. power dissipation specification Table provided design thermal solutions during operation sustained maximum level. This worst-case power device would dissipate system sustained period time. This number used design thermal solution device.
(1,3)
Table 3.3V Specifications TCASE 3.3V Symbol VIL3 VIH3 VOL3 VOH3 ICC3 Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Power Supply Current 2650 -0.3 Vcc+0.3 Unit Notes Level Level Level Level
NOTES: Parameter measured Parameter measured 3.3V levels apply signals except PICCLK. This value should used power supply design. determined using worst-case instruction Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from stop clock full active modes. more information, refer section 4.3.2.
PENTIUM PROCESSOR (610\75)
Table 3.3V Safe) Specifications Symbol VIL5 VIH5 Parameter Input Voltage Input High Voltage -0.3 5.55 Unit Notes Level Level
NOTES: Applies PICCLK only.
Table Input Output Characteristics Symbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input Leakage Current Input Leakage Current -400 Unit 2.4V 0.4V Notes
NOTES: This parameter input without pull pull down. This parameter input with pull This parameter input with pull down. Guaranteed design.
PENTIUM PROCESSOR (610\75)
Table Power Dissipation Requirements Thermal Solution Design Parameter Active Power Dissipation Stop Grant Auto Halt Powerdown Power Dissipation Stop Clock Power Dissipation Typical Max(2) Unit Watts Watts Watts Notes
NOTES: This typical power dissipation system. This value average value measured system using typical device 3.3V running typical applications. This value highly dependent upon specific system configuration. Systems must designed thermally dissipate maximum active power dissipation. determined using worstcase instruction with 3.3V. nominal this measurement takes into account thermal time constant package. Stop Grant/Auto Halt Powerdown Power Dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input. Complete characterization specification still process time print. Please contact Intel latest information. final specification less than
4.3. Specifications
specifications Pentium processor (610\75) consist setup times, hold times, valid delays WARNING exceed Pentium processor (610\75) internal maximum frequency either selecting fraction providing clock greater than MHz. 4.3.1. POWER GROUND
performance. Inductance reduced shortening circuit board traces between Pentium processor (610\75) decoupling capacitors much possible. These capacitors should evenly distributed around each component 3.3V plane. Capacitor values should chosen ensure they eliminate both high frequency noise components. Pentium processor (610\75), power consumption transition from level power much higher level high power) very rapidly. typical example would entering exiting Stop Grant state. Another example would executing HALT instruction, causing Pentium processor (610\75) enter Auto HALT Powerdown state, transitioning from HALT Normal state. these examples cause abrupt changes power being consumed Pentium processor (610\75). Note that Auto HALT Powerdown feature always enabled even when other power management features implemented. Bulk storage capacitors with (Effective Series Resistance) range required maintain regulated supply voltage during interval between time current load changes point that regulated power supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel.
clean on-chip power distribution, Pentium processor (610\75) (power) (ground) inputs. Power ground connections must made external pins Pentium processor (610\75). circuit board pins must connected 3.3V plane. pins must connected plane. 4.3.2. DECOUPLING RECOMMENDATIONS
Liberal decoupling capacitance should placed near Pentium processor (610\75). Pentium processor (610\75) driving large address data buses high frequencies cause transient power surges, particularly when driving large capacitive loads. inductance capacitors interconnects recommended best high frequency electrical
PENTIUM PROCESSOR (610\75)
These capacitors should placed near Pentium processor (610\75) 3.3V plane) ensure that supply voltage stays within specified limits during changes supply current during operation. 4.3.3. CONNECTION SPECIFICATIONS 4.3.4. TIMINGS 50-MHZ
specifications given Table consist output delays, input setup requirements input hold requirements 50-MHz external bus. specifications (with exception those signals APIC signals) relative rising edge input. timings referenced 1.5V both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct Pentium processor (610\75) operation.
pins must remain unconnected. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected Vcc. Unused active high inputs should connected ground.
Table Pentium Processor (610\75) Specifications 50-MHz Operation 3.3V± CASE Symbol Frequency Period Period Stability High Time Time Fall Time Rise Time ADS#, PWT, PCD, BE0-7#, M/IO#, D/C#, CACHE#, SCYC, W/R# Valid Delay Valid Delay A3-A31, LOCK# Valid Delay 0.15 0.15 Parameter 25.0 20.0 50.0 40.0 ±250 Unit (1), (19) @2V, @0.8V, (2.0V-0.8V), (1), (0.8V-2.0V), (1), Figure Notes Core Freq.
PENTIUM PROCESSOR (610\75)
Table Pentium Processor (610\75) Specifications 50-MHz Operation (Contd.) 3.3V± CASE Symbol Parameter ADS#, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR#, PCHK# Valid Delay BREQ, HLDA, SMIACT# Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY# Setup Time BRDY# Hold Time BOFF# Setup Time AHOLD Setup Time AHOLD, BOFF# Hold Time 10.0 Unit Figure Notes
t10a t10b t11a t11b t16a t16b t18a t18b t22a
10.0 10.0
(20)
PENTIUM PROCESSOR (610\75)
Table Pentium Processor (610\75) Specifications 50-MHz Operation (Contd.) 3.3V± CASE Symbol t25a Parameter BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Unit CLKs CLKs CLKs Figure (11), (15) (12) (16) Power (15), (16) (12) (11), (15) (12) (11), (15), (16) (12) (14), (16) (11), (15) (12) (14), (16) Notes
PENTIUM PROCESSOR (610\75)
Table Pentium Processor (610\75) Specifications 50-MHz Operation (Contd.) 3.3V± CASE Symbol t42a Parameter Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDY#, BUSCHK#) Hold Time, Async. Reset Configuration Signal (BRDY#, BUSCHK#) Setup Time, Async. Reset Configuration Signal BRDY# Hold Time, RESET driven synchronously Setup Time Hold Time APICEN Setup Time APICEN Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay 40.0 13.0 20.0 25.0 20.0 Unit CLKs Figure Notes RESET falling edge (15) RESET falling edge (211) RESET falling edge (21) RESET falling edge (1), (21) (18) RESET falling edge (18) RESET falling edge RESET falling edge RESET falling edge
t42b
CLKs
t42c
CLKs
t42d
t43a t43b t43c t43d
62.5 25.0 25.0 16.0
CLKs CLKs CLKs
@2V, @0.8V, (2.0V- 0.8V), (1), (8), (0.8V- 2.0V), (1), (8), (1), Asynchronous (1), (3), (8), (10)
PENTIUM PROCESSOR (610\75)
Table Pentium Processor (610\75) Specifications 50-MHz Operation (Contd.) 3.3V± CASE Symbol Parameter Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 25.0 Unit Figure Notes (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
APIC Specifications t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay (LtoH) PICD0-1 Valid Delay (HtoL) 60.0 38.0 22.0 16.66 500.0 PICCLK PICCLK from PICCLK, (22) from PICCLK, (22)
NOTES: Notes general apply standard signals used with Pentium Processor family. 100% tested. Guaranteed design. input test waveforms assumed transitions with 1V/nS rise fall times. Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions (i.e., glitches). 0.8V/ns input rise/fall time 8V/ns. 0.3V/ns input rise/fall time 5V/ns. Referenced rising edge. Referenced falling edge. added maximum rise fall times every frequency below MHz. During probe mode operation, boundary scan timings 55-58). Setup time required guarantee recognition specific clock. Hold time required guarantee recognition specific clock. timings referenced from 1.5V. guarantee proper asynchronous recognition, signal must have been de-asserted (inactive) minimum clocks before being returned active must meet minimum pulse width. This input driven asynchronously. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must de-asserted (inactive) minimum clocks before being returned active. D/C#, M/IO#, W/R#, CACHE#, A5-A31 signals sampled only that ADS# active. should strapped Vss.
PENTIUM PROCESSOR (610\75)
These signals measured rising edge adjacent CLKs 1.5V. ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. Timing required external snooping (e.g., address setup which EADS# sampled active). BUSCHK# used reset configuration signal select buffer size. This assumes external pullup resistor lumped capacitive load. pullup resistor must between ohms ohms, capacitance must between product must between Each valid delay specified load. system designer should buffer modeling account signal flight time delays.
Figure Clock Waveform
PENTIUM PROCESSOR (610\75)
Figure Valid Delay Timings
Figure Float Delay Timings
PENTIUM PROCESSOR (610\75)
Figure Setup Hold Timings
Figure Reset Configuration Timings
PENTIUM PROCESSOR (610\75)
Figure Test Timings
Figure Test Reset Timings
PENTIUM PROCESSOR (610\75)
4.4. Buffer Models
This section describes buffer models Pentium processor (610\75) first order buffer model simplified representation complex input output buffers used Pentium processor (610\75). Figures show structure input buffer model Figure shows output buffer model. Tables show parameters used specify these models.
Although simplified, these buffer models will accurately model flight time signal quality. these parameters, there very little added accuracy complete transistor model. following models represent input buffer models. first model, Figure represents input buffers Pentium processor (610\75) except special group input buffers. second model, Figure represents these special buffers. These buffers inputs: AHOLD, EADS#, KEN#, WB/WT#, INV, NA#, EWBE#, BOFF#, CLK, PICCLK.
Figure Input Buffer Model, Except Special Group
PENTIUM PROCESSOR (610\75)
Figure Input Buffer Model Special Group
PENTIUM PROCESSOR (610\75)
Table Parameters Used Specification First Order Input Buffer Model Parameter Description Minimum Maximum value capacitance input buffer model. Minimum Maximum value package inductance. Minimum Maximum value package capacitance. Diode Series Resistance Ideal Diodes
Figure shows structure output buffer model. This model used output buffers Pentium processor (610\75)
Figure First Order Output Buffer Model Table Parameters Used Specification First Order Output Buffer Model Parameter dV/dt Description Minimum maximum value rate change open circuit voltage source used output buffer model. Minimum maximum value output impedance output buffer model. Minimum Maximum value capacitance output buffer model. Minimum Maximum value package inductance. Minimum Maximum value package capacitance.
addition input output buffer parameters, input protection diode models provided added accuracy. These diodes have been optimized provide protection provide some level clamping. Although diodes required simulation, more difficult meet specifications without them.
Note, however, some signal quality specifications require that diodes removed from input model. series resistors (Rs) part diode model. Remove these when removing diodes from input model.
PENTIUM PROCESSOR (610\75)
4.4.1. BUFFER MODEL PARAMETERS configurable output buffer EB2. Table shows drive level BRDY# required falling edge RESET select buffer strength. buffer sizes selected should appropriate size required; otherwise timings might met, much overshoot ringback occur. There other selection choices; configurable buffers same size same time.
This section gives parameters each Pentium processor (610\75) input, output, bidirectional signal, well settings configurable buffers. Some pins Pentium processor (610\75) have selectable buffer sizes. These pins
Table Buffer Selection Chart Environment Typical Stand Alone Component Loaded Component BRDY# EB2A Buffer Selection
NOTES: correct buffer selection, BUSCHK# signal must held inactive (high) falling edge RESET. Pentium processor (610\75) SPGA version, BRDYC# used configure selectable buffer sizes.
Please refer Table groupings buffers. Table Signal Buffer Type Signals A20M#, AHOLD, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, PICCLK, R/S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB/WT# APCHK#, BE[7:5]#, BP[3:2], BREQ, FERR#, IERR#, PCD, PCHK#, PM0/BP0, PM1/BP1, PRDY, PWT, SMIACT#, TDO, U/O# A[31:21], BE[4:0]#, CACHE#, D/C#, D[63:0], DP[8:0], HLDA, LOCK#, M/IO#, SCYC A[20:3], ADS#, HITM#, W/R# HIT# PID0, PICD1 input, output bidirectional buffer values listed Table This table contains listings three types, them confused during simulation. When bidirectional operating Type Driver Buffer Type Receiver Buffer Type
EB2A
input, just Cin, values; operating driver, data parameters.
PENTIUM PROCESSOR (610\75)
Table Input, Output Bidirectional Buffer Model Parameters Buffer Type Transition (input) (input) Rising Falling Rising Falling Rising 3/3.0 3/2.8 3/3.0 3/2.8 3/3.0 3/2.8 3/2.4 3/2.4 3/3.0 3/2.8 3/3.0 3/2.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.9 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 21.6 17.5 21.6 17.5 21.6 17.5 10.1 21.6 17.5 21.6 17.5 53.1 50.7 53.1 50.7 53.1 50.7 22.4 21.2 53.1 50.7 53.1 50.7 dV/dt (V/nsec) (Ohms) (pF) (nH) Co/Cin (pF)
(output) Falling (bidir) (bidir) EB2A (bidir) (bidir) (bidir) Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling
Table Input Buffer Model Parameters: (Diodes) Symbol Parameter Saturation Current Emission Coefficient Series Resistance Transit Time Potential Zero Bias Capacitance Grading Coefficient 1.4e-14A 1.19 ohms 0.983V 0.281 0.385 2.78e-16A 1.00 ohms 0.967V 0.365 0.376
4.4.2.
SIGNAL QUALITY SPECIFICATIONS
Signals driven system into Pentium processor (610\75) must meet signal quality specifications guarantee that components
read data properly ensure that incoming signals affect reliability component. There signal quality parameters: Ringback Settling Time.
PENTIUM PROCESSOR (610\75)
4.4.2.1. Ringback Excessive ringback contribute long-term reliability degradation Pentium processor (610\75), cause false signal detection. Ringback simulated input component using input buffer model. Ringback simulated with without diodes that input buffer model. Ringback absolute value voltage receiving below Vss) relative Vss) level after reached maximum voltage level. diodes assumed present. maximum above signal input meeting overshoot/undershoot specification, signal guaranteed ringback excessively. simulated with diodes present input model, follow maximum ringback specification. Overshoot (Undershoot) absolute value maximum voltage above (below Vss). guideline assumes absence diodes input. Maximum Overshoot/Undershoot 82497 Cache Controller, 82492 Cache SRAM Inputs (CLK PICCLK only) 1.6V above VCC5 (without diodes) Maximum Overshoot/Undershoot 3.3V Pentium processor (610\75) Inputs (not PICCLK) 1.4V above (without diodes)
Maximum Ringback Inputs 0.8V (with diodes) simulated without input diodes, follow Maximum Overshoot/Undershoot specification.
Figure Overshoot/Undershoot Ringback Guidelines 4.4.2.2. Settling Time settling time defined time signal requires receiver settle within percent Vss. Settling time maximum time allowed signal reach within percent final value. Most available simulation tools unable simulate settling time that accurately reflects silicon measurements. physical board, second-order effects other effects serve dampen signal receiver. Because these concerns, settling time recommendation tool layout tuning specification. Settling time simulated slow corner, make sure that there impact flight times signals waveform settled. Settling time
PENTIUM PROCESSOR (610\75)
simulated with diodes included excluded from input buffer model. diodes included, settling time recommendation will easier meet. Although simulated settling time shown good correlation with physical, measured settling time, settling time simulations still used tool tune layouts. following procedure verify board simulation tuning with concerns settling time. Simulate settling time slow corner particular signal. settling time violations occur, simulate signal trace with D.C. diodes place receiver pin. D.C. diode behaves almost identically actual (non-linear) diode part long excessive overshoot does occur. settling time violations still occur, simulate flight times consecutive cycles that particular signal. flight time values consistent over simulations, settling time should concern. however, flight times consistent over simulations, tuning layout required. Note that, signals that allocated cycles flight time, recommended settling time doubled. typical design method would include settling time that ensures signal within least prior period.
Figure Settling Time
PENTIUM PROCESSOR (610\75)
5.0. Pentium Processor (610\75) MECHANICAL SPECIFICATIONS
Today's portable computers face challenge meeting desktop performance environment that constrained thermal, mechanical, electrical design considerations. These considerations have driven development implementation Intel' Tape Carrier Package (TCP). Intel package been designed offer high count, profile, reduced footprint package with uncompromised thermal electrical performance. Intel continues provide packaging solutions that meet rigorous criteria quality performance, this entry into Intel package portfolio exception. features package include: surface mount technology design, lead pitch 0.25 polyimide body size polyimide
pick&place handling. components shipped with leads flat slide carriers, designed excised lead formed customer manufacturing site. Recommendations manufacture this package included Pentium® Processor (610\75) Tape Carrier Package User' Guide. Figure shows cross-sectional view package mounted Printed Circuit Board. Figures show shipped slide carrier, dimensions carrier package. Figure shows blow detail package cross-section. Figure shows enlarged view outer lead bond area package. Tables provide Pentium processor (610\75) package dimensions.
5.1. Package Mechanical Diagrams
Polyimide Support Ring Polyimide Keeper
Encapsulant Gold Bump
Lead (OFC Copper)
X-Section Thermally Electrically Conductive Adhesive (Silver Filled Thermoplastic) Thermal vias Ground plane Note: Sketches Scale
Full X-Section
Figure Cross-Sectional View Mounted Package
PENTIUM PROCESSOR (610\75)
Figure Site Carrier (Bottom View Die)
PENTIUM PROCESSOR (610\75)
Figure Site Carrier (Top View Die)
PENTIUM PROCESSOR (610\75)
Figure Site (Cross-Sectional Detail)
Figure Outer Lead Bond (OLB) Window Detail
PENTIUM PROCESSOR (610\75)
Table Dimensions Symbol Symbol D1,E1 Leadcount Tape Width Site Length Outer Lead Pitch Outer Lead Width Package Body Size Package Height Length Width Lead Thickness Encap Length Encap Width Description Description leads 48.18 ±0.12 (43.94) reference only 0.25 nominal 0.10 ±0.01 24.0 ±0.1 MHz/90 MHz-0.615 ±0.030 MHz-0.605 ±0.030 MHz/90 MHz-12.769 ±0.015 MHz-9.929 ±0.015 MHz/90 MHz-11.755 ±0.015 MHz-9.152 ±0.015 MHz/90 MHz-0.035 MHz-0.025 MHz/90 MHz-(13.40 reference only MHz-(10.56 reference only MHz/90 MHz-(12.39 reference only MHz-(9.78 reference only Dimension Dimension
NOTES: Dimensions millimeters unless otherwise noted. Dimensions parentheses reference only.
Table Mounted Package Dimensions Description Package Height Terminal Dimension Package Weight 0.75 max. 29.5 nom. max. Dimension
NOTE: Dimensions millimeters unless otherwise noted. Package terminal dimension (lead tip-to-lead tip) assumes keeper bar.
PENTIUM PROCESSOR (610\75)
6.0. Pentium Processor (610\75) THERMAL SPECIFICATIONS
Pentium processor (610\75) specified proper operation when case temperature, TCASE, (TC) within specified range
where,
6.1. Measuring Thermal Values
verify that proper (case temperature) maintained Pentium processor (610\75), should measured center package surface (encapsulant). minimize measurement errors, following techniques recommended: gauge finer diameter type thermocouples. Intel's laboratory testing done using thermocouple made Omega (part number: 5TC-TTK-36-36). Attach thermocouple bead junction center package surface using highly thermally conductive cements. Intel's laboratory testing done using Omega Bond (part number: OB-100). thermocouple should attached angle shown Figure
ambient case temperatures Case-to-Ambient thermal resistance C/W) Junction-to-Ambient thermal resistance C/W) Junction-to-Case thermal resistance C/W) maximum power consumption (Watts)
(maximum power consumption) specified section 4.2.
6.3. Thermal Characteristics
primary heat transfer path from Tape Carrier Package (TCP) through back side into board. There thermal paths traveling from board ambient air. spread heat within board dissipation heat board ambient air. other transfer heat through board opposite side where thermal enhancements (e.g., heat sinks, pipes) attached. prevent possibility damaging component, thermal enhancements should attached opposite side site directly mounted package surface.
6.4. Board Enhancements
Copper planes, thermal pads, vias design options that used improve heat transfer from board ambient air. Tables present thermal resistance data copper plane thickness effects. should noted that although thicker copper planes will reduce system without thermal enhancements, they have less effect system with thermal enhancements. However, placing vias under will reduce system with without thermal enhancements.
Figure Technique Measuring Case Temperature
6.2. Thermal Equations
Pentium processor (610\75), ambient temperature (TA) specified directly. only requirement that case temperature (TC) met. ambient temperature calculated from following equations:
PENTIUM PROCESSOR (610\75)
Table Thermal Resistance Copper Plane Thickness with without Enhancements Copper Plane Thickness* C/W) Enhancements C/W) With Heat Pipe NOTE Thermal resistance values should used guidelines only, highly system dependent. Final system verification should always refer case temperature specification. Table Pentium Processor (610\75) Package Thermal Resistance without Enhancements C/W) Thermal Resistance without Enhancements C/W) 13.9
NOTES: *225 vias underneath
Table Thermal Resistance Thermal Vias underneath Vias Under Die* C/W) Enhancements
Table Pentium Processor (610\75) Package Thermal Resistance with Enhancements (without Airflow) Thermal Enhancements Heat sink Plate C/W) 11.7 Notes
NOTE: copper planes test boards
6.4.1.
STANDARD TEST BOARD CONFIGURATION
Plate with Heat Pipe
Tape Carrier Package (TCP) thermal measurements provided following tables were taken with component soldered test board outline. This six-layer board contains vias (underneath die) attach which connected copper planes located layers five. Pentium processor (610\75) TCP, vias attach should connected without thermal reliefs ground plane(s). attached attach using thermally electrically conductive adhesive. This test board designed optimize heat spreading into board heat transfer through opposite side board.
Table Pentium Processor (610\75) Package Thermal Resistance with Enhancements (with Airflow) Thermal Enhancements Heat sink with Heat sink with Airflow Heat sink with Airflow
heat sink Linear Feet/Minute Cubic Feet/Minute
C/W) Notes