Download

PDF Abstract Text:

Order Number 242323-004

1.0. INTRODUCTION

Compatible with Large Software Base - MS-DOS, Windows, OS / 2, UNIX 32-Bit CPU with 64-Bit Data Bus Superscalar Architecture - Two Pipelined Integer Units Are Capable of 2 Instructions / Clock - Pipelined Floating Point Unit Separate Code and Data Caches - 8K Code, 8K Writeback Data - MESI Cache Protocol Advanced Design Features - Branch Prediction - Virtual Mode Extensions
3.3V BiCMOS Silicon Technology 4M Pages for Increased TLB Hit Rate IEEE 1149.1 Boundary Scan Internal Error Detection Features SL Enhanced Power Management Features - System Management Mode - Clock Control Fractional Bus Operation - 75-MHz Core / 50-MHz Bus
June 1997
Order Number 242323-004
CONTENTS
1.0. INTRODUCTION
BRDYC#
CPUTYP D / P# FRCMC#
PBGNT# PBREQ# PHIT# PHITM#
2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW
2.1. Pentium ® Processor Family Architecture
The application instruction set of the Pentium processor family includes the complete Intel486 CPU family instruction set with extensions to accommodate some of the additional functionality of the Pentium processors. All application software written for the Intel386 and Intel486 family microprocessors will run on the Pentium processors without modification. The on-chip memory management unit (MMU) is completely compatible with the Intel386 family and Intel486 family of CPUs. The Pentium processors implement several enhancements to increase performance. The two instruction pipelines and floating-point unit on Pentium processors are capable of independent operation. Each pipeline issues frequently used instructions in a single clock. Together, the dual pipes can issue two integer instructions in one clock, or one floating point instruction (under certain circumstances, two floating-point instructions) in one clock. Branch prediction is implemented in the Pentium processors. To support this, Pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the BTB so the needed code is almost always prefetched before it is needed for execution. The floating-point unit has been completely redesigned over the Intel486 CPU. Faster algorithms provide up to 10X speed-up for common operations including add, multiply, and load. Pentium processors include separate code and data caches integrated on-chip to meet performance goals. Each cache is 8 Kbytes in size, with a 32-byte line size and is 2-way set associative. Each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The data cache is configurable to be
Figure 1. Pentium ® Processor Block Diagram
3.0. TCP PINOUT 3.1. TCP Pinout and Pin Desc riptions
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) Control A20M# ADS# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY# 286 296 14 308 315 285 284 283 282 279 278 277 276 9 28 25 10 BREQ BUSCHK# CACHE# D / C# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# FLUSH# HIT# APIC PICCLK PICD0 DPEN# 155 156 PICD1 APICEN 158 BF CLK 186 272 312 288 21 298 140 127 114 99 84 71 54 37 297 16 31 287 292 HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK# PEN# PM0 / BP0 293 311 4 34 193 192 197 15 13 303 22 8 199 300 316 191 30 Clock Control STPCLK# 181 PM1 / BP1 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# W / R# WB / WT# 29 318 299 198 270 273 196 319 161 163 162 164 167 289 5
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) Vcc 1 2 6 11 17 19 23 27 33 35 41 43 49 51 57 59 65 67 73 79 85 91 97 103 109 111 117 123 129 135 141 147 153 157 160 165 168 170 172 174 177 178 180 183 188 Vss 3 7 12 18 20 24 26 32 36 42 44 50 52 58 60 66 68 74 80 86 92 98 104 110 112 118 124 130 136 142 148 154 159 166 169 171 173 176 179 182 187 189 194 203 NC 175 184 185 271 209 215 218 220 224 229 233 235 239 244 246 250 252 256 261 263 267 269 274 280 290 294 302 305 307 310 314 320 190 195 204 210 216 217 221 225 226 230 232 236 240 241 243 247 249 253 257 258 260 264 266 268 275 281 291 295 301 304 306 309 313 317
3.2. Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to Vcc. Unused active HIGH inputs should be connected to GND (Vss).
No Connect (NC) pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings.
3.3. Quick Pin Reference
Note that all input pins must meet their AC / DC specifications to guarantee proper functional behavior. The # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage. When a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level.
A31-A3
ADS# AHOLD
APCHK#
APICEN PICD1
BE7#-BE5# BE4#-BE0#
BOFF#
BP3:2 PM / BP1:0
BUSCHK#
CACHE#
D63-D0
DP7-DP0
DPEN# PICD0
EADS# EWBE#
FERR#
HITM#
IERR#
IGNNE#
LINT0 / INTR LINT1 / NMI LOCK#
NMI / LINT1
PCHK#
PICCLK
PICD0-1 DPEN# APICEN PM / BP1:0
RESET
SMIACT# STPCLK#
TMS TRST#
3.4. Pin Reference Tables
Table 4. Output Pins Name ADS# APCHK# BE7#-BE5# BREQ CACHE# FERR# HIT# HITM# HLDA IERR# LOCK# M / IO#, D / C#, W / R# PCHK# BP3-2, PM1 / BP1, PM0 / BP0 PRDY PWT, PCD SCYC SMIACT# TDO Low Low Low High Low Low Low Low High Low Low n / a Low High High High High Low n / a All states except Shift-DR and Shift-IR Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Active Level When Floated Bus Hold, BOFF#
NOTE: All output and input / output pins are floated during tristate test mode (except TDO).
Table 5. Input Pins Name A20M# AHOLD BF BOFF# BRDY# BUSCHK# CLK EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR INV KEN# NA# NMI PEN# PICCLK R / S# RESET SMI# STPCLK# TCK TDI TMS TRST# WB / WT# Active Level Low High High Low Low Low n / a Low Low Low High Low High High High Low Low High Low High n / a High Low Low n / a n / a n / a Low n / a Synchronous / TCK Synchronous / TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY# / NA# TCK TCK Pullup Pullup BRDY# EADS# First BRDY# / NA# Bus State T2, TD, T2P BRDY# Synchronous / Asynchronous Asynchronous Synchronous Synchronous / RESET Synchronous Synchronous Synchronous Pullup Bus State T2, T12, T2P BRDY# Pullup Internal resistor Qualified
Table 6. Input / Output Pins Name A31-A3 AP BE4#-BE0# D63-D0 DP7-DP0 PICD0DPEN# PICD1APICEN
NOTES: All output and input / output pins are floated during tristate test mode (except TDO). BE3#-BE0# have pulldowns during RESET only.
When Floated Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF#
Qualified (when an input) EADS# EADS# RESET BRDY# BRDY#
Internal Resistor
Pulldown
Pullup Pulldown
3.5. Pin Grouping According to Function
Table 7 organizes the pins with respect to their function. Table 7. Pin Functional Grouping Function Clock Initialization Address Bus Address Mask Data Bus Address Parity APIC Support Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping / Consistency Cache Flush Write Ordering Bus Arbitration Interrupts Floating Point Error Reporting System Management Mode TAP Port Breakpoint / Performance Monitoring Clock Control Probe Mode CLK RESET, INIT A31-A3, BE7# - BE0# A20M# D63-D0 AP, APCHK# PICCLK, PICD0-1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, NA# PCD, PWT KEN#, WB / WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0 / BP0, PM1 / BP1, BP3-2 STPCLK# R / S#, PRDY Pins
WARNING Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
4.2. DC Specifications
Table 9. 3.3V (5V Safe) DC Specifications Symbol VIL5 VIH5 Parameter Input Low Voltage Input High Voltage Min -0.3 2.0 Max 0.8 5.55 Unit V V Notes TTL Level (1) TTL Level (1)
NOTES: 1. Applies to CLK and PICCLK only.
NOTES: 1. This parameter is for input without pull up or pull down. 2. This parameter is for input with pull up. 3. This parameter is for input with pull down. 4. Guaranteed by design.
Table 11. Power Dissipation Requirements for Thermal Solution Design Parameter Active Power Dissipation Stop Grant and Auto Halt Powerdown Power Dissipation Stop Clock Power Dissipation .02 Typical (1) 3-4 8.0 1.2 .05 Max(2) Unit Watts Watts Watts Notes @ 75 MHz @ 75 MHz (3) (4) (5)
4.3. AC Specifications
All NC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to Vcc. Unused active high inputs should be connected to ground.
t6b t6c
t8 t9a t10a t10b t11a t11b t12 t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t22a t23
t43a t43b t43c t43d t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55
mS CLKs CLKs CLKs MHz nS nS nS nS nS nS nS nS nS nS nS
3 3 3 3 3 9 8 8 8 8 8 @2V, (1) @0.8V, (1) (2.0V- 0.8V), (1), (8), (9) (0.8V- 2.0V), (1), (8), (9) (1), Asynchronous (7) (7) (8) (1), (8) (3), (8), (10)
APIC AC Specifications t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Low Time PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay (LtoH) PICD0-1 Valid Delay (HtoL) 2.0 60.0 9.0 9.0 1.0 1.0 3.0 2.5 4.0 4.0 38.0 22.0 5.0 5.0 16.66 500.0 MHz nS nS nS nS nS nS nS nS nS 3 3 3 3 3 6 6 4 4 to PICCLK to PICCLK from PICCLK, (22) from PICCLK, (22)
These signals are measured on the rising edge of adjacent CLKs at 1.5V. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 KHz and 1 / 3 of the CLK operating frequency. The amount of jitter present must be accounted for as a component of CLK skew between devices. 20. Timing t14 is required for external snooping (e.g., address setup to the CLK in which EADS# is sampled active). 21. BUSCHK# is used as a reset configuration signal to select buffer size. 22. This assumes an external pullup resistor to V cc and a lumped capacitive load. The pullup resistor must be between 150 ohms and 1K ohms, the capacitance must be between 20 pF and 240 pF, and the RC product must be between 3 ns and 36 ns. Each valid delay is specified for a 0 pF load. The system designer should use I / O buffer modeling to account for signal flight time delays. 19.
Figure 3. Clock Waveform
Figure 4. Valid Delay Timings
Figure 5. Float Delay Timings
Figure 6. Setup and Hold Timings
Figure 7. Reset and Configuration Timings
Figure 8. Test Timings
Figure 9. Test Reset Timings
4.4. I / O Buffer Models
Figure 10. Input Buffer Model, Except Special Group
Figure 11. Input Buffer Model for Special Group
Table 13. Parameters Used in the Specification of the First Order Input Buffer Model Parameter Cin Lp Cp Rs D1, D2 Description Minimum and Maximum value of the capacitance of the input buffer model. Minimum and Maximum value of the package inductance. Minimum and Maximum value of the package capacitance. Diode Series Resistance Ideal Diodes
Figure 12. First Order Output Buffer Model Table 14. Parameters Used in the Specification of the First Order Output Buffer Model Parameter dV / dt Ro Co Lp Cp Description Minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model. Minimum and maximum value of the output impedance of the output buffer model. Minimum and Maximum value of the capacitance of the output buffer model. Minimum and Maximum value of the package inductance. Minimum and Maximum value of the package capacitance.
In addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. These diodes have been optimized to provide ESD protection and provide some level of clamping. Although the diodes are not required for simulation, it may be more difficult to meet specifications without them.
Note, however, some signal quality specifications require that the diodes be removed from the input model. The series resistors (Rs) are a part of the diode model. Remove these when removing the diodes from the input model.
4.4.1. BUFFER MODEL PARAMETERS configurable output buffer EB2. Table 15 shows the drive level for BRDY# required at the falling edge of RESET to select the buffer strength. The buffer sizes selected should be the appropriate size required otherwise AC timings might not be met, or too much overshoot and ringback may occur. There are no other selection choices all of the configurable buffers get set to the same size at the same time.
Table 15. Buffer Selection Chart Environment Typical Stand Alone Component Loaded Component 1 0 BRDY# EB2 EB2A Buffer Selection
Please refer to Table 16 for the groupings of the buffers. Table 16. Signal to Buffer Type Signals CLK A20M#, AHOLD, BF, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, PICCLK, R / S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB / WT# APCHK#, BE7:5#, BP3:2, BREQ, FERR#, IERR#, PCD, PCHK#, PM0 / BP0, PM1 / BP1, PRDY, PWT, SMIACT#, TDO, U / O# A31:21, AP, BE4:0#, CACHE#, D / C#, D63:0, DP8:0, HLDA, LOCK#, M / IO#, SCYC A20:3, ADS#, HITM#, W / R# HIT# PID0, PICD1 The input, output and bidirectional buffer values are listed in Table 17. This table contains listings for all three types, do not get them confused during simulation. When a bidirectional pin is operating as Type I I Driver Buffer Type Receiver Buffer Type ER0 ER1
EB1 EB2A EB3 EB4
EB1 EB2 EB3 EB4
an input, just use the Cin, Cp and Lp values if it is operating as a driver, use all of the data parameters.
Table 17. Input, Output and Bidirectional Buffer Model Parameters Buffer Type Transition min ER0 (input) ER1 (input) ED1 Rising Falling Rising Falling Rising 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 2.4 3 / 2.4 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.9 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 21.6 17.5 21.6 17.5 21.6 17.5 10.1 9.0 21.6 17.5 21.6 17.5 53.1 50.7 53.1 50.7 53.1 50.7 22.4 21.2 53.1 50.7 53.1 50.7 dV / dt (V / nsec) max Ro (Ohms) min max min 0.3 0.3 0.2 0.2 0.3 0.3 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.3 0.3 Cp (pF) max 0.4 0.4 0.5 0.5 0.6 0.6 0.5 0.5 0.5 0.5 0.5 0.5 0.4 0.4 0.4 0.4 min 3.9 3.9 3.1 3.1 3.7 3.7 2.9 2.9 3.1 3.1 3.1 3.1 3.2 3.2 4.0 4.0 Lp (nH) max 5.0 5.0 6.0 6.0 6.6 6.6 6.1 6.1 6.4 6.4 6.4 6.4 4.1 4.1 4.1 4.1 Co / Cin (pF) min 0.8 0.8 0.8 0.8 2.0 2.0 2.0 2.0 9.1 9.1 9.1 9.1 3.3 3.3 5.0 5.0 max 1.2 1.2 1.2 1.2 2.6 2.6 2.6 2.6 9.7 9.7 9.7 9.7 3.9 3.9 7.0 7.0
(output) Falling EB1 (bidir) EB2 (bidir) EB2A (bidir) EB3 (bidir) EB4 (bidir) Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling
Table 18. Input Buffer Model Parameters: D (Diodes) Symbol IS N RS TT VJ CJ0 M Parameter Saturation Current Emission Coefficient Series Resistance Transit Time PN Potential Zero Bias PN Capacitance PN Grading Coefficient 1.4e-14A 1.19 6.5 ohms 3 ns 0.983V 0.281 pF 0.385 D1 D2 2.78e-16A 1.00 6.5 ohms 6 ns 0.967V 0.365 pF 0.376
SIGNAL QUALITY SPECIFICATIONS
read data properly and to ensure that incoming signals do not affect the reliability of the component. There are two signal quality parameters: Ringback and Settling Time. 37
Figure 13. Overshoot / Undershoot and Ringback Guidelines 4.4.2.2. Settling Time The settling time is defined as the time a signal requires at the receiver to settle within 10 percent of Vcc or Vss. Settling time is the maximum time allowed for a signal to reach within 10 percent of its final value. Most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. On a physical board, 38 second-order effects and other effects serve to dampen the signal at the receiver. Because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. Settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. Settling time
Figure 14. Settling Time
5.1. TCP Package Mechanical Diagrams
Polyimide Support Ring Polyimide Keeper Bar
Encapsulant Gold Bump
TAB Lead (OFC Copper)
Die PCB 1 / 2 X-Section Thermally & Electrically Conductive Adhesive (Silver Filled Thermoplastic) Thermal vias Ground plane Note: Sketches Not to Scale
PCB Full X-Section
Figure 15. Cross-Sectional View of the Mounted TCP Package
Figure 16. One TCP Site in Carrier (Bottom View of Die)
Figure 17. One TCP Site in Carrier (Top View of Die)
Figure 18. One TCP Site (Cross-Sectional Detail)
Figure 19. Outer Lead Bond (OLB) Window Detail
NOTES: Dimensions are in millimeters unless otherwise noted. Dimensions in parentheses are for reference only.
Table 20. Mounted TCP Package Dimensions Description Package Height Terminal Dimension Package Weight 0.75 max. 29.5 nom. 0.5 g max. Dimension
NOTE: Dimensions are in millimeters unless otherwise noted. Package terminal dimension (lead tip-to-lead tip) assumes the use of a keeper bar.
where,
6.1. Measuring Thermal Values
P (maximum power consumption) is specified in section 4.2.
6.3. TCP Thermal Characteristics
The primary heat transfer path from the die of the Tape Carrier Package (TCP) is through the back side of the die and into the PC board. There are two thermal paths traveling from the PC board to the ambient air. One is the spread of heat within the board and the dissipation of heat by the board to the ambient air. The other is the transfer of heat through the board and to the opposite side where thermal enhancements (e.g., heat sinks, pipes) are attached. To prevent the possibility of damaging the TCP component, the thermal enhancements should be attached to the opposite side of the TCP site - not directly mounted to the package surface.
6.4. PC Board Enhancements
Copper planes, thermal pads, and vias are design options that can be used to improve heat transfer from the PC board to the ambient air. Tables 21 and 22 present thermal resistance data for copper plane thickness and via effects. It should be noted that although thicker copper planes will reduce the ca of a system without any thermal enhancements, they have less effect on the ca of a system with thermal enhancements. However, placing vias under the die will reduce the ca of a system with and without thermal enhancements.
Figure 20. Technique for Measuring Case Temperature (T C)
6.2. Thermal Equations
Table 22. Thermal Resistance vs. Thermal Vias underneath the Die No. of Vias Under the Die 0 144 15 13 CA (° C / W) No Enhancements
NOTE: 3 oz. copper planes in test boards
STANDARD TEST BOARD CONFIGURATION
Al Plate with Heat Pipe