Full system management solution with environmental instrumentation int

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Alert LAN* ASIC
Full system management solution with environmental instrumentation interface host Multiple transmissions packets Five External maskable events Automatic heartbeat generation when system powered-off
Watchdog timer detection system hang Power plane signal detection power state status Clock synchronization smooth transition logic 82558 B-step Fast Ethernet** controller compliance only
EVENT INTERFACE SYNC EVENT TIMERS REGISTERS DATA PACKET CONTROL MISCELLANEOUS LOGIC DECODE EEPROM INTERFACE
INTERFACE
BYTE SYNC
INTERFACE
Figure Alert ASIC Block Diagram
Order Number: 692818-003 Version July 1998
Alert LAN* ASIC
Revision History
Revision Date Oct. 1997 Feb. 1998 July 1998 Version Description First release General editing Expanded Section 2.4, "Event Interface" include more detail added Section 5.0, "Reset Test Modes"
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Alert LAN* ASIC contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copyright Intel Corporation, 1997 Alert result Intel-IBM Advanced Manageability Alliance trademark IBM. **Third-party brands names property their respective owners.
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Contents
INTRODUCTION Alert Overview Management Overview Alert Feature Specifications Standards Compliance
ALERT ASIC ARCHITECTURAL OVERVIEW Interface Interface. EEPROM Interface Event Interface 2.4.1 Event Definition Results 2.4.2 External Events 2.4.3 Event Sticky Latch Clearing Mechanism 2.4.4 Event Link Detect Packet Transmission Interrupt. 2.4.5 Watchdog Event 2.4.6 Software Event 2.4.7 Polarity Functionality 2.4.8 Event Status Mask Mask 2.4.9 Event Packet Transmissions Event Timers Synchronous Packet Control Clock Synchronization Logic Logic Miscellaneous Logic
SIGNAL DESCRIPTION Signal Type Definition Clock Signals Interface Signals 82558 B-step Flash Interface Signals EEPROM Interface Signals Alert/SOS Events Signals Miscellaneous Signals Power Ground Signals
CONFIGURATION STATUS REGISTERS 4.10 4.11 4.12 Register Types Register Revision Register Event Status. Register Event Polarity Register Event Mask Register Mask Register Watchdog Status Byte Register Watchdog Timer. Register Heartbeat Timer Register Retransmission Timer Register Control Register Software Status Byte
Alert LAN* ASIC
Contents
4.13 4.14 4.15 Register Software Status Byte Register EEPROM Access Register Test Mode
RESET TEST MODES Reset Mode Manufacturing Test Mode. 5.2.1 NAND Tree. 5.2.2 Tri-State. Vector Test Mode 5.3.1 Vector Input Interface 5.3.2 Vector Output Interface
ELECTRICAL SPECIFICATIONS Recommended Operation Conditions Absolute Maximum Ratings Characteristics
PACKAGING INFORMATION APPENDIX ALERT SUPPORTING HARDWARE
Networking Silicon Alert LAN* ASIC
Introduction
Alert ASIC intended provide system manageability function desktop platform when used conjunction with Intel 82558 B-step (82558B) Fast Ethernet Controller. Together, these integrated circuits (ICs) provide management interface between remote management console server client system. Additional hardware required provide Alert ASIC with system monitoring instrumentation (for example, over-voltage overtemperature indications). Alert ASIC stand alone device requires 82558B, 64x16 EEPROM, environmental ICs, support software create functional management solution. more detailed description EEPROM environmental other external components found Section 8.0, "Appendix Alert Supporting Hardware" page
Alert Overview
primary function Alert ASIC provide transmit stream 82558B, which transmits alert ("SOS") packets heartbeat ("presence") packets. Alert ASIC responsible transmitting these packets when software unable (for example, during power state system failure). Alert ASIC communicates system through System Management (SMB), which subset Phillips I2C** interface. typically connects PCI-to-ISA/ Xcelerator (PIIX4), which accessible system through Basic Input/Output System (BIOS). Communication between Alert ASIC 82558B through 8-bit wide parallel data interface plus supporting control signals. Alert ASIC uses this interface transfer data transmission packets, alert heartbeat, 82558B. Alert ASIC transfers packets either internal external events. External events detected through five dedicated pins Alert ASIC; internal events generated either timers support software. Alert ASIC contains configuration registers enable disable events store packet information. Since packets must Internet Protocol (IP) routeable, packet headers stored Alert ASIC. Alert ASIC does have resources necessary create correct packets relies supporting software stack supply with appropriate information. external EEPROM used provide default configuration information Alert ASIC. also provides only method loading packet structure header into Alert ASIC. This allows Alert ASIC power-up into configured state without need software configuration.
Management Overview
Alert ASIC/82558B management solution intended provide system management capabilities including (but limited to):
Alert LAN* ASIC
(alert) events
Transmit packets from preboot, State (working), State (sleeping), State (soft-off) Transmit sender identification messages hardware events Chassis intrusion Voltage specification Temperature specification leash tamper Processor missing
software events lockup/system hang Failure boot BIOS/System Management Interrupt (SMI) generated exception message Desktop Management Interface (DMI)/management agent generated exception message
Presence heartbeat with status information
Alert Feature
Alert ASIC includes following features:
Full system management solution with environmental instrumentation 82558 B-step controller compliance only interface host Multiple transmissions packets Five external maskable events Automatic heartbeat generation when system sleep shutdown modes Watchdog timer detecting system hang Power plane signal detection power state status Clock synchronization smooth transition logic
Specifications Standards Compliance
Advanced Configuration Power Interface Specification (ACPI), Revision Intel System Management (SMB) Specification, Revision
Networking Silicon Alert LAN* ASIC
Alert ASIC Architectural Overview
internal architecture Alert ASIC shown Figure "Alert ASIC Block Diagram" front cover.
Interface
interface proprietary General Purpose Input/Output (GPIO) type interface 82558B. 8-bit parallel data interface along with several control signals. This interface unidirectional data bus. Data only transmitted from Alert ASIC 82558B. Read Request (TRDREQ) Active (TACTIVE) signals provide handshaking mechanism that allows GPIO type interface. Marker (TMARKER) signal that indicates whether data command byte data byte. used delineate datagrams data bus. only command that Alert ASIC uses Transmit command. format Transmit command Marker (TMARKER) Data (TDATA[7:0]) lines 82558B shown below.
TMARKER TDATA[7:0] Data Byte Data Byte Data Byte Data Byte
Additional signals used 82558B mode. Force (TFORCE) signal active high input that forces 82558B into mode. TFORCE also used transaction. TFORCE will forced inactive when following conditions occur:
Both Reset signal (PCI_RST#) Main Power Good signal (PWR_GOOD)
active.
82558 Software Reset (CTL_558RST) Control register (Section 4.11,
"Register Control" page 22).
Transmit Enable (CTL_TXEN) Control register cleared (Section 4.11,
"Register Control" page 22).
Ready Active (CTL_TRDY) Control register (Section 4.11, "Register
Control" page Ready (TREADY#) signal inactive.
Alert LAN* ASIC
Alert Software Reset (TST_RST) Test Mode register (Section
4.15, "Register Test Mode" page 23). transaction aborted above mechanisms, except TST_RST bit, Alert ASIC will retry transaction start transaction with prior status information when condition that caused abort longer exists. Status (TSTATUS#) signal pulse that indicates that 82558B completely processed command. case Transmit command, this signal indicates that packet been sent wire been aborted transmission errors. This signal indicates Alert ASIC that TFORCE signal should de-asserted until cycle. basic flow cycle Alert ASIC samples TACTIVE pin, which should prior cycle. sampled low, ASIC asserts TFORCE 82558B. Alert ASIC asserts TRDREQ transfers byte command byte) TMARKER 82558B least clock cycles after TFORCE asserted. 82558B asserts TACTIVE upon completion sampling data. Alert ASIC samples TACTIVE high de-asserts TRDREQ. After data read 82558B TRDREQ de-asserted, 82558B de-asserts TACTIVE. Alert ASIC repeats steps through five bytes frame with TMARKER inactive data bytes. After Alert ASIC completed transferring whole frame, de-asserts TFORCE pin. following diagram illustrates timing Alert ASIC.
Figure Timing Diagram
Networking Silicon Alert LAN* ASIC
Interface
interface slave-only interface. Since Alert ASIC completely under software control provides interrupts output signal (SMI#), alert signal supported. address ASIC responds determined reset time. After EEPROM load completed (due hardware software reset Main Power Good signal transition low), TDATA[2:0] internally latched inputs during EEPROM load reset. TDATA[2:0] lines multiplexed with address lines through (SMB_A[2:0]). value these input pins, SMB_A[2:0], used create address 0101XXXb, where represents SMB_A2, SMB_A1, SMB_A0, respectively. These inputs configured using pull-up pull-down resistors. There default pull-up pull-down resistors silicon select 110b SMB_A[2:0]. However, internal pull-up resistors device address weak; therefore, ones address lines require strong, external pull-up resistor (for example, value Resistor values tolerances described Section 6.0, "Electrical Specifications" page More details found Intel System Management Specification, Revision 1.0. register accesses Alert ASIC, simple commands supported: Write Byte command Read Byte command. command field used access individual registers. Explicit details cycles definitions described Section 4.0, "Configuration Status Registers" page interface configured drive Data Input/Output Serial Clock pins when Main Power Good signal equals using Drive Control register. This method preventing open drain from floating when other connections have been powered-off. After reset, interface will driven Main Power Good signal equals until Control register read. this point, function will depend configuration bit. requires approximately microseconds from reset read Drive Control register.
Note:
EEPROM Interface
Alert ASIC requires 64x16 EEPROM which separate from 82558B's EEPROM. EEPROM interface provided allow default configuration information. This gives Alert ASIC default power-up state enabled disabled events, packet information, Individual Address, other configuration data. Alert ASIC reads information from EEPROM during following:
Hardware Reset. This happens when Alert ASIC first powered-up when
Auxiliary Power Good (AUX_GOOD) signal transitions low. Alert ASIC begins loading EEPROM configuration information soon reset de-asserted.
Software Reset. This accomplished writing Test Mode register
SMB. After reset completed, Alert ASIC begins reading EEPROM.
Hard Transition Power State. hard transition power state occurs when
system powered down before software notifies Alert ASIC transition
Alert LAN* ASIC
setting ACPI State Indicator Control register equal 10b, where value indicates that system power state. This typically occurs when system powered down using 4-second power switch. Loading EEPROM this time guarantees that Alert ASIC placed known state since sudden power loss occurred without software knowledge. Alert ASIC reads first words (124 bytes) data EEPROM leaves last words bytes) free vendor information. ensure that EEPROM contains valid data, Alert ASIC uses word checksum. checksum 16-bit value that causes ASIC's data checksum other words, words through 3Dh) equal BABAh. checksum invalid, ASIC resets most registers reset value prevent from entering unpredictable state invalid EEPROM data. reset values registers such that packet transmissions events disabled until EEPROM loaded. writes should also prevented software during EEPROM load. reads always permitted should used check EEPROM Read Complete Indication EEPROM Access register (Section 4.14, "Register EEPROM Access" page determine when EEPROM load completed. EEPROM interface MicroWire** interface that uses control signals: EEPROM Chip Select (EECS), EEPROM Serial Clock (EESK), EEPROM Data Input (EEDI) EEPROM Data Output (EEDO). More details MicroWire interface found MicroWire EEPROM datasheet. GPIO interface provided access EEPROM from software. This allows each EEPROM controlled through register interface. This only method which EEPROM programmed.
2.4.1
Event Interface
Event Definition Results
There components event interface. first portion occurrence event. event occurrence happens time event caused: event active level, software event write, Watchdog Timer expires. EEPROM does load, each these events will Event Status register when they happen. second part event interface event. term event refers event occurrence that initiates packet generated transmitted, regardless whether packet currently being transmitted not. event occurs whenever following happens:
Event Status register changes from inactive active Event Mask register
already enabled this event. This occurs time unmasked event becomes active status previously either because event happened before because software cleared
Event Status register already particular event, Event Mask changed
from inactive active. Since event that occurs stored Event Status register, event does have currently active order produce event.
Software Event, event occurs whenever software writes Software Event
Status Event Status register.
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above considered events because they initiate packet transmission interrupt current transmissions. Section 2.4.9, "New Event Packet Transmissions" page describes event occurrences more detail. Note: heartbeat does cause event. Although initiate packet, does interrupt current packet transmissions. does initiate packet, Quantum field will incremented that packet. heartbeat occurs within event packet transmission window (three packets including time period between three packets), current heartbeat will ignored. other reason that heartbeat event because only causes single packet transmitted, rather than three.
2.4.2
External Events
external events level inputs that cause alert packets sent Alert ASIC. active level (polarity) signals configurable through Polarity register, which written EEPROM writes. Each hardware event latched Event Status register after occurred, regardless Event Mask Mask registers. clear event SMI, enabled, must written appropriate status register bit. Event Mask register selects events that cause alert packet transmission well masking status bits into packet payload. Mask register selects events that cause event. Both these registers loaded EEPROM configurable through interface. Every time event activated, Alert ASIC sends alert soon possible (the 82558B invoke wait states). same time, retransmission timer starts. expiration this timer, second identical packet sent followed third packet after same timer interval. Whenever event activated, this sequence begins again. ASIC does continually send alert packets while level input active. This helps reduce amount redundant management network-generated traffic. Alert packets always take priority over heartbeat packets. event occurs, three alert packets sent along with retransmission delays before another heartbeat packet sent. Retransmission Timer starts when packet queued transmitted. packet been transmitted time retransmission timer expired, next packet will transmitted. This highly unlikely occur; however, possible 82558B delays transmission packet. Possible delays include EEPROM read collision back-off. There five separate external level events: Cover Tamper. This indicates that cover been opened tampered with. Environmental SMI. This indicates that environmental control generated event. Temperature. This indicates that environmental control generated event. Leash. This indicates that lost link. This event signal uses different interface than other events. enabled, detection link that been down five seconds generates event; however, Alert ASIC does transmit unless link currently valid. Processor Missing. This indicates that processor installed. Although these events defined, they used event long corresponding software function properly.
Alert LAN* ASIC
2.4.3
Event Sticky Latch Clearing Mechanism
Event_1 input signal Alert ASIC designed work with event that stored sticky latch. This event configured clear sticky latch driving opposite polarity Event_1 pin. configured, this will occur when Event Status register Event_1 cleared writing this bit. Alert ASIC will drive Event_1 signal minimum allowing plenty time sticky latch clear. Section 8.0, "Appendix Alert Supporting Hardware" page describes sticky latch more detail. With exception sticky latch clearing mechanism, Event input behaves similar other events. enable clearing mechanism Event input, POL_CLREV1 Polarity register must set. desired sticky latch Event clearing mechanism disabled clearing POL_CLEV1 bit.
2.4.4
Event Link Detect Packet Transmission Interrupt
Event input designed with Link status output from 82558B. There special enable functions available with this event. First method detecting lost link. configured, Alert ASIC will only cause Event Event Status register detects inactive link (based polarity setting) consecutive timer ticks separated seconds. window time that event will detect link loss between through 10.8 seconds since "tick time" "link loss" events synchronous each other. This feature required prevent events resets 82558B resets, which should produce invalid link approximately seconds. second feature Event_4 input signal ability cancel disable packet transmissions across interface whenever Event_4 active. active event Event_4 indicates that link down, which will obviously prevent packet transmission network, even though transaction successful. packet currently being transmitted will interrupted retransmission will occur when link returns. above features cause Event_4 input cause Alert ASIC behave differently than would other events. order activate these features, POL_LNKEV4 Polarity register must set. desired these features, this must disabled. Since link always lost when power completely state), this event preset Event Status register, causing event Event Mask appropriately) when Alert ASIC powered Note: software reset will preset clear this bit. this feature desired, then Event_4 Status cleared before mask enabled.
2.4.5
Watchdog Event
Watchdog event similar other events, except that caused internal timer expiring. Watchdog event used notify network console when monitored machine hangs during boot-up. example, timer enabled upon initial power-up. system reaches specified point during boot-up, BIOS disable Watchdog Timer, preventing Watchdog event. system hangs before this point boot-up reached, Watchdog Timer will time-out notify network console.
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Since hard transition happen without software knowledge, important disable watchdog events during This done temporarily disabling watchdog enable while PWR_GOOD signal equals This disables Watchdog Timer during hard transition occurs, EEPROM load will reload Watchdog Timer possibly enabled. point that PWR_GOOD signal transitions high, Watchdog Timer becomes enabled configured enabled) starts counting from initial loaded value, essentially restarting boot-up time-out timer.
2.4.6
Software Event
software event also unique functionality special purpose. event status when written Software Status Event Event Status register. After three packets have been transmitted successfully, this cleared Event Status register. However, write time this will cause event cause ASIC start transmitting series event packets with current software information. Software detect which packet progress monitoring CTL_RTCNT bits Control Register.
2.4.7
Polarity Functionality
external events, Event Polarity register informs Alert ASIC whether particular event active high low. bits Event Polarity register enable special features available Events (described above).
2.4.8
Event Status Mask Mask
Event Mask register selects events that cause packet transmission well masking status bits into packet payload. Mask selects events that will cause SMI. Both these registers loaded EEPROM configurable through interface. While EEPROM being read, events will observed Alert ASIC, regardless either mask settings. After EEPROM finished loading, Alert ASIC allows events enter into status register, subsequently causing packet sent output asserted depending setting mask registers.
2.4.9
Event Packet Transmissions
Every time event occurs, following sequence events will performed: current packet transmission will aborted. Quantum counter will increment. CTL_RTCNT counter value will reset 11b. Retransmission Timer will reloaded. Data latched internal Alert ASIC packet creation: High byte Quantum counter byte Quantum counter Masked Event Status register Control register (since latched, packets will show RTCNT equals 11b)
Alert LAN* ASIC
High byte Software register byte Software register Watchdog data checksum word will incrementally calculated based data above written appropriate checksum location. Assuming that packet sent (CTL_TXEN set, EEPROM completed loading, 82558_RST active, TREADY# active CTL_TRDY clear, link valid POL_LNKEV4 clear), complete packet, internally latched, will transmitted 82558 bus. Once packet been successfully transmitted 82558B, CTL_RTCNT counter will decremented one. sequence 11b, 10b, 01b, 00b. When Retransmission timer expired, execution will begin step CTL_RTCNT counter value does equal 00b. CTL_RTCNT equals after previous packet been transmitted identical packets have been transmitted), then packet transmissions stop until next event heartbeat occurs. Since this process always restarted when event occurs, possible skip Quantum numbers network transmissions. example:
Event occurs causes packets with Quantum transmit. Event occurs starts transmitting packet with Quantum n+1. Event occurs middle packet from Event
This causes this packet transmission halt, packet started with Quantum n+2. Therefore, packet with Quantum never actually fully transmitted. Note: alerts will always take priority over heartbeat packets. event occurs, three packets will sent along with re-transmission delays before another heartbeat packet transmitted.
Event Timers
Event Timers consist clock divider circuit three timers within Alert ASIC: Heartbeat Timer. This timer controls heartbeat status packet frequency. Alert ASIC transmits packet heartbeat timer expiration. Watchdog Timer. This configurable timer used time-out critical events (for example, failed boot, POST failure, hang, etc.). Retransmission Timer. This timer controls frequency retransmission packets. Alert ASIC transmits alert packet three times. Watchdog Timer Event automatically masked hardware while Main Power Good signal equals This prevents Watchdog Timer from failing when system power lost. Watchdog Timer used only detect hang.
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Synchronous Packet Control
There 128-byte synchronous block inside Alert ASIC primarily used storing packet sent. contents EEPROM directly loaded into when EEPROM load occurs. packet control block responsible adding data dynamic packet data controlling block send each packet interface.
Clock Synchronization Logic
clock synchronization logic used provide smooth transition clocks 82558B. Since 82558B requires clock support power states, clock synchronization logic necessity. This logic ensures that transition between clock clock generated 82558B smooth non-glitching. This assures that 82558B continues operate known state. PCI_CK B25_CK 82558B output clocks, respectively. Alert ASIC must monitor both order provide smooth transition between both clocks. Both clocks required during power state transition other words, PWR_GOOD transitions low). after Main Power Good signal transitions least clocks required switch from clock 82558B's clock. PCI_SEL B25_SEL 82558B clock gates, respectively. These outputs control analog switches that turn clocks off. Note: analog switches used must selected carefully guarantee that clock skew specifications violated.
Logic
SMI# signal asserted (active low) Event Status Mask bits particular event, with exception software event. software event cannot used generate SMI. Since SMI# requires both Event Status mask event set, clearing these bits will de-assert SMI# signal only event causing SMI#. external event occurred mask set, SMI# signal will active. event cleared writing appropriate status bit, event will cleared Alert ASIC. However, event still active, will again Event Status register. result that SMI# line will pulse inactive single clock cycle. this undesired, software will need take steps avoid this. This achieved disabling mask ensuring that external event longer active. events happen independently jointly with packet transmission events since each Mask register.
Alert LAN* ASIC
Miscellaneous Logic
Alert ASIC block miscellaneous logic, consisting registers, reset circuitry, PWR_GOOD monitoring. power monitoring significant explained this section. Alert ASIC monitors input signals, PWR_GOOD AUX_GOOD, indicate status main power supply auxiliary power supply, respectively. These signals allow Alert ASIC determine state power supplies control 82558B appropriately. This enables Alert ASIC determine whether interface active. order guarantee that ALTRST# asserted before ISOLATE#, Alert ASIC provides combinational logic driven PWR_GOOD AUX_GOOD control ISOLATE# output. This important since 82558B will able propagate reset unless four clock cycles present while ALTRST# PCI_RST# active ISOLATE# inactive. Another main function Alert ASIC determine when power been lost attained main power plane. This allows Alert ASIC enable disable certain events necessary different power states. Alert ASIC monitors Main Power Good signal times designed detect when system been powered down with without software knowledge. When system powered down normally, software will ACPI state ACPI State Indicator bits Control register ACPI state (10b), anticipating power-down. From this state, Alert ASIC will continue operating normally system powered down (for example, Main Power Good signal transitions from high low). However, ACPI system state when Main Power Good signal transitions from high low, Alert ASIC will force re-read EEPROM load default values. This ensures that Alert ASIC will able operate known state, rather than unpredictable state software unaware power-down. PCI_RST# used input Alert ASIC stimulus reset 82558B with 82558_RST# signal. system with Alert management solution, undesirable reset 82558B while Main Power Good signal low. Alert ASIC only allows PCI_RST# assert 82558_RST# when Main Power Good signal This input also cause Alert ASIC terminate transactions with 82558B until continue later time. Alert ASIC offers software capability resetting 82558B through CTL_558RST Control register (Section 4.11, "Register Control" page 22). Main Power Good signal effect propagation PCI_RST# 82558_RST# important since PIIX4 will assert PCI_RST# when power being lost. However, PCI_RST# will reset 82558B which undesirable. Therefore, Alert ASIC uses Main Power Good signal determine PCI_RST# should propagated not. This assumes that Main Power Good signal de-asserted before PCI_RST#.
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Signal Description
Signal Type Definition
Symbol CMOS Input Totem Pole Output Input/Output Open Drain CMOS Input Buffer Input Buffer Schmitt-Trigger Input Pull-up Resistor Pull-down Resistor Name Input standard input. Totem pole output standard active driver. This signal used input output device. Open drain allows multiple devices share wired gate. Voltage detail CMOS Input Buffer described Section 6.3, Characteristics" page Voltage detail CMOS Input Buffer described Section 6.3, Characteristics" page This used Schmitt-Trigger Input. Pull-up resistance silicon present. Pull-down resistance silicon present. Output buffer drive milliamps, where integer value. Description
Clock Signals
Symbol PCI_CK Type CMOS CMOS Name Function Clock. This signal clock from interface. frequency range MHz. 82558 Generated Clock. This clock input provided 82558B. This clock expected operate times constant frequency, unless power Alert ASIC lost. PCI_CK Select. This asserted high (active) when PCI_CK enabled 82558B. B25_CK Select. This asserted high (active) when B25_CK enabled 82558B.
B25_CK
PCI_SEL B25_SEL
Interface Signals
Symbol Type I/O, TTL, Name Function Serial Clock. This clock signal provided system order communicate over SMB. This used output when driven during reset while PWR_GOOD equal enabled (Drive Control register). Otherwise, SMB_SCL signal used input.
SMB_SCL
Alert LAN* ASIC
Symbol
Type I/O, TTL,
Name Function Data Input/Output. This data signal used transfer data over SMB. used output when driven during reset while PWR_GOOD equal enabled (drive Control register). Otherwise, SMB_SDA signal used input output data.
SMB_SDA
82558 B-step Flash Interface Signals
Symbol TDATA7
(TEST_EN)
Type I/O, CMOS, I/O, CMOS,
Name Function Data [7]. During reset (AUX_GOOD 0b), this acts Test Enable (TEST_EN) input. rising edge reset, test enable latched active. high value causes test mode enabled. Otherwise, TDATA7 used data bus. Data [6]. During reset (AUX_GOOD 0b), this acts TEST_MODE input. rising edge reset, test mode latched active. Otherwise, TDATA6 used data bus. Data [5:3]. data used transmit packets from Alert ASIC 82558B. This data only valid when TFORCE signal asserted. Data [2:0]. During reset EEPROM load, these pins inputs. EEPROM load, address latched TDATA[2:0] acts output SMB_A[2:0]. default address 110b internal pull-up pull-down resistors. Otherwise, TDATA[2:0] used data bus. Marker. marker strobe used indicate start command TDATA[7:0] bus. When TMARKER active, this indicates that TDATA contains command byte (not data byte). Read Request. When TRDREQ asserted (active high), indicates that Alert ASIC byte transferred 82558B. TRDREQ de-asserted upon acknowledgment from TACTIVE signal. Active. TACTIVE asserted 82558B indicate that 82558B acknowledged TRDREQ transaction (TFORCE that 82558B ready cycle (TFORCE 0b). Force. TFORCE control signal used force 82558B into mode. When 82558B forced into mode, TDATA[7:0] TMARKER interface 82558B activated. Status. TSTATUS# active input indicating that 82558B completed current command. This indication necessary mark packet transmission. Ready. Ready signal active input indicating power state 82558B. asserted, 82558B power state (D1, D3). This input indicates when Alert ASIC should de-assert TFORCE signal wake-up scenarios
TDATA6
(TEST_MODE)
TDATA5 TDATA4 TDATA3 TDATA2 TDATA1 TDATA0
(SMB_A[2:0])
I/O, CMOS,
TMARKER
TRDREQ
TACTIVE
CMOS
TFORCE
TSTATUS#
CMOS
TREADY#
CMOS
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EEPROM Interface Signals
Symbol EE_CS EE_SK EE_DO EE_DI Type TTL, Name Function EEPROM Chip Select. EEPROM Chip Select used control access EEPROM. EEPROM Shift Clock. EE_SK signal used shift data EEPROM. EEPROM Data Out. Serial data output from EEPROM. EEPROM Data Serial data input EEPROM.
Alert/SOS Events Signals
Symbol EVENT_1 Type I/O, TTL, TTL, TTL, TTL, TTL, Name Function Event_1 Cover Tamper. Level input that causes alert packet transmission. This used output clearing mechanism external sticky logic. Event_2 ENV_SMI. Level input that causes alert packet transmission. Event_3 BTI_Temperature. Level input that causes alert packet transmission. Event_4 LANLeash. Level input that causes alert packet transmission. Event_5 Processor Missing. Level input that causes alert packet transmission. This reserved should pulled down resistor.
EVENT_2 EVENT_3 EVENT_4 EVENT_5 Reserved
Miscellaneous Signals
Symbol Type Name Function Reset. PCI_RST# active input signal from interface. propagates 82558B through 82558_RST# line PWR_GOOD active. also used indication Alert ASIC that 82558B being reset. 82558 Reset. 82558 Reset signal active reset. driven when PCI_RST# signal active PWR_GOOD signal active. also driven when 82558B software reset triggered through internal registers. Isolate Output. This output signal used isolate 82558B. implements 82558B Wake LAN* (WOL) circuitry guarantee that ALTRST# signal 82558B asserted before ISOLATE# asserted. This based PWR_GOOD AUX_GOOD signals. Output. SMI# signal asserted Alert ASIC various events depending mask register settings. SMI# de-asserted clearing events masks Alert ASIC's status registers.
PCI_RST#
82558_RST#
ISOLATE#
SMI#
Alert LAN* ASIC
Power Ground Signals
Symbol PWR_GOOD Type TTL, Name Function Main Power Good. This signal indicates that main power supply available. Auxiliary Power Good. This signal indicates that auxiliary power supply available. also used active reset Alert ASIC. Power. Ground.
AUX_GOOD
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Configuration Status Registers
Alert ASIC configuration status registers accessible through SMB. cycles register reads writes shown below.
Read Byte:
Address XXXXRR Address RXByte
Write Byte:
Address XXXXRRRR Byte
Figure Register Read Write Cycle
Register Types
Symbol R/W1 EE(x) HWRST Read/Write Read Only Self Clearing Read/Write clear Default value from EEPROM with value EEPROM invalid Hardware Reset only (software reset effect) Description
Register Revision
Revision register identifies Alert ASIC silicon revision. intended provide software method accessing this information.
Bits Name AP_ID AP_REV Type Name Description Alert This register contains 11010b binary code identifying Alert ASIC. Alert Silicon Revision. This register contains three coded silicon revision. Default 11010b XXXb
Register Event Status
Event Status register holds status events. watchdog event events through five when event occurs remain until software clears them writing event status bit. Software Event, software causing event self-clears after three packet transmissions. However, writing Software Event always causes packet started, regardless many packets have been transmitted. software wants send only packet before causes Software Event, monitor packet retry counter Retransmission Count field (CTL_RTCNT) Control register. When STA_EV1
Alert LAN* ASIC
cleared writing Clear Sticky Latch Polarity (POL_CLREV1) Event Polarity register equals EVENT_1 outputs opposite Event Polarity register between milliseconds.
Bits Name Type Name Description Software Event Status. This software causes event. also forced writing this bit. Force Software Event This self-clears after three software event packet transmissions. Watchdog Event Status. This Watchdog Timer expired. Writing this clears Watchdog Timer expired Reserved This reserved should Event_5 Status. This indicates status Event Processor Missing. processor installed. Writing this clears Event_5 occurred Event_4 Status. This indicates status Event Leash. lost link. Writing this clears Event_4 occurred Event_3 Status. This indicates status Event Temperature. temperature specified range. Writing this clears Event_3 occurred Event_2 Status. This indicates status Event ENV_SMI. hardware monitoring device event. Writing this clears Event_2 occurred Event_1 Status. This indicates status Event Cover Tamper. cover been opened tampered with. Writing this clears Event_1 occurred
hardware reset causes this return default value software reset leaves this value unaffected.
Default
STA_SWE
STA_WDG
R/W1
STA_EV5
R/W1
STA_EV4
R/W1
STA_EV3
R/W1
STA_EV2
R/W1
STA_EV1
R/W1
Register Event Polarity
Event Polarity register used polarity event inputs. This flexibility allows Alert handle external interfaces that either active active high.
Bits Name POL_CLREV1 Type Name Description Clear Sticky Latch. This enables EVENT_1 drive clear sticky latch. This enabled when Link Status. This enables EVENT_4 link status input. When enabled, EVENT_4 status only latched event active five seconds, packet transmission valid only when link good. Default EE(0)
POL_LNKEV4
EE(0)
Networking Silicon Alert LAN* ASIC
Bits
Name Reserved POL_EV5 POL_EV4 POL_EV3 POL_EV2 POL_EV1
Type
Name Description This reserved should Event_5 Polarity. Active High Event_4 Polarity. Active High Event_3 Polarity. Active High Event_2 Polarity. Active High Event_1 Polarity. Active High Active Active Active Active Active
Default
EE(0) EE(0) EE(0) EE(0) EE(0)
Register Event Mask
Event Mask register used mask events from transmitting packets. event event will cause packet. will not. This mask also prevents event from showing status byte packet when
Bits Name Reserved MSK_WDG Reserved MSK_EV5 MSK_EV4 MSK_EV3 MSK_EV2 MSK_EV1 Type Name Description This reserved should Watchdog Event Mask. Watchdog Timer packet enabled This reserved should Event_5 Mask. Event_5 transmit packet enabled Event_4 Mask. Event_4 transmit packet enabled Event_3 Mask. Event_3 transmit packet enabled Event_2 Mask. Event_2 transmit packet enabled Event_1 Mask. Event_1 transmit packet enabled EE(0) EE(0) EE(0) EE(0) EE(0) EE(0) EE(0) Default
Note:
Watchdog event masked hardware when PWR_GOOD signal low.
Register Mask
Mask register used mask events from causing System Management Interrupt (SMI). event event will cause SMI. will not.
Bits Name Reserved SMI_WDG Reserved SMI_EV5 SMI_EV4 SMI_EV3 SMI_EV2 SMI_EV1 Type Name Description This reserved should Watchdog Event Mask. Watchdog Timer enabled This reserved should Event_5 Mask. Event_5 enabled Event_4 Mask. Event_4 enabled Event_3 Mask. Event_3 enabled Event_2 Mask. Event_2 enabled Event_1 Mask. Event_1 enabled EE(0) EE(0) EE(0) EE(0) EE(0) EE(0) Default
Alert LAN* ASIC
Register Watchdog Status Byte
Watchdog Status Byte register used provide more watchdog information packet recipient. provides means identifying cause watchdog event (such hang, failed boot, etc.). This byte transmitted with each packet. Note that some software implementations this byte additional information software event. This requires that watchdog event disabled (masked) during these transmissions since this byte designated watchdog data when watchdog event Event Status register.
Bits Name WDG_DAT Type Name Description Watchdog Status. This register byte-wide indicates status transmitted packets Watchdog Timer expiration. Default EE(40h)
Register Watchdog Timer
Watchdog Timer register used enable configure time-out value Watchdog Timer. watchdog time-out value only written when timer disabled. However, value written timer enabled single write. timer begins counting down from value received during write register. When timer reaches zero, event caused timer begins counting down again. write this register while enabled will reload time-out value. read from register will result current value timer.
Bits Name Type Name Description Watchdog Timer Value. This value loads 43-second resolution with range from seconds minutes. only written while timer disabled. This timer accuracy value minus tick, where tick equal seconds. WDG_ENA Timer Enable. Enable/Reset counter Disable counter EE(0) Default
WDG_VAL
EE(0000001b)
Note:
recommended time-out value 00h. Although event will caused immediately, will caused first incident timer loaded with nonzero value enabled with write.
Register Heartbeat Timer
Heartbeat Timer register used enable configure time-out value Heartbeat Timer. heartbeat time-out value only written when timer disabled. However, value written timer enabled single write.
Networking Silicon Alert LAN* ASIC
timer begins counting down from value received during write register. When timer reaches zero, heartbeat event caused timer begins counting down again. write this register while enabled reloads time-out value. read from register results current value timer.
Bits Name Type Name Description Heartbeat Timer Value. This value loads 43-second resolution with range from seconds minutes. only written while timer disabled. This timer accuracy value minus tick, where tick equal seconds. HBT_ENA Timer Enable. Enable/Reset counter Disable counter EE(0) Default
HBT_VAL
EE(0000001b)
Note:
recommended time-out value 00h. Although event will caused immediately, will caused first incident timer loaded with nonzero value enabled with write.
4.10
Register Retransmission Timer
Retransmission Timer register used configure time-out value Retransmission Timer. Retransmission Timer always enabled reloaded when event occurs. Unlike Watchdog Timer Heartbeat Timer, Retransmission Timer only reloads timeout value when expires event occurs, every time write done.
Bits Name Type Name Description Retransmit Timer Value. This value loads 2.7second resolution with range from seconds minutes. only written while timer disabled. This timer accuracy value minus tick, where tick equal seconds. RTM_RSVD This reserved should Default
RTM_VAL
EE(0000001b)
Note:
read from Retransmission Timer register results current time-out value, current timer value.
Alert LAN* ASIC
4.11
Register Control
Control register used provide miscellaneous control status functions. retransmission packet count, interface active indication, APCI states obtained from Control register. Also, 82558B reset, packet transmission enabled disabled, behavior TREADY# signal set, ACPI state changed through this register.
Bits Name Type Name Description Retransmission Count. These bits indicate which three Alert packet types currently being processed sent. CTL_RTCNT First packet Second packet Third packet packets CTL_TRDY TREADY# Active. When this set, TFORCE deasserted when TREADY# asserted high. Otherwise, TREADY# does affect TFORCE. 82558 Software Reset. Setting this causes hardware reset line asserted 82558B. value de-asserts reset. Drive SMB. Setting this causes Alert ASIC drive open drain interface while PWR_GOOD low. this interface operates normally expected, regardless PWR_GOOD. Transmit Enable. This enables real time control Alert ASIC transmission. When active (1b), transmission occurs normal; otherwise, when inactive (0b), transmission halts. ACPI State Indicator. Power State Power State CTL_ACPI Power State Preboot. ACPI state PWR_GOOD transitions from high low, EEPROM load will occur. Thus, this register reloaded. EE(11) EE(0) Default
CTL_558RST
EE(0)
CTL_DRSMB
EE(1)
CTL_TXEN
EE(0)
4.12
Register Software Status Byte
Software Byte register used provide detailed software information packet recipient. This byte provides method sending specific information from software transmitted with each packet. intended valid when Software Event Event Status register.
Bits Name SWS1_DAT Type Name Description These bits indicate status transmitted packets from Software Event. Default
Networking Silicon Alert LAN* ASIC
4.13
Register Software Status Byte
Software Byte register used provide detailed software information packet recipient. This byte provides method sending specific information from software transmitted with each packet. intended valid when Software Event Event Status register.
Bits Name SWS2_DAT Type Name Description These bits indicate status transmitted packets from Software Event. Default
4.14
Register EEPROM Access
EEPROM register used give EEPROM status allow access individual EEPROM pins. EEPROM read complete status invalid checksum status indicated this register. GPIO interface provided allow software access write directly EEPROM.
Bits Name EE_COMP Type Name Description EEPROM Read Complete Indication. This after configuration EEPROM read complete. EEPROM Invalid Checksum Indication. This should only read after EEPROM read been completed. Invalid checksum detected Reserved EE_DO EE_DI EE_CS EE_SK These bits reserved should 00b. EEDO Input State. This indicates EE_DO status. EEDI Output State. This sets EE_DI status. EECS Output State. This sets EE_CS status. EESK Output State. This sets EE_SK status. Default
EE_ICKSM
default value EE_ICKSM after reset. After valid data been detected, EE_ICKSM valid checksum detected.
4.15
Register Test Mode
Test Mode register used access internal test modes Alert ASIC force software reset ASIC.
Bits Name Type Name Description Alert Software Reset. This used reset Alert LAN. performs equivalent hardware reset re-reads EEPROM. This self-clears reset completes after four clock cycles. Test Mode. Test Mode enable provides access into Alert ASIC's Vector Test Mode coverage. Default
TST_RST
TST_MODE
Alert LAN* ASIC
Bits
Name TST_FRC25
Type
Name Description Force Clock. This forces clock switching mechanism select 82558B generated clock. Mode Active Indication. This active while Alert sending packet 82558B. Otherwise, this cleared. Fast Mode. Fast Mode enable provides quick test modes test vector coverage These bits reserved should 000b.
Default
TST_TCO
TST_FAST Reserved
000b
Networking Silicon Alert LAN* ASIC
Reset Test Modes
Reset Mode
When Alert ASIC's AUX_GOOD signal asserted (active low), internal circuits reset, except test mode circuitry. AUX_GOOD signal expected remain least B25_CLK cycles before completely reset stable. Reset signal (PCI_RST#) does reset Alert ASIC. However, passed through 82558 Reset signal (82558_RST#) when PWR_GOOD active. When PWR_GOOD de-asserted, 82558_RST# driven high (inactive).
Manufacturing Test Mode
Alert ASIC into Test Mode when TDATA7 (TEST_EN) signal, sampled high rising edge reset (AUX_GOOD 0b). Also, value TDATA6 (TEST_MODE) latched internal Alert ASIC. value this latched signal determines test mode that activated (while TEST_EN asserted). test modes supported are:
NANDTREE TRI-STATE
TDATA6 latched value TDATA6 latched value
test mode remains enabled until another reset occurs where TDATA7 sampled rising edge reset.
5.2.1
NAND Tree
This test mode provides NAND tree path around periphery Alert ASIC consisting Alert ASIC inputs stimuli. first input NAND tree PCI_RST#, output NAND tree ISOLATE#, NAND tree travels clockwise around chip (decreasing order), including every input buffer, with exception AUX_GOOD, B25_CLK, TDATA6 pins. AUX_GOOD cannot used part NAND tree because used reset, B25_CLK special input buffer that cannot NAND tree. During test mode, TDATA6 used required dedicated input process monitor. input buffers true buffers except PCI_CLK, which inverting input buffer. This should taken into consideration when implementing test vectors.
5.2.2
Tri-State
This test mode tri-states outputs Alert ASIC well disables internal pullup pull-down resistors.
Alert LAN* ASIC
Vector Test Mode
Alert ASIC into different test modes allowing easier access registers during testing. setting TST_MODE Test Mode register, Alert ASIC provides special parallel data interface easy input output. ASIC also into "fast" mode that internally configures Alert ASIC such that counters state machines free running. This done setting TST_FAST Test Mode register. These Vector Test Modes used provide method obtaining better faster test coverage internal nodes, helping facilitate higher yields achieve higher probability error-free devices ASIC manufacturing line. These modes recommended normal operation Alert ASIC. Note: Vector Test Mode mode will make Alert ASIC unusable intended operation. These special modes that only intended more efficient test vector coverage.
5.3.1
Vector Input Interface
input interface Vector Test Mode uses bits: bits data select between address phase data phase. There chip select, which means that address phase data phase will occur every rising edge Alert ASIC clock. 8-bit address/data signals used TREADY#, EVENT_6, EVENT_5, EVENT_4, EVENT_3, EVENT_2, EVENT_1, TSTATUS#. order listed shows order with TREADY# most significant TSTATUS# least significant bit. address/data select input TACTIVE signal. When equals address phase occurs next rising edge; when signal data phase occurs. addressing scheme input interface described Table Table Vector Input Interface Addressing Scheme
Data Select (TACTIVE) AD[7:0] 1RRRRRRR Description This address phase where "RRRRRRR" addresses RAM. This allows addressing bytes RAM. This address phase where "RRRRR" addresses Alert ASIC registers. This addresses registers. "XX" "don't care" bits. This data phase where "DDDDDDDD" data that written previously latched address from address phase.
0XXRRRRR
DDDDDDDD
Note:
This only input interface. Section 5.3.2, "Vector Output Interface" describes output interface more detail.
5.3.2
Vector Output Interface
output interface Vector Test Mode uses bits. This output simply result current addresses latched from vector input interface. example, last address phase input vector interface 10001001b, some propagation delay after this value latched rising clock edge, output interface would show results RAM, address 09h. 8-bit data output signals used TDATA[7:0]. This order shows order, where TDATA7 most significant TDATA0 least significant bit.
Networking Silicon Alert LAN* ASIC
Electrical Specifications
Recommended Operation Conditions
Table Recommended Operating Conditions
Symbol Parameter voltage supply Operating ambient temperature Junction temperature 4.75 5.25 Unit
Absolute Maximum Ratings
Table Absolute Maximum Ratings
Symbol TSTG RPUD Parameter voltage supply Input voltage input current Storage temperature Pull-up/Pull-down resistor -0.3 -1.0 Unit
Characteristics
Table Characteristics
Symbol Parameter Voltage input Condition CMOS CMOS CMOS Unit
Voltage input high
Switching threshold Input current: CMOS, inputs Inputs with pull-down resistors inputs with pull-up resistors
-115
-214
Alert LAN* ASIC
Table Characteristics
Symbol Parameter Condition 5.25 VDD; 5.25 input bidirectional buffer output bufferb Unit
Voltage output high
Voltage output
Tri-state output leakage current
Output short current
-117
Quiescent supply current
Input capacitance
COUT
Output capacitance
output. output short circuit current other outputs will scale. Output using single buffer structure (excluding package).
Networking Silicon Alert LAN* ASIC
Packaging Information
allocation based 44-pin Thin Quad Flat Package (TQFP). Package dimensions attributes shown Figure Table below.
Figure Dimension Diagram Alert ASIC
NOTES: Coplanarity difference between highest lead seating plane, -C-. Datums determined Datum plane -H-. Datum plane determined seating plane -C-. Dimensions include mold protrusion. Allowable protrusion 0.25 millimeter/0.010 inch side. Dimensions include mold mismatch determined Datum plane -H-. Details identifier optional must located within zone indicated.
Alert LAN* ASIC
Datum plane located mold parting line coincident with bottom leads where lead exits plastic body. drawing/dimensions only reference. board layout, request detailed engineering drawing from Logic sales office.
Table Dimensions 44-pin TQFP Alert ASIC
Symbol NOTE: measurements millimeters. -0.05 1.35 0.30 11.90 9.90 -11.90 9.90 0.45 -Max 1.60 -1.45 0.45 12.10 10.10 -12.10 10.10 0.75 0.10 0.10 -0.80
Networking Silicon Alert LAN* ASIC
Appendix Alert Supporting Hardware
Alert ASIC stand alone device. requires additional components create functional management solution. possible supporting hardware identified this appendix. Note: Supporting hardware sets will differ from implementation implementation.
82558 B-step device
82558 Ethernet Controller required complete solution. Alert ASIC designed communicate with proprietary interface 82558B. 82558B provides functionality transmit data network calculates adds 32-bit data packet from Alert ASIC.
64x16 EEPROM
Alert ASIC designed 64x16 EEPROM configure default settings upon reset hard transitions. EEPROM present contains invalid checksum, Alert ASIC defaults component default settings defined section Section 4.0, "Configuration Status Registers" page Note: Alert ASIC requires EEPROM configuration settings; this separate EEPROM from 82558B's EEPROM.
Environmental integrated circuit
environmental that capable monitoring voltage, temperature, cover tamper used part system management solution. However, only input signal Alert ASIC exists (EVENT_2). voltage specification, Alert ASIC expects receive event EVENT_2 signal. Alert uses other inputs, EVENT_3 (BTI Temperature) EVENT_1 (Cover Tamper), monitor these other events. This required since Alert ASIC does have ability distinguish difference between temperature voltage events over input signal.
PIIX4 equivalent
PCI-to-ISA/IDE Xcelerator (PIIX4) provides master interface that enables system BIOS communicate with Alert ASIC. PIIX4 also provides PWR_GOOD PCI_RST# signals that propagate Alert ASIC. Note: PIIX4 ability force system into power state without prior indication software. This reason Alert ASIC monitors PWR_GOOD hard transition.
Sticky latch (optional)
Sticky latches useful detecting events that occur when system state (completely off), such Cover Tamper input. latch battery-backed that Alert ASIC will become aware that event occurred when powered-up. sticky latch also provides ability reset driving opposite polarity latch bidirectional pin, EVENT_1, Alert ASIC. EVENT_1 Alert ASIC ability clear sticky latch. this feature enabled, executed clearing STA_EV1 Event Status register. result least output
Alert LAN* ASIC
pulse opposite polarity EVENT_1 pin. example sticky latch circuit illustrated Figure
SAMPLE/CLEAR
5VSB
Figure Sticky Latch Example Note: This solution also prohibits ASIC cover tamper clear mechanism (the ASIC configured output clear pulse). environmental should clear sticky latch.

Full system management solution with environmental instrumentation int

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