Preliminary PRELIMINARY CMOS SRAM 256Kx4 (with High Speed Static
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K6R1004V1B-C
Preliminary PRELIMINARY CMOS SRAM
256Kx4 (with High Speed Static RAM(3.3V Operating), Revolutionary out.
Revision History
Rev. Rev.1.0 History Initial release with Design Target. Release Preliminary Data Sheet. 1.1. Replace Design Target Preliminary. Release Final Data Sheet. 2.1. Delete Preliminary. 2.2. Delete L-version. 2.3. Delete Data Retention Characteristics Waveform. 2.4. Delete Industrial Temperature Range Part. 2.5. Delete TSOP2 Package. 2.6. Capacitive load test environment test load. 2.7. Change characteristics. Previous spec. Changed spec. Items (8/10/12ns part) (8/10/12ns part) 150/140/130mA 150/145/140mA 30mA 50mA Draft Data Apr. 1st, 1997 Jun. 1st, 1997 Feb. 25th, 1998 Rev.2.0 Remark Design Target Preliminary Final
attached data sheets prepared approved SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications. SAMSUNG Electronics will evaluate reply your requests questions parameters this device. have questions, please contact SAMSUNG branch office near your office, call contact Headquarters.
February 1998
K6R1004V1B-C
FEATURES
Fast Access Time 8,10,12ns(Max.) Power Dissipation Standby (TTL) 50mA(Max.) (CMOS) 5mA(Max.) Operating K6R1004V1B-8 150mA(Max.) K6R1004V1B-10 145mA(Max.) K6R1004V1B-12 140mA(Max.) Single 3.3±0.3V Power Supply Compatible Inputs Outputs Fully Static Operation Clock Refresh required Three State Outputs Center Power/Ground Configuration Standard Configuration K6R1004V1B-J 32-SOJ-400
Preliminary PRELIMINARY CMOS SRAM
256K (with OE)High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTION
K6R1004V1B 1,048,576-bit high-speed Static Random Access Memory organized 262,144 words bits. K6R1004V1B uses common input output lines output enable which operates faster than address access time read cycle. device fabricated using SAMSUNGs advanced CMOS process designed highspeed circuit technology. particularly well suited high-density high-speed system applications. K6R1004V1B packaged 32-pin plastic SOJ.
CONFIGURATION(Top View)
FUNCTIONAL BLOCK DIAGRAM
CLK. Gen.
Pre-Charge Circuit
I/O1
I/O4
I/O3
Select
I/O2
Memory Array Rows 1024x4 Columns
I/O1 ~I/O4
Data Cont. Gen.
Circuit Column Select
FUNCTION
Name Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3V) Ground Connection
I/O1 I/O4
February 1998
K6R1004V1B-C
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT TSTG Rating -0.5 -0.5
Preliminary PRELIMINARY CMOS SRAM
Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress ating only functional operation device these other conditions above those indicated operating sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
RECOMMENDED OPERATING CONDITIONS(TA=0 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Voltage Symbol -0.3* 0.3** Unit
VIL(Min)=-2.0V a.c(Pulse Width 6ns) 20mA. (Max)=VCC 2.0V (Pulse Width 6ns) 20mA.
OPERATING CHARACTERISTICS(TA=0 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol Test Conditions VIN=VSS CS=VIH OE=VIH WE=VIL VOUT=VSS Min. Cycle, 100% Duty CS=VIL, VIN=VIH VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V VIN0.2V IOL=8mA IOH=-4mA 10ns 12ns Standby Current ISB1 Output Voltage Level Output High Voltage Level Unit
CAPACITANCE* (TA=25°C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance
Capacitance sampled 100% tested.
Symbol CI/O
Test Conditions VI/O=0V VIN=0V
Unit
February 1998
K6R1004V1B-C
CHARACTERISTICS (TA=0 70°C, VCC=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter Input Pulse Levels Input Rise Fall Times Input Output timing Reference Levels Output Loads Value 1.5V below
Preliminary PRELIMINARY CMOS SRAM
Output Loads(A)
Output Loads(B) tHZ, tLZ, tWHZ, tOW, tOLZ tOHZ +3.3V
DOUT
1.5V
30pF* DOUT
5pF*
Capacitive Load consists components test environment.
Including Scope Capacitance
READ CYCLE
Parameter Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Chip Enable Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Chip Selection Power Time Chip Selection Power DownTime Symbol tOLZ tOHZ K6R1004V1B-8 K6R1004V1B-10 K6R1004V1B-12 Unit
February 1998
K6R1004V1B-C
WRITE CYCLE
Parameter Write Cycle Time Chip Select Write Address Set-up Time Address Valid Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z Symbol tWP1 tWHZ K6R1004V1B-8 K6R1004V1B-10
Preliminary PRELIMINARY CMOS SRAM
K6R1004V1B-12
Unit
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS=OE=VIL WE=VIH)
Address Data Previous Valid Data Valid Data
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tOLZ tLZ(4,5) Valid Data tOHZ tHZ(3,4,5)
Data Current
February 1998
K6R1004V1B-C
NOTES(READ CYCLE)
Preliminary PRELIMINARY CMOS SRAM
high read cycle. read cycle timing referenced from last valid address first transition address. tOHZ defined time which outputs achieve open circuit condition referenced levels. given temperature voltage condition, (Max.) less than tLZ(Min.) both given device from device device. Transition measured ±200mV from steady state voltage with Load(B). This parameter sampled 100% tested. Device continuously selected with CS=VIL. Address valid prior coincident with transition low. common applications, minimization elimination contention conditions necessary during read write cycle.
TIMING WAVEFORM WRITE CYCLE(1) (OE= Clock)
Address tCW(3) tAS(4) Data High-Z tOHZ(6) Data High-Z(8) Valid Data tWP(2) tWR(5)
TIMING WAVEFORM WRITE CYCLE(2)
(OE=Low Fixed)
Address tCW(3) tAS(4) Data High-Z tWHZ(6) Data High-Z(8) Valid Data
(10)
tWR(5)
tWP1(2)
February 1998
K6R1004V1B-C
TIMING WAVEFORM WRITE CYCLE(3) (CS=Controlled)
Address tCW(3) tAS(4) Data tWP(2)
Preliminary PRELIMINARY CMOS SRAM
tWR(5)
High-Z
tWHZ(6)
Valid Data
High-Z
Data
High-Z
High-Z(8)
NOTES(WRITE CYCLE) write cycle timing referenced from last valid address first transition address. write occurs during overlap write begins latest transition going going write ends earliest transition going high going high. measured from beginning write write. measured from later going write. measured from address valid beginning write. measured from write address change. applied case write ends going high. Read Mode during this period, pins output low-Z state. Inputs opposite phase output must applied because contention occur. common applications, minimization elimination contention conditions necessary during read write cycle. goes simultaneously with going after going low, outputs remain high impedance state. Dout read data address. When pins output state. input signals opposite phase leading output should applied.
FUNCTIONAL DESCRIPTION
means Dont Care.
Mode Select Output Disable Read Write
High-Z High-Z DOUT
Supply Current ISB, ISB1
February 1998
K6R1004V1B-C
PACKAGE DIMENSIONS
32-SOJ-400
Preliminary PRELIMINARY CMOS SRAM
Units:millimeters/Inches
10.16 0.400
11.18 ±0.12 0.440 ±0.005
9.40 ±0.25 0.370 ±0.010
0.20 21.36 0.841 20.95 ±0.12 0.825 ±0.005 1.30 0.051 1.30 0.051
+0.10 -0.05 +0.004 0.017 -0.002
0.69 0.027
0.008
+0.10 -0.05 +0.004 -0.002
3.76 0.148
0.10 0.004
0.95 0.0375
0.43
1.27 0.050
0.71 0.028
+0.10 -0.05 +0.004 -0.002
February 1998
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