Power Voltage CMOS Static CMOS SRAM Revision History Re

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Power Voltage CMOS Static CMOS SRAM Revision History Re

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K6L1016V3B, K6L1016U3B Family
Power Voltage CMOS Static
CMOS SRAM
Revision History
Revision History Design target Initial draft Draft Data July 1995 August 1995 Remark Advance Preliminary Final
Finalize April 1996 datasheet commercial industrial part 3.0, 3.3V product. Revised Change datasheet format. Remove write current value. Remove power product from TSOP package Remove 100ns part from KM616V1000B Family Remove Extended product Errata correction February 1998
Final
2.01
August 1998
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision 2.01 February 1998
K6L1016V3B, K6L1016U3B Family
Power Voltage CMOS Static
FEATURES
Process Technology: Poly Load Organization: Data Byte Control: LB=I/O1~8, UB=I/O9~16 Power Supply Voltage: K6L1016V3B family: 3.0~3.6V K6L1016U3B family: 2.7~3.3V Data Retention Voltage 2V(Min) Three state output Compatible Package Type :44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
K6L1016V3B K6L1016U3B families fabricated SAMSUNGs advanced CMOS process technology. families support various operating temperature ranges have small package types user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed Standby
(ISB1, Max)
Operating (Icc2, Max)
Type
K6L1016V3B-B K6L1016U3B-B K6L1016V3B-F K6L1016U3B-F
Commercial(0~70°C) Industrial(-40~85°C)
3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V
1)ns 100ns 100ns
15µA 15µA 20µA 20µA
65mA
44-TSOP2 Forward/Reverse
parameter measured with 30pF test load.
DESCRIPTION
I/OI I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/OI I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
FUNCTIONAL BLOCK DIAGRAM
gen.
I/O1~I/O8
Precharge circuit.
Memory array 1024 rows columns
select
44-TSOP2 Forward
44-TSOP2 Reverse
Data cont Data cont Data cont
Circuit Column select
9~I/O16
Name
Function Chip Select Input Output Enable Input Write Enable Input Lower Byte (I/O1~8) Upper Byte(I/O9~16)
Name
Function Power Ground
I/O1~16 Data Inputs/Outputs A0~A15 Address Inputs Connection
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision 2.01 February 1998
K6L1016V3B, K6L1016U3B Family
PRODUCT LIST
Commercial Temperature Products(0~70°C) Part Name
K6L1016V3B-TB70 K6L1016U3B-TB10 K6L1016V3B-RB70 K6L1016U3B-RB10
CMOS SRAM
Industrial Temperature Products(-40~85°C) Part Name Function
44-TSOP-2F, 3.3V, 85ns, 44-TSOP-2F, 3.0V, 100ns, 44-TSOP-2R, 3.3V, 85ns, 44-TSOP-2R, 3.0V, 100ns,
Function
44-TSOP-2F, 3.3V, 70ns, 44-TSOP-2F, 3.0V, 100ns, 44-TSOP-2R, 3.3V, 70ns, 44-TSOP-2R, 3.0V, 100ns,
K6L1016V3B-TF85 K6L1016U3B-TF10 K6L1016V3B-RF85 K6L1016U3B-RF10
FUNCTIONAL DESCRIPTION
I/O1~8 High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Active Active Active Active Active Active Active Active
means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Symbol VIN,VOUT TSTG Ratings -0.5 Vcc+0.5 -0.5 Operating Temperature Soldering temperature time TSOLDER 260°C, 10sec (Lead Only) Unit Remark K6L1016V3B-B K6L1016U3B-B K6L1016V3B-F K6L1016U3B-F
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision 2.01 February 1998
K6L1016V3B, K6L1016U3B Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol Product K6L1016V3B Family K6L1016U3B Family Family K6L1016V3B, K6L1016U3B Family K6L1016V3B, K6L1016U3B Family -0.3
CMOS SRAM
VCC+0.3
Unit
Note: Commercial Product TA=0 70°C, otherwise specified Industrial Product TA=-40 85°C, otherwise specified Overshoot CC+3.0V case pulse width 30ns Undershoot -3.0V case pulse width 30ns Overshoot undershoot sampled, 100% tested
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ICC11) ICC2 Output voltage Output high voltage Standby Current(TTL) Standby current(CMOS) ISB1 VIN=VSS
CS=VIH OE=VIH WE=VIL, VIO=VSS
Test Conditions
Read Write
152)
Unit
IIO=0mA, CS=VIL, VIN=VIL VIH, Read Cycle time=1µs, 100% duty, IO=0mA CS0.2V, VIN0.2V VINVcc-0.2V
Average operating current
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL VIN=VIL
IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs=VIL CSVCC-0.2V, Other inputs=0VCC
Industrial Product ICC1(Read/Write)=20mA/45mA Industrial Product=20µA
Revision 2.01 February 1998
K6L1016V3B, K6L1016U3B Family
OPERATING CONDITIONS
TEST CONDITIONS( Test Load Input/Output Reference)
Input pulse level 2.2V Input rising falling time Input output reference voltage :1.5V Output load(see right) CL=100pF+1TTL CL=30pF+1TTL CL1)
CMOS SRAM
Including scope capacitance
CHARACTERISTICS (K6L1016V3B-C Family Vcc=3.0~3.6V, K6L1016U3B-I Family Vcc=2.7~3.3V
Commercial product TA=0 to70°C, Industrial product :TA=-40 85°C) Speed Bins Parameter List Symbol Read cycle time Address access time Chip select output Output enable valid output UB,LB Access Time Read Chip select low-Z output Output enable low-Z output UB,LB enable low-Z output Chip disable high-Z output Output disable high-Z output UB,LB disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write pulse width Write valid write Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tOLZ tBLZ tOHZ tBHZ tWHZ 70ns 85ns 100ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time
Industrial product=20µA
Symbol tSDR tRDR
Test Condition CSVcc-0.2V VCC=3.0V, CSVcc-0.2V data retention waveform
Unit
Revision 2.01 February 1998
K6L1016V3B, K6L1016U3B Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1)
Address Data Previous Data Valid
CMOS SRAM
(Address Controlled, CS=OE=VIL, WE=VIH, or/and LB=VIL)
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address
tBHZ tOLZ tBLZ Data
High-Z
tOHZ Data Valid
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision 2.01 February 1998
K6L1016V3B, K6L1016U3B Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
High-Z
TIMING WAVEFORM WRITE CYCLE(2) Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision 2.01 February 1998
K6L1016V3B, K6L1016U3B Family
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends going high.
DATA RETENTION WAVE FORM
controlled
3.0/2.7V1) tSDR Data Retention Mode tRDR
2.2V CSVCC 0.2V
3.0V K6L1016V3B family, 2.7V K6L1016U3B family
Revision 2.01 February 1998
K6L1016V3B, K6L1016U3B Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (400F)
CMOS SRAM
Unit: millimeter(inch)
0~8° 0.25 0.010
0.45 ~0.75 0.018 0.030
11.76±0.20 0.463±0.008
10.16 0.400
0.50 0.020
1.00±0.10 0.039±0.004 1.20 MAX. 0.047
0.15
.002
18.81 MAX. 0.741 18.41±0.10 0.725±0.004
0.805 0.032
0.35±0.10 0.014±0.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004
THIN SMALL OUTLINE PACKAGE TYPE (400R)
0.25 0.010
0~8°
0.45 ~0.75 0.018 0.030
11.76±0.20 0.463±0.008
10.16 0.400
0.50 0.020
1.00±0.10 0.039±0.004 1.20 MAX. 0.047
0.15
.006
18.81 MAX. 0.741 18.41±0.10 0.725±0.004
0.805 0.032
0.35±0.10 0.014±0.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004
Revision 2.01 February 1998

Power Voltage CMOS Static CMOS SRAM Revision History Re

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