Power CMOS Static CMOS SRAM Revision History Revision H

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Power CMOS Static CMOS SRAM Revision History Revision H

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K6L1016C3B
Power CMOS Static
CMOS SRAM
Revision History
Revision History
Initial draft Finalize datasheet commercial industrial part. Revised Change datasheet format. Remove write current value. Remove power product from product
Draft Data
August 1995 April 1996
Remark
Preliminary Final
February 1998
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision February 1998
K6L1016C3B
Power CMOS Static
FEATURES SUMMARY
Process Technology: Poly Load Organization: Data Byte Control: LB=I/O1~8, UB=I/O9~16 Power Supply Voltage: 4.5~5.5V Data Retention Voltage: 2V(Min) Three state output Compatible Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
K6L1016C3B families fabricated SAMSUNGs advanced CMOS process technology. families support various operating temperature ranges have various package types user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6L1016C3B-B K6L1016C3B-F Operating Temperature Commercial(0~70°C) 5.5V Industrial(-40~85°C) 70/100ns 50µA
parameter measured with 30pF test load.
Range
Speed 55*/70ns
Standby (ISB1, Max) 20µA
Operating (ICC2, Max) 120mA
Type
44-TSOP2-F/R
DESCRIPTION
I/OI I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/OI I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
FUNCTIONAL BLOCK DIAGRAM
gen.
Precharge circuit.
select Memory array 1024 rows columns
44-TSOP2 Forward
44-TSOP2 Reverse
I/O1~I/O8
Data cont Data cont Data cont
Circuit Column select
9~I/O16
Name
Function Chip Select Input Output Enable Input Write Enable Input
Name Power
Function
Ground Lower Byte (I/O1~8) Upper Byte(I/O9~16) Connection
A0~A15 Address Inputs 1~16 Data Inputs/Outputs
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision February 1998
K6L1016C3B
PRODUCT LIST
Commercial Temperature Product(0~70°C) Part Name K6L1016C3B-TB55 K6L1016C3B-TB70 K6L1016C3B-RB55 K6L1016C3B-RB70 Function 44-TSOP2-F, 55ns, LL-pwr 44-TSOP2-F, 70ns, LL-pwr 44-TSOP2-R, 55ns, LL-pwr 44-TSOP2-R, 70ns, LL-pwr
CMOS SRAM
Industrial Temperature Products(-40~85°C) Part Name K6L1016C3B-TF70 K6L1016C3B-TF10 K6L1016C3B-RF70 K6L1016C3B-RF10 Function 44-TSOP2-F, 70ns, LL-pwr 44-TSOP2-F, 100ns, LL-pwr 44-TSOP2-R, 70ns, LL-pwr 44-TSOP2-R, 100ns, LL-pwr
FUNCTIONAL DESCRIPTION
I/O1~8 High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Active Active Active Active Active Active Active Active
means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Soldering temperature time Symbol VIN,VOUT TSTG TSOLDER Ratings -0.5 Vcc+0.5 -0.5 260°C, 10sec(Lead Only) Unit Remark K6L1016C3B-B K6L1016C3B-F
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision February 1998
K6L1016C3B
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol -0.5
CMOS SRAM
VCC+0.5
Unit
Note: Commercial Product TA=0 70°C, otherwise specified Industrial Product TA=-40 85°C, otherwise specified Overshoot VCC+3.0V case pulse width 30ns Undershoot -3.0V case pulse width 30ns Overshoot undershoot sampled, 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply Symbol ICC1 ICC2 Output voltage Output high voltage Standby Current(TTL) Standby Current(CMOS)
Industrial Product 50µA
Test Conditions VIN=VSS
CS=VIH OE=VIH WE=VIL, VIO=VSS
Read Write
201)
Unit
IIO=0mA, CS=VIL, VIN=VIL VIH, Read Cycle time=1µs, 100% duty, IIO=0mA CS0.2V, VIN0.2V VINVcc-0.2V
Average operating current
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIL IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs=V CSVCC-0.2V, Other inputs=0VCC
ISB1
Revision February 1998
K6L1016C3B
OPERATING CONDITIONS
TEST CONDITIONS
(Test Load Test Input/Output Reference)
CMOS SRAM
Input pulse level 2.4V Input rising falling time Input output reference voltage 1.5V Output load (See right) :CL=100pF+1TTL CL=30pF+1TTL
CL1)
Including scope capacitance
CHARACTERISTICS
Speed Bins Parameter List Read cycle time Address access time Chip select output Output enable valid output UB,LB Access Time Read Chip select low-Z output UB,LB enable low-Z output Output enable low-Z output Chip disable high-Z output UB,LB disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write pulse width Write valid write Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z Symbol tBLZ tOLZ tBHZ tOHZ tWHZ 55ns 70ns 100ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CSVcc-0.2V VCC=3.0V, CSVcc-0.2V data retention waveform Unit
Revision February 1998
K6L1016C3B
TIMMING DIAGRAMS
CMOS SRAM
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, or/and LB=VIL)
Address Data Previous Data Valid Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address
tBHZ tOLZ tBLZ Data
High-Z
tOHZ Data Valid
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than (Min.) both given device from device device interconnection.
Revision February 1998
K6L1016C3B
TIMING WAVEFORM WRITE CYCLE(1)
Controlled)
CMOS SRAM
Address tCW(2) tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid High-Z tWR(4)
TIMING WAVEFORM WRITE CYCLE(2) Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision February 1998
K6L1016C3B
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(t write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends going high.
DATA RETENTION WAVE FORM
controlled
4.5V tSDR Data Retention Mode tRDR
2.2V CSVCC 0.2V
Revision February 1998
K6L1016C3B
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (400F)
CMOS SRAM
Unit: millimeter(inch)
0~8° 0.25 0.010
0.45 ~0.75 0.018 0.030
10.16 0.400
11.76±0.20 0.463±0.008
0.50 0.020
1.00±0.10 0.039±0.004 18.81 MAX. 0.741 18.41±0.10 0.725±0.004 1.20 MAX. 0.047
0.15 0.00
0.805 0.032
0.35±0.10 0.014±0.004
0.80 0.0315
THIN SMALL OUTLINE PACKAGE TYPE (400R)
0.25 0.010
0.05 MIN. 0.002
0.10 0.004
0~8°
0.45 ~0.75 0.018 0.030
10.16 0.400
11.76±0.20 0.463±0.008
0.50 0.020
1.00±0.10 0.039±0.004 18.81 MAX. 0.741 18.41±0.10 0.725±0.004 1.20 MAX. 0.047
0.15 0.006
0.805 0.032
0.35±0.10 0.014±0.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004
Revision February 1998

Power CMOS Static CMOS SRAM Revision History Revision H

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