128K Power Voltage CMOS Static CMOS SRAM Revision History
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K6L1008V2C, K6L1008U2C Family
128K Power Voltage CMOS Static
CMOS SRAM
Revision History
Revision History
Initial draft Finalize Increased ISB, Commercial part 10µA Industrial part 20µA Revise Change speed KM68V1000C Family: 70/85ns 70/100ns KM68U1000C Family: 70/100ns 85/100ns Improved operating current: 40mA 35mA Improved power dissipation 0.7W 1.0W Improved standby current Extended/Industrial: 10µA VIL: 0.4V 0.6V
Draft Data
July 1996 December 1996
Remark
Preliminary Final
November 1997
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision November 1997
K6L1008V2C, K6L1008U2C Family
128K Power Voltage CMOS Static
FEATURES
Process Technology: 0.4µm CMOS Organization: 128K Power Supply Voltage: K6L1008V2C family: 3.0~3.6V K6L1008U2C family: 2.7~3.3V Data Retention Voltage: 2V(Min) Three state output Compatible Package Type: 32-SOP-525, 32-TSOP1-0820F/R, 32-TSOP1-0813.4F/R
CMOS SRAM
GENERAL DESCRIPTION
K6L1008V2C K6L1008U2C families fabricated SAMSUNGs advanced CMOS process technology. families support various operating temperature ranges have various package types user flexibility system design. families also supports data retention voltage battery back-up operation with data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6L1008V2C-B K6L1008U2C-B K6L1008V2C-D K6L1008U2C-D K6L1008V2C-F K6L1008U2C-F Industrial(-40~85°C) Extended(-25~85°C) Operating Temperature Range 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V Speed 70/100ns 85/100ns 70/100ns 85/100ns 70/100ns 85/100ns 10µA 35mA 32-SOP 32-TSOP1-F/R 32-sTSOP1-F/R Standby (ISB1, Max) Operating (ICC2, Max) Type
Commercial(0~70°C)
DESCRIPTION
I/O8 I/O7 I/O6 I/O5 I/O4 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
I/O1 I/O2 I/O3
32-TSOP 32-STSOP Type1-Forward
Memory array 1024 rows columns
select
32-SOP
I/O1 I/O8
32-TSOP 32-STSOP Type1-Reverse
Data cont
Circuit Column select
Name
~A16 I/O1 ~I/O8
Function
Chip Select Inputs Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Power Ground Connection
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision November 1997
K6L1008V2C, K6L1008U2C Family
PRODUCT LIST
Commercial Temperature Products (0~70°C) Part Name
K6L1008V2C-GB70 K6L1008V2C-GB10 K6L1008V2C-TB70 K6L1008V2C-TB10 K6L1008V2C-RB70 K6L1008V2C-RB10 K6L1008U2C-GB85 K6L1008U2C-GB10 K6L1008U2C-TB85 K6L1008U2C-TB10 K6L1008U2C-RB85 K6L1008U2C-RB10 K6L1008V2C-YB70 K6L1008V2C-YB10 K6L1008V2C-NB70 K6L1008V2C-NB10 K6L1008U2C-YB85 K6L1008U2C-YB10 K6L1008U2C-NB85 K6L1008U2C-NB10
CMOS SRAM
Industrial Temperature Products (-40~85°C) Part Name
K6L1008V2C-GF70 K6L1008V2C-GF10 K6L1008V2C-TF70 K6L1008V2C-TF10 K6L1008V2C-RF70 K6L1008V2C-RF10 K6L1008U2C-GF85 K6L1008U2C-GF10 K6L1008U2C-TF85 K6L1008U2C-TF10 K6L1008U2C-RF85 K6L1008U2C-RF10 K6L1008V2C-YF70 K6L1008V2C-YF10 K6L1008V2C-NF70 K6L1008V2C-NF10 K6L1008U2C-YF85 K6L1008U2C-YF10 K6L1008U2C-NF85 K6L1008U2C-NF10
Extended Temperature Products (-25~85°C) Part Name
K6L1008V2C-GD70 K6L1008V2C-GD10 K6L1008V2C-TD70 K6L1008V2C-TD10 K6L1008V2C-RD70 K6L1008V2C-RD10 K6L1008U2C-GD85 K6L1008U2C-GD10 K6L1008U2C-TD85 K6L1008U2C-TD10 K6L1008U2C-RD85 K6L1008U2C-RD10 K6L1008V2C-YD70 K6L1008V2C-YD10 K6L1008V2C-ND70 K6L1008V2C-ND10 K6L1008U2C-YD85 K6L1008U2C-YD10 K6L1008U2C-ND85 K6L1008U2C-ND10
Function
32-SOP, 70ns, 3.3V 32-SOP, 100ns, 3.3V 32-TSOP 70ns, 3.3V 32-TSOP 100ns, 3.3V 32-TSOP 70ns, 3.3V 32-TSOP 100ns, 3.3V 32-SOP, 85ns, 3.0V 32-SOP, 100ns, 3.0V 32-TSOP 85ns, 3.0V 32-TSOP 100ns, 3.0V 32-TSOP 85ns, 3.0V 32-TSOP 100ns, 3.0V 32-sTSOP 70ns, 3.3V 32-sTSOP 100ns, 3.3V 32-sTSOP 70ns, 3.3V 32-sTSOP 100ns, 3.3V 32-sTSOP 85ns, 3.0V 32-sTSOP 100ns, 3.0V 32-sTSOP 85ns, 3.0V 32-sTSOP 100ns, 3.0V
Function
32-SOP, 70ns, 3.3V 32-SOP, 100ns, 3.3V 32-TSOP 70ns, 3.3V 32-TSOP 100ns, 3.3V 32-TSOP 70ns, 3.3V 32-TSOP 100ns, 3.3V 32-SOP, 85ns, 3.0V 32-SOP, 100ns, 3.0V 32-TSOP 85ns, 3.0V 32-TSOP 100ns, 3.0V 32-TSOP 85ns, 3.0V 32-TSOP 100ns, 3.0V 32-sTSOP 70ns, 3.3V 32-sTSOP 100ns, 3.3V 32-sTSOP 70ns, 3.3V 32-sTSOP 100ns, 3.3V 32-sTSOP 85ns, 3.0V 32-sTSOP 100ns, 3.0V 32-sTSOP 85ns, 3.0V 32-sTSOP 100ns, 3.0V
Function
32-SOP, 70ns, 3.3V 32-SOP, 100ns, 3.3V 32-TSOP 70ns, 3.3V 32-TSOP 100ns, 3.3V 32-TSOP 70ns, 3.3V 32-TSOP 100ns, 3.3V 32-SOP, 85ns, 3.0V 32-SOP, 100ns, 3.0V 32-TSOP 85ns, 3.0V 32-TSOP 100ns, 3.0V 32-TSOP 85ns, 3.0V 32-TSOP 100ns, 3.0V 32-sTSOP 70ns, 3.3V 32-sTSOP 100ns, 3.3V 32-sTSOP 70ns, 3.3V 32-sTSOP 100ns, 3.3V 32-sTSOP 85ns, 3.0V 32-sTSOP 100ns, 3.0V 32-sTSOP 85ns, 3.0V 32-sTSOP 100ns, 3.0V
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout
Mode
Deselected Deselected Output Disabled Read Write
Power
Standby Standby Active Active Active
means dont care(Must high status.)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT TSTG Ratings -0.5 VCC+0.5 -0.3 Soldering temperature time TSOLDER 260°C, 10sec (Lead Only) Unit Remark K6L1008V2C-L/K6L1008U2C-L K6L1008V2C-N/K6L1008U2C-N K6L1008V2C-P/K6L1008U2C-P
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision November 1997
K6L1008V2C, K6L1008U2C Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol Product K6L1008V2C Family K6L1008U2C Family Family K6L1008V2C, K6L1008U2C Family K6L1008V2C, K6L1008U2C Family -0.3
CMOS SRAM
Vcc+0.32) Unit
Commercial Product: TA=0 70°C, unless otherwise specified Extended Product: TA=-25 85°C, unless otherwise specified Industrial Product: A=-40 85°C, unless otherwise specified Overshoot: VCC+3.0V case pulse width 30ns Undershoot: -3.0V case pulse width 30ns Overshoot undershoot sampled, 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply Average operating current Symbol ICC1 ICC2 Output voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) ISB1 VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL, VIO=Vss IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL VIH, Read Cycle time=1µs, 100% duty, IIO=0mA, CS10.2V, CS2VCC-0.2V, VIN0.2V VINVCC-0.2V Read Write Test Conditions Unit
Cycle time=Min, 100% duty, IIO=0mA, =VIL, =VIH, =VIL
IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other inputs=VIL CS1Vcc-0.2V, CS2Vcc-0.2V CS20.2V, Other inputs=0~Vcc
Revision November 1997
K6L1008V2C, K6L1008U2C Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Input/Output Reference)
Input pulse level: 2.2V Input rising falling time: Input output reference voltage:1.5V Output load(see right): L=100pF+1TTL CL1)
CMOS SRAM
Including scope capacitance
CHARACTERISTICS (Commercial product:TA=0 70°C, Extended product:TA=-25 85°C, Industrial product: TA=-40 85°C
K6L1008V2C Family: Vcc=3.0~3.6V, K6L1008U2C Family: Vcc=2.7~3.3V)
Speed Bins Parameter List Symbol 70ns Read cycle time Address access time Chip select output Output enable valid output Read Chip select low-Z output Output enable low-Z output Chip disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write Write pulse width Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tCO1, tCO2 tOLZ tOHZ tWHZ 85ns 100ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR CS11)Vcc-0.2V Vcc=3.0V, CS1Vcc-0.2V, CS2VCC-0.2V, CS20.2V data retention waveform Test Condition1) Unit
CS1Vcc-0.2V, VCC-0.2V, 0.2V
Revision November 1997
K6L1008V2C, K6L1008U2C Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address Data Previous Data Valid
CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than (Min.) both given device from device device interconnection.
Revision November 1997
K6L1008V2C, K6L1008U2C Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
TIMING WAVEFORM WRITE CYCLE(2) (CS1 Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision November 1997
K6L1008V2C, K6L1008U2C Family
TIMING WAVEFORM WRITE CYCLE(3) (CS2 Controlled)
Address tAS(3) tCW(2) tWP(1) Data Data Valid tCW(2) tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap high write begins latest transition among goes low, going high going low: write earliest transition among going high, going going high, measured from beginning write write. measured from going going high write. measured from address valid beginning write. measured from write address change. WR(1) applied case write ends going high tWR(2) applied case write ends going low.
DATA RETENTION WAVE FORM
controlled
3.0/2.7V tSDR Data Retention Mode tRDR
2.2V CS1VCC-0.2V
controlled
3.0/2.7V1) tSDR
Data Retention Mode
tRDR
0.4V
3.0V K6L1008V2C Family, 2.7V K6L1008U2C Family
CS20.2V
Revision November 1997
K6L1008V2C, K6L1008U2C Family
PACKAGE DIMENSIONS
PLASTIC SMALL OUTLINE PACKAGE (525mil)
CMOS SRAM
Units: millimeter(inch)
0~8°
14.12±0.30 0.556±0.012
11.43±0.20 0.450±0.008
20.87 0.822 20.47±0.20 0.806±0.008
2.74±0.20 0.108±0.008 3.00 0.118
13.34 0.525
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.80±0.20 0.031±0.008
0.10 0.004
+0.100 -0.050 +0.004 0.016 -0.002
0.71 0.028
0.41
1.27 0.050
0.05 0.002
Revision November 1997
K6L1008V2C, K6L1008U2C Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (0813.4F)
CMOS SRAM
Units: millimeter(inch)
0.20 0.008
+0.10 -0.05 +0.004 -0.002
13.40±0.20 0.528±0.008
0.10 0.004
8.40 0.331 8.00 0.315
0.25 0.010
0.50 0.0197
1.00±0.10 0.039±0.004
0.25 0.010
11.80±0.10 0.465±0.004
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.05 0.002 1.20 0.047
0~8°
0.45~0.75 0.018~0.030
0.50 0.020
THIN SMALL OUTLINE PACKAGE TYPE (0813.4R)
0.10 0.004 0.20 0.008
+0.10 -0.05 +0.004 -0.002
13.40±0.20 0.528±0.008 8.40 0.331 8.00 0.315 0.25 0.010
0.50 0.0197
0.25 0.010
1.00±0.10 0.039±0.004 11.80±0.10 0.465±0.004
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.05 0.002
1.20 0.047
0~8°
0.45~0.75 0.018~0.030
0.50 0.020
Revision November 1997
K6L1008V2C, K6L1008U2C Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (0820F)
CMOS SRAM
Units: millimeter(inch)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.00±0.20 0.787±0.008 8.40 0.331 8.00 0.315 0.25 0.010
0.50 0.0197
1.00±0.10 0.039±0.004 1.20 0.047
+0.10 -0.05 0.006+0.004 -0.002
0.05 0.002
0.25 0.010
18.40±0.10 0.724±0.004
0.15
0~8°
0.45 ~0.75 0.018 ~0.030
0.50 0.020
THIN SMALL OUTLINE PACKAGE TYPE (0820R)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.00±0.20 0.787±0.008 8.40 0.331 8.00 0.315 0.25 0.010
0.50 0.0197
1.00±0.10 0.039±0.004 1.20 0.047 0.05 0.002
0.25 0.010
18.40±0.10 0.724±0.004
0~8°
0.45 ~0.75 0.018 ~0.030
0.50 0.020
Revision November 1997
0.10 0.004
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.10 0.004
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