64Kx8 Power Voltage CMOS Static CMOS SRAM Revision History

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64Kx8 Power Voltage CMOS Static CMOS SRAM Revision History

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K6L0908V2A, K6L0908U2A Family
64Kx8 Power Voltage CMOS Static
CMOS SRAM
Revision History
Revision
History
Design target Initial draft datasheet commercial, extended industrial product. 85ns part KM68V512AFamily. Finalize Revise 32-sTSOP type package product. Revise Change datasheet format Improve power dissipation 1.0W
Draft Data
January 1996 April 1996
Remark
Advance Preliminary
June 1996 September 1996
Final Final
February 1998
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision February 1998
K6L0908V2A, K6L0908U2A Family
64Kx8 Power Voltage CMOS Static
FEATURES
Process Technology: Poly Load Organization: 64Kx8 Power Supply Voltage K6L0908V2A family: 2.7~3.3V K6L0908U2A family: 3.0~3.3V Data Retention Voltage: 2V(Min) Three state output Compatible Package Type: 32-SOP-525, 32-TSOP1-0820F, 32-TSOP1-0813.4F
CMOS SRAM
GENERAL DESCRIPTION
K6L0908V2A K6L0908U2A families fabricated SAMSUNGs advanced CMOS process technology. families support various operating temperature ranges have various package types user flexibility system design. family also support data retention voltage battery back-up operation with data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6L0908V2A-B K6L0908U2A-B K6L0908V2A-D K6L0908U2A-D K6L0908V2A-F K6L0908U2A-F
parameter measured with 30pF test load.
Operating Temperature
Range 3.6V 3.3V
Speed 701)/85/100ns /100ns 701)/85/100ns 851)/100ns 701)/85/100ns /100ns
Standby (Isb1, Max) 10µA 10µA 20µA 15µA 20µA 15µA
Operating (Icc2, Max)
Type
Commercial(0~70°C)
Extended(-25~85°C)
3.6V 3.3V
40mA
32-SOP 32-TSOP1-F 32-sTSOP1-F
Industrial (-40~85°C)
3.6V 3.3V
DESCRIPTION
I/O1 I/O2 I/O3 I/O8 I/O7 I/O6 I/O5 I/O4 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
32-TSOP Type1 Forward (8mm 20mm)
32-SOP
select
Memory array rows columns
32-sTSOP Type1 Forward (8mm 13.4mm)
I/O1 I/O8
Data cont
Circuit Column select
Data cont
Name Name 1,CS2 A0~A15 I/O1~I/O8
Function Chip Select Inputs Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Power Ground Connection
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision February 1998
K6L0908V2A, K6L0908U2A Family
PRODUCT LIST
Commercial Temperature Products (0~70°C) Part Name
K6L0908V2A-GB70 K6L0908V2A-GB85 K6L0908V2A-GB10 K6L0908V2A-TB70 K6L0908V2A-TB85 K6L0908V2A-TB10 K6L0908V2A-YB70 K6L0908V2A-YB85 K6L0908V2A-YB10 K6L0908U2A-GB85 K6L0908U2A-GB10 K6L0908U2A-TB85 K6L0908U2A-TB10 K6L0908U2A-YB85 K6L0908U2A-YB10
CMOS SRAM
Industrial Temperature Products (-40~85°C) Part Name
K6L0908V2A-GF70 K6L0908V2A-GF85 K6L0908V2A-GF10 K6L0908V2A-TF70 K6L0908V2A-TF85 K6L0908V2A-TF10 K6L0908V2A-YF70 K6L0908V2A-YF85 K6L0908V2A-YF10 K6L0908U2A-GF85 K6L0908U2A-GF10 K6L0908U2A-TF85 K6L0908U2A-TF10 K6L0908U2A-YF85 K6L0908U2A-YF10
Extended Temperature Products (-25~85°C) Part Name
K6L0908V2A-GD70 K6L0908V2A-GD85 K6L0908V2A-GD10 K6L0908V2A-TD70 K6L0908V2A-TD85 K6L0908V2A-TD10 K6L0908V2A-YD70 K6L0908V2A-YD85 K6L0908V2A-YD10 K6L0908U2A-GD85 K6L0908U2A-GD10 K6L0908U2A-TD85 K6L0908U2A-TD10 K6L0908U2A-YD85 K6L0908U2A-YD10
Function
32-SOP, 70ns, 3.3V, 32-SOP, 85ns, 3.3V, 32-SOP, 100ns, 3.3V, 32-TSOP 70ns, 3.3V, 32-TSOP 85ns, 3.3V, 32-TSOP 100ns, 3.3V,LL 32-sTSOP F,70ns,3.3V,LL
Function
32-SOP, 70ns, 3.3V, 32-SOP, 85ns, 3.3V, 32-SOP, 100ns, 3.3V, 32-TSOP 70ns, 3.3V, 32-TSOP 85ns, 3.3V, 32-TSOP 100ns, 3.3V,LL 32-sTSOP F,70ns,3.3V,LL
Function
32-SOP, 70ns, 3.3V, 32-SOP, 85ns, 3.3V, 32-SOP, 100ns, 3.3V, 32-TSOP 70ns, 3.3V, 32-TSOP 85ns, 3.3V, 32-TSOP 100ns, 3.3V,LL 32-sTSOP F,70ns,3.3V,LL
32-sTSOP F,85ns,3.3V,LL 32-sTSOP F,100ns,3.3V,LL
32-SOP, 85ns, 3.0V, 32-SOP, 100ns, 3.0V, 32-TSOP 85ns, 3.0V, 32-TSOP 100ns, 3.0V, 32-sTSOP 85ns, 3.0V, 32-sTSOP 100ns,3.0V,
32-sTSOP F,85ns,3.3V,LL 32-sTSOP F,100ns,3.3V,LL
32-SOP, 85ns, 3.0V, 32-SOP, 100ns, 3.0V, 32-TSOP 85ns, 3.0V, 32-TSOP 100ns, 3.0V, 32-sTSOP 85ns, 3.0V, 32-sTSOP 100ns,3.0V,
32-sTSOP F,85ns,3.3V,LL 32-sTSOP F,100ns,3.3V,LL
32-SOP, 85ns, 3.0V, 32-SOP, 100ns, 3.0V, 32-TSOP 85ns, 3.0V, 32-TSOP 100ns, 3.0V, 32-sTSOP 85ns, 3.0V, 32-sTSOP 100ns,3.0V,
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout
Mode Deselected Deselected Output Disabled Read Write
Power Standby Standby Active Active Active
means dont care(Must high state.)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Symbol VIN,VOUT TSTG Ratings -0.5 VCC+0.5 -0.3 Operating Temperature Soldering temperature time TSOLDER 260°C, 10sec (Lead Only) Unit Remark K6L0908V2A-B, K6L0908U2A-B K6L0908V2A-D, K6L0908U2A-D K6L0908V2A-F, K6L0908U2A-F
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision February 1998
K6L0908V2A, K6L0908U2A Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol Product K6L0908V2A Family K6L0908U2A Family Family K6L0908V2A, K6L0908U2A Family K6L0908V2A, K6L0908U2A Family -0.3
CMOS SRAM
Vcc+0.3V Unit
Note: Commercial Product 70°C, otherwise specified Extended Product TA=-25 85°C, otherwise specified Industrial Product TA=-40 85°C, otherwise specified Overshoot +3.0V case pulse width30ns Undershoot -3.0V case pulse width30ns Overshoot undershoot sampled, 100% tested
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ICC1 Average operating current ICC2 Output voltage Output high voltage Standby Current(TTL) VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL, VIO=Vss IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH Cycle time=1µs, 100% duty, IIO=0mA, CS10.2V, CS2Vcc-0.2V, VIN0.2V VINVcc-0.2V Cycle time=Min, 100% duty, IIO=0mA CS1=VIL, CS2=VIH, VIN=VIL IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other inputs=VIL K6L0908V2A-B CS1Vcc-0.2V, CS2Vcc-0.2V, CS20.2V Other inputs=0~Vcc K6L0908V2A-D K6L0908V2A-F K6L0908U2A-B K6L0908U2A-D K6L0908U2A-F Test Conditions Unit
Standby Current(CMOS)
ISB1
Revision February 1998
K6L0908V2A, K6L0908U2A Family
OPERATING CONDITIONS
TEST CONDITIONS( Test Load Input/Output Reference)
Input pulse level 2.2V Input rising falling time Input output reference voltage :1.5V Output load(see right) CL=100pF+1TTL 1)CL=30pF+1TTL
K6L0908V2A-70 Family, K6L0908U2A-85 Family
CMOS SRAM
CL1)
Including scope capacitance
CHARACTERISTICS (K6L0908V2B Family:Vcc=3.0~3.6V, K6L0908U2B Family:Vcc=2.7~3.3V,
Commercial product:TA=0 70°C, Extended product:TA=-25 85°C, Industrial product:TA=-40 85°C)
Speed Bins Parameter List Symbol Read cycle time Address access time Chip select output Output enable valid output Read Chip select low-Z output Output enable low-Z output Chip disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write Write pulse width Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tOLZ tOHZ tWHZ 70ns 85ns 100ns Units
DATA RETENTION CHARACTERISTICS
Item data retention K6L0908V2A-B K6L0908V2A-D K6L0908V2A-F Data retention current K6L0908U2A-B K6L0908U2A-D K6L0908U2A-F Data retention set-up time Recovery time tSDR tRDR Symbol
Test Condition Vcc-0.2V
Unit
Vcc=3.0V, 1Vcc-0.2V, CS2Vcc-0.2V CS20.2V
data retention waveform
Vcc-0.2V, Vcc-0.2V( controlled) 0.2V(CS2 controlled)
Revision February 1998
K6L0908V2A, K6L0908U2A Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
Address Data Previous Data Valid
CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision February 1998
K6L0908V2A, K6L0908U2A Family
TIMING WAVEFORM WRITE CYCLE(1)
Controlled)
CMOS SRAM
Address tCW(2) tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
TIMING WAVEFORM WRITE CYCLE(2) (CS1
Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision February 1998
K6L0908V2A, K6L0908U2A Family
TIMING WAVEFORM WRITE CYCLE(3)
(CS1 Controlled)
CMOS SRAM
Address tAS(3) tCW(2) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap high write begins latest transition among goes low, going high going write earliest transition among going high, going going high, measured from begining write write. measured from going going high write. measured from address valid beginning write. measured from write address change. tWR(1) applied case write ends going high tWR(2) applied case write ends going low.
DATA RETENTION WAVE FORM
controlled
3.0/2.7V tSDR Data Retention Mode tRDR
2.2V CS1VCC 0.2V
controlled
3.0/2.7V tSDR
Data Retention Mode
tRDR
0.4V
CS20.2V
Revision February 1998
K6L0908V2A, K6L0908U2A Family
PACKAGE DIMENSIONS
SMALL OUTLINE PACKAGE (525mil)
CMOS SRAM
Units: millimeter(inch)
0~8°
14.12±0.30 0.556±0.012
11.43±0.20 0.450±0.008
13.34 0.525
20.87 0.822 20.47±0.20 0.806±0.008
2.74±0.20 0.108±0.008 3.00 0.118
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.80±0.20 0.031±0.008
0.10 0.004
+0.100 -0.050 0.016 +0.004 -0.002
0.71 0.028
0.41
1.27 0.050
0.05 0.002
THIN SMALL OUTLINE PACKAGE TYPE (0820F)
0.20
+0.10 -0.05
0.008+0.004 -0.002
20.00±0.20 0.787±0.008 8.40 0.331 8.00 0.315 0.25 0.010
0.50 0.0197
1.00±0.10 0.039±0.004 1.20 0.047
+0.10 -0.05 0.006+0.004 -0.002
0.05 0.002
0.25 0.010
18.40±0.10 0.724±0.004
0.15
0~8°
0.45 ~0.75 0.018 ~0.030
0.50 0.020
Revision February 1998
0.10 0.004MAX
K6L0908V2A, K6L0908U2A Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (0813.4F)
+0.10 -0.05 0.008+0.004 -0.002
CMOS SRAM
Units: millimeter(inch)
0.20
13.40±0.10 0.528±0.008 8.40 0.331 8.00 0.315 0.25 0.010
0.50 0.0197
1.00±0.10 0.039±0.004 1.20 0.047
0.05 0.002
0.15
+0.10 -0.05
0.006+0.004 -0.002 0~8°
0.45 ~0.75 0.018 ~0.030
0.50 0.020
THIN SMALL OUTLINE PACKAGE TYPE (0813.4R)
0.20
+0.10 -0.05
0.008+0.004 -0.002
13.40±0.10 0.528±0.008 8.40 0.331 8.00 0.315 0.25 0.010
0.50 0.0197
1.00±0.10 0.039±0.004 1.20 0.047 11.80±0.10 0.465±0.004
+0.10 -0.05 0.006+0.004 -0.002
0.25 0.010
0.15
0~8°
0.45 ~0.75 0.018 ~0.030
0.50 0.020
0.10 0.004
0.10 0.004 0.05 0.002
0.25 0.010
11.80±0.10 0.465±0.004
Revision February 1998

64Kx8 Power Voltage CMOS Static CMOS SRAM Revision History

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