64Kx8 Power CMOS Static CMOS SRAM Revision History Revi

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64Kx8 Power CMOS Static CMOS SRAM Revision History Revi

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K6L0908C2A Family
64Kx8 Power CMOS Static
CMOS SRAM
Revision History
Revision
History
Initial draft Revision Finalize Revision 45ns part with 30pf test load. Revision Change Data Sheet format data sheets industrial commercial product Revision Change Data Sheet format Remove 45ns part from commercial product 100ns part from industrial product Remove power part form TSOP package
Draft Data
Novemer 1993 1994 December 1994 August 1995
Remark
Design target Preliminary Final Final
April 1996
Final
January 1998
Final
attached data, sheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision January 1997
K6L0908C2A Family
64Kx8 Power CMOS Static
FEATURES
Process Technology: Poly Load Organization: 64Kx8 Power Supply Voltage: 4.5~5.5V Data Retention Voltage: 2V(Min) Three state output Compatible Package Type: 32-SOP-525, 32-TSOP1-0820F
CMOS SRAM
GENERAL DESCRIPTION
K6L0908C2A families fabricated SAMSUNGs advanced CMOS process technology. families support various operating temperature ranges have various package types user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6L0908C2A-L K6L0908C2A-B K6L0908C2A-P K6L0908C2A-F Industrial (-40~85°C) Operating Temperature Range Speed Standby (ISB1, Max) 100µA 20µA 70ns 100µA 50µA 70mA 32-SOP 32-TSOP1-F Operating (ICC2, Max) Type
Commercial (0~70°C) 5.5V
55/70ns
DESCRIPTION
I/O1 I/O2 I/O3 I/O8 I/O7 I/O6 I/O5 I/O4 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
32-SOP
select
32-TSOP Type1 Forward
Memory array rows columns
I/O1 I/O8
Data cont
Circuit Column select
Data cont
Name CS1, A0~A15 I/O1~I/O8
Function Chip Select Inputs Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Power Ground Connection
Control Logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision January 1997
K6L0908C2A Family
PRODUCT LIST
Commercial Temperature Products(0~70°C) Part Name K6L0908C2A-GL55 K6L0908C2A-GB55 K6L0908C2A-GL70 K6L0908C2A-GB70 K6L0908C2A-TB55 K6L0908C2A-TB70 Function 32-SOP, 55ns, L-pwr 32-SOP, 55ns, LL-pwr 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP1-F, 55ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr K6L0908C2A -TF70
CMOS SRAM
Industrial Temperature Products(-40~85°C) Part Name K6L0908C2A-GP70 K6L0908C2A-GF70 Function 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout Mode Deselected Deselected Output Disabled Read Write Power Standby Standby Active Active Active
means dont care.(Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Soldering temperature time Symbol VIN,VOUT TSTG TSOLDER Ratings -0.5 -0.5 260°C, 10sec(Lead Only) Unit Remark K6L0908C2A-C K6L0908C2A-I
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision January 1997
K6L0908C2A Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol -0.53)
CMOS SRAM
Vcc+0.5V
Unit
Note Commercial Product TA=0 70°C, unless otherwise specified Industrial Product TA=-40 85°C, unless otherwise specified Overshoot CC+3.0V case pulse width30ns Undershoot -3.0V case pulse width30ns Overshoot undershoot sampled, 100% tested
CAPACITANCE1)(f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ICC1 Average operating current ICC2 Output voltage Output high voltage Standby Current(TTL) Standby Current (CMOS) K6L0908C2A-L/-B ISB1 K6L0908C2A-P/-F VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL, VIO=Vss IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH Cycle time=1µs, 100% duty, IIO=0mA CS10.2V, CS2VCC-0.2V, VIN0.2V VINVcc -0.2V
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, 2=VIH, VIN=VIH
Test Conditions
Unit
IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other inputs =VIH Power CS1Vcc-0.2V, CS2Vcc-0.2V CS20.2V Power Other inputs Power Power
Revision January 1997
K6L0908C2A Family
OPERATING CONDITIONS
TEST CONDITIONS( Test Load Input/Output Reference)
Input pulse level 2.4V Input rising falling time Input output reference voltage :1.5V Output load(see right) CL=100pF+1TTL
CMOS SRAM
CL1)
Including scope capacitance
CHARACTERISTICS (Vcc=4.5~5.5V,
Parameter List
K6L0908C2A-C Family:T 70°C, K6L0908C2A-I Family:TA=-40 85°C) Speed Bins Symbol 55ns 70ns Units
Read cycle time Address access time Chip select output Output enable valid output Read Chip select low-Z output Output enable low-Z output Chip disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write Write pulse width Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z
tCO1, tCO2 tOLZ tOHZ tWHZ
DATA RETENTION CHARACTERISTICS
Item data retention K6L0908C2A-L/-B Data retention current K6L0908C2A-P/-F Data retention set-up time tSDR Recovery time tRDR Vcc=3.0V CS1Vcc-0.2V CS2Vcc-0.2V CS20.2V Symbol
Test Condition Vcc-0.2V L-Ver LL-Ver L-Ver LL-Ver
Unit
data retention waveform
CS1Vcc-0.2V, Vcc-0.2V( controlled) CS20.2V(CS2 controlled).
Revision January 1997
K6L0908C2A Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
Address Data Previous Data Valid
CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision January 1997
K6L0908C2A Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
TIMING WAVEFORM WRITE CYCLE(2) (CS1
Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision January 1997
K6L0908C2A Family
TIMING WAVEFORM WRITE CYCLE(3)
(CS2 Controlled)
CMOS SRAM
Address tAS(3) tCW(2) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap CS1, high write begins latest transition among goes low, going high going write earliest transition among going high, going going high, measured from begining write write. measured from going going high write. measured from address valid beginning write. measured from write address change. tWR(1) applied case write ends going high tWR(2) applied case write ends going low.
DATA RETENTION WAVE FORM
controlled
4.5V tSDR Data Retention Mode tRDR
2.2V CS1VCC 0.2V
controlled
4.5V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision January 1997
K6L0908C2A Family
PACKAGE DIMENSIONS
SMALL OUTLINE PACKAGE (525mil)
CMOS SRAM
Units: millimeter(Inch)
0~8°
11.43±0.20 0.450±0.008
20.87 0.822 20.47±0.20 0.806±0.008
2.74±0.20 0.108±0.008 3.00 0.118 0.20 +0.10 -0.05 0.008+0.004 -0.002 0.80±0.20 0.031±0.008
0.10 0.004
+0.100 -0.050 +0.004 0.016 -0.002
0.71 0.028
0.41
1.27 0.050
0.05 0.002
32-THIN SMALL OUTLINE PACKAGE TYPE (0820F)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.00±0.20 0.787±0.008 8.00 0.315 0.25 0.010
8.40 0.331
0.50 0.0197
1.00±0.10 0.039±0.004 1.20 0.047
13.34 0.525
14.12±0.30 0.556±0.012
0.05 0.002
0.25 0.010
18.40±0.10 0.724±0.004
0~8°
0.45 ~0.75 0.018 ~0.030
0.50 0.020
Revision January 1997
0.10 0.004
+0.10 -0.05 0.006+0.004 -0.002
0.15

64Kx8 Power CMOS Static CMOS SRAM Revision History Revi

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