WORKAROUND: None Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part:
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Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 68332.V 00F98R Modules Current Module Revision CPU32.12 QSM.9A SIM.12_3 STDPORT.10 TPU.6_3 TPUSRAM_2048A.6.2 VCO.7 MODULAR_AR_12 Customer Information 68332.V DESCRIPTION: After power-up (Vdd min.) MCU, input/output output-only port pins modules other than integration module indeterminate state (depends ramp conditions). Input/output pins these modules output mode (instead high impedance) short time, which create conflict with external drive logic. (Previously 68332:005) WORKAROUND: known state required these pins, before port initialization period, external reset control logic must condition these lines. MODULAR_AR_220 Customer Erratum CPU32.12 DESCRIPTION: When there error released write cycle cycle re-run instruction immediately before instruction, then re-run cycle write, read instead. Most applications experience this problem since software usually designed interpret recover from errors. common reaction error abort program flow, report error occurrence, then attempt restart application. Applications designed that need concerned with this problem. (Previously CPU32:061).
WORKAROUND: None Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_213 Customer Erratum CPU32.12 DESCRIPTION: When there error second word released longword write cycle immediately before instruction, then bits special status word (SSW) incorrect. bits represent cycle instead released write cycle. cycle which error will re-run return from exception. Most applications experience this problem since software usually designed interpret recover from errors. common reaction error abort program flow, report error occurrence, then attempt restart application. Applications designed that need concerned with this problem. (Previously CPU32:053). WORKAROUND: Sometimes possible determine this fault condition from stack program contents. When released write happens byte write supervisor space, looks exactly like error write cycle, released write address same address, fault address different between cases. error exception handler resolve situation looking size, R/W, function code information, when that fails; examining faulted address determining whether same address that would generated instruction return program counter. case released write error, then setting clearing should correct action (with RTE), after resolving original cause error. MODULAR_AR_222 Customer Erratum CPU32.12 DESCRIPTION: does properly execute DBcc instruction under following condition. DBcc about fetched second time, loop mode possible, slow 8-bit memory) that DBcc offset fetched second time, looped instruction gets released write error, then DBcc instruction executed. return points looped instruction, which will executed once often. (was CPU32:063).
WORKAROUND: loop mode possible, force software loop mode placing prior DBcc instruction. Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_224 Customer Erratum CPU32.12 DESCRIPTION: When BERR terminates operand write cycle, CPU32 enters BERR exception right after BERR. However, stack, next instruction addr. shows wrong address. cause this condition, slow least clock cycle). This results running operand write cycle more time than should (was CPU32:066). WORKAROUND: Ensure that loop mode entered when there possibility released write error. MODULAR_AR_812 Customer Erratum CPU32.12 DESCRIPTION: acknowledge breakpoint, CPU32 performs read from space address $1E. cycle terminates normally, instruction execution continues with next instruction, breakpoint request occurred. cycle terminated BERR, begin exception processing. breakpoint occurred while loop mode, breakpoint acknowledge cycle terminates normally, does continue with next instruction execution. (Previously CPU32:071). WORKAROUND: Always terminate breakpoint acknowledge cycle with BERR (bus Error) MODULAR_AR_206 Customer Erratum CPU32.12 DESCRIPTION: internal arbitrated away just before last cycle MOVEM memory, MOVEM followed other instructions which write external memory (known problem instructions are: MOVE Rn,-(An) LINK), then data written last cycle MOVEM will same data subsequent instruction (ex: MOVE). other words, next instruction (MOVE) started execution early. Internal arbitration occur
following situations:1. external request occurs with SHEN[1:0] or2. on-chip alternate master (ex: DMA) module takes mastership or3. external request occurs when Factory Test (Slave) mode enabled.(Previously CPU32:051). WORKAROUND: external requests occur, ensure SHEN[1:0] anything except %11.2. alternate master (DMA) present on-chip, operating, arrange instruction sequences prevent occurrence MOVEM followed another instruction which writes external memory (MOVE Rn,-(An) LINK). recommended place after MOVEM.3. Factory Test (Slave) mode should used. Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_216 Customer Erratum CPU32.12 DESCRIPTION: When jump branch address occurs there pending error, address error exception incorrectly taken error exception taken. (Previously CPU32:056) WORKAROUND: jump branch addresses when errors occur. MODULAR_AR_210 Customer Erratum CPU32.12 DESCRIPTION: IACK cycle (with AVEC asserted) terminated normal BERR, Spurious Interrupt exception will taken expected. BERR IACK cycle LATE ERROR (BERR asserted after AVEC), then Type error exception (Faults during exception processing) will taken, this case Status Register stack frame will corrupted there recovery from exception. (Previously CPU32:045). WORKAROUND: allow LATE BERR during IACK cycles that terminated with AVEC.
MODULAR_AR_221 Customer Erratum CPU32.12 DESCRIPTION: When exiting BDM, FREEZE negated after DSI/IFETCH signal turns around from input output. This means that external development system could driving while still driving IFETCH. (Previously CPU32:062). WORKAROUND: Provide sufficient isolation externally contention cause system problems. MODULAR_AR_975 Customer Information CPU32.12 DESCRIPTION: When spurious interrupt awakens from LPSTOP, spurious interrupt handler called, sits idle until another detected. effect same STOP instruction actually executed, from point that spurious interrupt occurs, instead LPSTOP instruction. WORKAROUND: power consumption important LPSTOP used, allow spurious interrupts occur during LPSTOP state. Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_218 Customer Information CPU32.12 DESCRIPTION: IRQ7 asserted released just before IACK cycle then reasserted, only IRQ7 interrupt taken. (Previously CPU32:058). WORKAROUND: NONE
MODULAR_AR_1018 Customer Information CPU32.12 DESCRIPTION: stack frame incorrect when error occurs (internal external BERR asserted) write cycle immediately followed "TRAP instruction. WORKAROUND: Avoid error occurrence when "TRAP run. error cannot avoided, insert "NOP" before running "TRAP #n", modify return address error exception frame direct back correct flow. MODULAR_AR_1020 Customer Information CPU32.12 DESCRIPTION: Incorrect operation occurs result following sequence conditions: error address error condition occurs during operand cycle MOVEM instruction. After exception processing, re-fetches MOVEM instruction. re-fetch cycle MOVEM instruction terminated error condition, error condition occurs. WORKAROUND: allow error condition occur fetch cycle MOVEM instruction, that fetch occurs after exception processing error address error MOVEM operand cycle. MODULAR_AR_226 Customer Information CPU32.12 DESCRIPTION: AVEC DSACK signals asserted simultaneously terminate IACK cycle, then DSACK signal higher priority. (Previously CPU32:069). WORKAROUND: None
Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_818 Customer Erratum SIM.12_3 DESCRIPTION: Under following conditions showcycles will truncated: showcycles external arbitration enabled, asserted immediately before clock edge from which asserts show cycle. data drive time show cycle will overlap front alternate master tenure clock asserted during time showcycle data driven). WORKAROUND: Disable show cycles when alternate master activity possible2. Delay assertion system clock, delay alternate master from driving date clock after asserts. MODULAR_AR_664 Customer Erratum SIM.12_3 DESCRIPTION: Unusual system operation occur when arbitration used combination with additional system configuration settings timing. example behavior, chip selects assert while external granted away they programmed respond interrupt stack addresses) interrupt stack corrupted. Reset only recover once this occurs.Conditions initiate:1. SHEN bits %10.and2. asserted coincident with IACK cycle.(BR assertion within range before after clockrelative falling edge CLKOUT when asserts.)and3. IACK cycle terminated with external AVEC.(Previously IM:092). WORKAROUND: SHEN=%11 prevent from running cycles while external grantedaway.or2. assert coincident with IACK.or3. external AVEC. chip select assert internal AVEC external interrupts. MODULAR_AR_667 Customer Erratum SIM.12_3 DESCRIPTION: Under certain conditions masked interrupt occur with incorrect level. conditions are: external unmasked interrupt must occur coincident with internal masked periodic interrupt (PIT). Also, previous above interrupts, external interrupt line same level masked interrupt must have been asserted remain asserted. Example sequence
cause problem:1. interrupt mask 5;2. level 2;3. Hold IRQ2 line low.4. Assert valid interrupts (asserting IRQ7) exception taken pending.(Previously IM:095) WORKAROUND: allow matching levels external pin. Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_331 Customer Erratum SIM.12_3 DESCRIPTION: RESET assertion time specification (#77) clocks (tcyc) minimum. However, current version this module requires RESET asserted until current cycle progress completes. (Previously IM:139) WORKAROUND: Assert RESET clock cycles longer than present timeout period monitor (BMT field SYPCR register). This will result internal reset, independent other system conditions (Bus Monitor does need enabled). MODULAR_AR_661 Customer Erratum SIM.12_3 DESCRIPTION: power-up, integration module pins should initialize high impedance state. following pins may, however, drive outputs until first CLKOUT edge occurs initialize internal logic into high impedance state. Port D[15:0] HALT (open Drain). (Previously IM:086). WORKAROUND: external conflicts result system problems these pins, isolate these pins from external devices using series resistor buffer offending pin. MODULAR_AR_635 Customer Erratum SIM.12_3 DESCRIPTION: used either mode external clock mode with prescalar enabled (PTP PITR register set), clock (crystal EXTAL/512 external clock mode).
PIfield PITR register written zero, followed immediately nonzero value, then LPSTOP entered before full period clock source, timer will never decrement which prevent exiting LPSTOP using timeout. (Previously IM:082). WORKAROUND: user wishes stop restart with time value writing zero followed value PIfield, user should delay entering LPSTOP least 32kHz clock period after writing value. Alternatively, user update PIfield with value without first stopping counter (writing zero PIfield). this case, timer will continue counting down original time value before updating value. Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_639 Customer Erratum SIM.12_3 DESCRIPTION: power-up, chip select pins drive (asserted) until first CLKOUT edge occurs. False writes result power does have pull-up resistor. line high impedance state power while reset asserted. (Previously IM:085). WORKAROUND: Insure external writes cannot occur power pulling pin. MODULAR_AR_876 Customer Information SIM.12_3 DESCRIPTION: When internal clock system used (MODCK=0) RESET negation) then following behavior occur. During power down, external clock degrades such that longer meets Timing Specification External Clock Input High/Low Time (tXCHL), then Input/Output Output-only pins integration module other modules become active. Assertion external RESET under these conditions does guarantee level RESET will internally recognized internal RESET signal negated under these anomalous conditions. internal RESET signal used hold Input/Output Output-only pins their respective high impedance mode. on-chip used clock source there problem will meet specifications minimum Vdd.
WORKAROUND: External Clock used, then insure that External Clock signal does degrade violate specifications power goes down. Alternately, protect external devices that damaged (ex: non-volatile memories). Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_930 Customer Information SIM.12_3 DESCRIPTION: Several conditions combined introduce apparent Periodic Interrupt Timer (PIT) clock errors. clock error occurs LPSTOP mode entered exited periodically using PIT, system clock minimum (PLL control bits SYNCR register Y=0, prior entry LPSTOP mode system clock maximum LPSTOP exit (STSIM=0, LPSTOP, therefore must re-lock). Also, exiting from LPSTOP, will held until re-locked. Variations clock period appear counter missing clocks (the clocked EXTAL reference clock LPSTOP, STSIM During normal operation (not LPSTOP) counter clock source (EXTAL) synchronized logic system clock (CLKOUT). combination re-lock time, frequency clock source (too near internal reference), synchronization, results this behavior. (Previously IM:097 Issue #653). WORKAROUND: Restrict minimum frequency least times minimum possible reference frequency (PLL control bits SYNCR register Y=0, =%01) higher. This restriction applies system clock toggled from frequency prior LPSTOP entry STSIM back maximum exit LPSTOP periodically using controlling source. problem only seen when switching clock frequency that close reference (EXTAL) clock frequency. MODULAR_AR_662 Customer Information SIM.12_3 DESCRIPTION: E-Clock synchronized chip selects (MODE=1) used combination with peripherals which retry cycles addressing problem occur. Chip selects synchronous E-clock support, configured port used with peripheral connected upper data (D15:8 BYTE upper). problem occurs during word access peripheral, combination with retry (terminate cycle with BERR HALT) being requested device second cycle access. Under this condition, second cycle will retried, [A0] will incorrect. (Previously IM:088)
WORKAROUND: attempt retry chip selects supporting synchronous E-clock cycles ports. Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_908 Customer Information SIM.12_3 DESCRIPTION: documentation state RMC/PE3, SIZ[1:0]/PE[7:6] DS/PE4 pins inconsistent between users manuals (MC68.USM) SIM/SCIM reference manuals (Module.RM). users manuals indicate pins high impedance state while RESET asserted, which correct. SCIM/SIM manuals indicate state determined data configuration while RESET asserted, which correct. WORKAROUND: Refer documentation users manuals RESET state these pins. MODULAR_AR_658 Customer Information SIM.12_3 DESCRIPTION: loss clock reference feature supported function. Disregard position SYNCR register (previously SLIMP bit), this reserved. Insure that position (previously RSTEN bit) SYNCR register always written it's RESET state (This previously IM:077). WORKAROUND: rely loss clock LIMP mode feature. Advanced CUSTOMER ERRATA INFORMATION SHEET Page Part: 68332.V Mask Set: 00F98R Division Report Generated: 17:37 MODULAR_AR_800 Customer Information VCO.7 DESCRIPTION: some Phase Lock Loop (PLL) documentation three component filter from VDDSYN recommended (18K resistor series with capacitor between VDDSYN XFC,
series combination parallel with 3300 capacitor loop multiplier 512). been determined with this three component filter, presence external leakage excess that provided Ohm) pin, result exiting RESET power During this condition, output frequency CLKOUT target value, lock detect logic does detect lock continues cause RESET assertion. Versions integration module that configured either slow fast (Typ. 32.768 4.194 MHz) crystal source option same filter component values since internal reference frequency always slow (ex: 32.768 kHz). Also, leakage from must excess that provided resistor meet jitter specifications (with filter, refer Electrical Characteristics section device users's manual). enabled (MODCK=0 RESET) then filter required. (Previously IM:179 VCO:051). WORKAROUND: three component filter XFC. originally documented filter (single capacitor from VDDSYN supply pin). MODULAR_AR_986 Customer Information VCO.7 DESCRIPTION: "PLL Lock Time" (tlpll) specification documented This value applies time lock after changing bits synthesizer control register (SYNCR) while running, period required lock after LPSTOP exited. This specification does apply warm start-up (with VDDSYN applied crystal stable, followed power application). warm start-up period maximum (This previously IM:098, VCO:059, AR_806 some cases AR_987). WORKAROUND: "PLL Lock Time" (tlpll) specification. Revision 0.0, last update: 1998
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