MPC860T enhanced version MPC860 with added 10/100 Ethernet capability.

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MPC860T enhanced version MPC860 with added 10/100 Ethernet capability.

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860T Design Advisory Rev.
MPC860T enhanced version MPC860 with added 10/100 Ethernet capability. Although additional Ethernet connectivity does impose limit protocols available other (slower) serial channels 860T, Fast Ethernet Controller (FEC) does share resources with other serial controllers virtual IDMA controller. working with current revision Fast Ethernet microcode 860T silicon (Rev. B.2), designer should take into account bottleneck that introduced this shared resource particular 860T configurations must aware potential worst-case latency that experience during certain boundary conditions operation. this paper, will present example scenarios illustrating these worst-case conditions give system design suggestions eliminating potential problems. 860T system designer also needs recognize that slow serial channels experience some throughput limitations result added latency that introduces bus. this paper, will quantify impact that operation slow serial channel latency describe mechanism determining whether 860T support proposed level loading.
Freescale Semiconductor, Inc.
Internal Arbitration
interdependence various on-chip controllers heart performance issues facing 860T designer. Therefore, order understand impact operation 860T system, first need consider mechanism used other serial channels share on-chip resources. behalf SCCs, SMCs, SPI, I2C, IDMA) arbitrate access SDMA hardware? Second, important know engine then shares internal U-bus with other internal masters 860T. other words, does SDMA controller arbitrate bus? will start with subject arbitration SDMA hardware. general, operate round-robin fashion gaining access SDMA. both attempt access SDMA once, wins first arbitration then round-robin follows. Next, SDMA arbitrates U-bus order transfer either 10/100 Ethernet data slow serial channel data perform IDMA operation. SDMA requests behalf either CPM. Since SDMA higher arbitration priority than CPU/caches, will (even also request) single-beat transaction burst. After transfer, SDMA then yields transaction, which, depending other requesting master(s), single-beat transaction burst. yielding after each transaction, SDMA allows other masters share (assuming some statistics about cache utilization) prevents from stalling.
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CPU, FEC, have requests, then mastership would alternately pass from SDMA back SDMA, etc. Each time SDMA master, access granted round-robin fashion (for slow serial channels IDMA). accesses occur following sequence: SDMA SDMA SDMA etc. When (with caches active) master, accesses cacheable memory will bursts. contrast, when SDMA master, transaction burst, depending source request. IDMA requests SDMA resource generate bursts from memory data transfers (although buffer descriptor accesses single-beat transactions). other hand, requests from behalf SCCs, SMCs, SPI, controllers will generate only single-beat transactions. Initially, will assume that IDMA source requests (which turn arbitrates SDMA). including burst transfers IDMA, rather than single-beat transfers slow serial controllers, will arrive better representation worst case latency FEC. Now, looking more specifically source request SDMA, accesses occur following sequence: IDMA etc.
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Timing Analysis: Base Case
Next, will consider capability interface 50MHz 860T, utilizing SDRAM memory system with equal access timing burst reads burst writes: 5-1-11. (Note: memory system with longer access time burst reads than burst writes, could read timing accesses illustrate worst case instantaneous access time. Alternatively, could average read write timing. will consider this choice examples section ahead.) system, burst transfer words (=16 bytes) from memory takes 8cycles 20ns/cycle 160ns. Thus, 860T's interface capable transferring byte every 10ns. Now, will focus requirements FEC. Full-duplex Fast Ethernet 200Mbps data rate, demand byte transferred to/from memory every 40ns. (Similarly, half-duplex Fast Ethernet 100Mbps data rate, demand byte every 80ns.) need determine whether 5-1-1-1 SDRAM access timing, sufficient support demand full- half-duplex operation) well demands other internal masters (e.g. CPU, CPM) 860T. begin calculations considering worst case latency conditions that will experience, will determine whether still support transfer rate byte every 40ns. Under worst case conditions FEC, would transfer every time SDMA yielded after transaction. addition, would request SDMA resource each time round-robin between returns CPM. result, mastership would proceed described earlier:
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IDMA etc. Adding analysis number cycles required each master complete burst transaction, using 5-1-1-1 timing from above, have following sequence cycles: IDMA etc. From this example, that makes burst transfer every cycles, data rate byte every 40ns: bytes cycles)*(50x10^6 cycles/sec)=1byte/40ns first glance, might that this rate exactly what required full-duplex Fast Ethernet, (and even exceeds requirement half-duplex Fast Ethernet), therefore conclude that this system will work. other hand, have considered system boundary conditions, namely, instantaneous effect accesses Fast Ethernet buffer descriptors latency seen FEC. Each time needs close current buffer descriptor open one, performs three single-beat accesses memory: access write status back current more read next same process occurs both buffer descriptors. Furthermore, accesses have higher priority than data transfers, accesses will latency described above burst transfers Fast Ethernet data. When configured full-duplex Fast Ethernet, transmitter receiver will alternate their memory accesses. worst case added latency accesses occurs when must opened both same time. (Even with half-duplex Fast Ethernet, system still experience simultaneous demand buffer descriptors. Consider scenario which begins transmission frame immediately after completes reception another frame. this case, starts filling FIFO with data from memory while still completing transfer received data from FIFO memory.) FEC's transmitter just used mastership bursting data from memory into FIFO, then receiver will have next available data access time. addition, opening will cause single-beat accesses memory (three three consume next times that becomes master. Keeping mind that single-beat accesses 5-1-1-1 memory system take cycles each, would following sequence cycles bus: FEC-Txdata IDMA FEC-Rxdata IDMA FEC-TxBD IDMA FEC-RxBD IDMA FEC-TxBD IDMA FEC-RxBD IDMA FEC-TxBD IDMA FEC-RxBD IDMA loop lines until buffer descriptor needs service again. this boundary case, FEC's FIFO obtains burst data total cycles: 6*(5+8+8+8) cycles. This translates into worst case latency cycles 50*10^6 cycles/sec 4.76us between successive accesses Fast Ethernet transmit data. Generally, FEC's FIFO absorb this latency when occurs middle transmission frame. However, this string buffer descriptor accesses occurs early frame, when FIFO contains minimum number bytes ready
Freescale Semiconductor, Inc.
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transmission, excessive latency bringing data from memory into FIFO could cause FIFO underrun. determine whether 4.76us excessive latency, must consider number bytes FIFO, well transmit data rate line (100Mbps). design, will begin transmission frame until FIFO contains bytes user data. Adding these bytes bytes preamble generated hardware, prepared transmit exactly byte-times, i.e. duration collision window start frame. size data buffer this particular frame equal bytes, (which size user data field minimum length frame), then accesses begin just when FIFO bytes available transmission. this case, while buffer descriptor accesses take place, FIFO will drain empty state 5.12us: 5.12
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Since latency 4.76us less than FIFO's drain time 5.12us, FIFO will underrun these conditions. alleviate need this margin, however, system should make larger buffers. This step would only minimize number times that buffer descriptors must opened closed (thereby reducing system overhead), would also reduce number instances that boundary case above could occur.
Timing Analysis: SDRAM necessary MPC860T System
Suppose that cost requirements design call 40MHz 860T DRAM, rather than 50MHz system with SDRAM, described above. will memory interface timing affect risk FIFO underrun? will begin making assumptions. First, assume that access timing memory system follows: Burst Read: Burst Write: Single Beat Read: Single Beat Write: 4-2-2-2 3-2-2-2
Second, since access timing differs read write, must choose appropriate value each cycle controlled various internal masters 860T. will Burst Read value clocks) accesses, since this represents worst case. will average Burst Read Burst Write values (9.5 clocks) IDMA accesses, since each IDMA transfer must include write every read. cycles, will each Burst Read (10), Burst Write (9), Single Read (4), Single Write timing values where appropriate. With these assumptions mind, proceed timing analysis 40MHz 860T system with DRAM, during boundary case which buffer descriptor accesses intervene between transmit data accesses: FEC-Txdata Read (10) (10) IDMA (9.5) (10) FEC-Rxdata Write (10) IDMA (9.5) (10) FEC-TxBD Write (10) IDMA (9.5) (10) FEC-RxBD Write (10) IDMA (9.5) (10)
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FEC-TxBD Read (10) IDMA (9.5) (10) FEC-RxBD Read (10) IDMA (9.5) (10) FEC-TxBD Read (10) IDMA (9.5) (10) FEC-RxBD Read (10) IDMA (9.5) (10) loop lines until buffer descriptor needs service again. boundary case, FEC's FIFO obtains burst data total cycles: 39.5 38.5 2*(3+10+9.5+10) 4*(4+10+9.5+10) cycles. This translates into worst case latency cycles 40*10^6 cycles/sec 6.93us between successive accesses Fast Ethernet transmit data. comparison this value with FIFO drain time 5.12us reveals that 40MHz implementation would also experience possibility FIFO underruns.
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Before accepting FIFO underrun certainty design, however, should consider some redesign alternatives that could potentially prevent underrun event altogether. will analyze impact each following four changes: Replace DRAM memory system with SDRAM external controller instead 860's IDMA faster clock speed
Redesign Option SDRAM
Beginning with 40MHz design incorporating full-duplex Fast Ethernet, consider single system change area memory. Using SDRAM timing 5-1-1-1 reads writes, which supported 40MHz design, arrive following timing sequence: FEC-Txdata Read IDMA FEC-Rxdata Write IDMA FEC-TxBD Write IDMA FEC-RxBD Write IDMA FEC-TxBD Read IDMA FEC-RxBD Read IDMA FEC-TxBD Read IDMA FEC-RxBD Read IDMA loop lines until buffer descriptor needs service again. With these values, burst data occurs every cycles, latency cycles 40*10^6 cycles/sec 5.95us. This value still exceeds FIFO drain time, must conclude that upgrading from SDRAM sufficient eliminate FIFO underrun risk.
Redesign Option Eliminate IDMA
support system's IDMA needs outside 860T, then CPM's internal mastership tenures used solely serial channel activity. Since accesses supporting serial channels always single beat accesses, rather than bursts, alter baseline case replacing IDMA burst timing (9.5 cycles average burst read burst write) with single-beat read timing cycles. read access time rather than average read write (3.5 cycles) order evaluate worst case latency during this boundary condition:
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FEC-Txdata Read (10) (10) non-IDMA (10) FEC-Rxdata Write (10) non-IDMA (10) FEC-TxBD Write (10) non-IDMA (10) FEC-RxBD Write (10) non-IDMA (10) FEC-TxBD Read (10) non-IDMA (10) FEC-RxBD Read (10) non-IDMA (10) FEC-TxBD Read (10) non-IDMA (10) FEC-RxBD Read (10) non-IDMA (10) loop lines until buffer descriptor needs service again. timing analysis yields total cycles cycles 40*10^6 cycles/sec 5.825us latency Fast Ethernet transmit data. Thus, eliminating support IDMA sufficient eliminate potential FIFO.
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Redesign Option 50MHz 860T
maintain DRAM system increase 860T's clock speed, arrive timing pattern memory interface: Burst Read: Burst Write: Single Beat Read: Single Beat Write: 5-2-2-2 3-2-2-2
access sequence with timing follows: FEC-Txdata Read (11) (11) IDMA (10) (11) FEC-Rxdata Write (11) IDMA (10) (11) FEC-TxBD Write (11) IDMA (10) (11) FEC-RxBD Write (11) IDMA (10) (11) FEC-TxBD Read (11) IDMA (10) (11) FEC-RxBD Read (11) IDMA (10) (11) FEC-TxBD Read (11) IDMA (10) (11) FEC-RxBD Read (11) IDMA (10) (11) loop lines until buffer descriptor needs service again. Once again, analysis reveals that FIFO underrun eliminated with increase clock speed. latency cycles 50*10^6 cycles/sec 6.04us, which still exceeds 5.12us. have just completed analysis various redesign options their impact risk FIFO underrun. briefly look impact latency FEC's receive path. this direction, factor related FIFO overrun simply FIFO size, which defaults bytes user-programmable. (The registers interest FIFO Receive Bound Register, FIFO.R_BOUND, FIFO Receive Start Register, FIFO.R_FSTART.) contrast path, path withstand significant latency before FIFO fills capacity. transfer receive data memory begins soon collision window bytes) data available FIFO. Therefore, FIFO empty when frame reception begins, FIFO size equal default, then FIFO receive bytes
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beyond collision window before access latency would pose threat FIFO overrun. Thus, although there boundary condition receive path, FIFO underrun risk greater concern.
Performance Analysis
Returning transmit case, complicating matters further, consider scenario which IDMA only controller making requests access SDMA resource. add, example, 10BaseT channel SCC1, need consider whether FEC, IDMA, data transfers will cause excessive latency SCC. Ignoring traffic moment, know that 50MHz support 10BaseT channels. (Using Table Appendix Serial Performance User's Manual, utilization with half-duplex 10BaseT channels [4*(10/22)*(25MHz/50MHz)]=91%.) This assessment based assumption that will experience latency greater than cycles between accesses. Such assumption reasonable when CPU, caches, IDMA only other internal masters requesting (i.e. active FEC), reasons: SDMA, arbitrating behalf CPM, higher priority than caches, when IDMA programmed have lower request priority within than SCCs, serial data transfers occur whenever mastership. 860T, however, which SCCs must alternate SDMA, both must share with CPU, regularly experience latency greater than cycles. result, maximum loading CPM, documented Serial Performance Appendix User's Manual, must derated. order ensure adequate access SCCs, thereby prevent serial channel FIFO overruns underruns, system designer should certain that planned loading does exceed percentage stated Table (below) corresponding access latency: Access Latency (cycles) Maximum Loading
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Table Access Latency Maximum Loading Using relationship outlined Table determine effect increased latency 860T system's aggregate serial bandwidth capability, Table (below) presents results variety latency values: Access Latency (cycles) Maximum Loading
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Table Examples Access Latency corresponding Maximum Loading With this information, consider original sequence accesses 860T's U-bus, evaluate access latency corresponding maximum loading system. have following sequence mastership: SDMA SDMA SDMA etc. Assuming either IDMA programmed with lower priority than SCCs, IDMA used this application, then following sequence illustrates latency CPM: etc. Adding cycles, based SDRAM timing 50MHz 860T: repeat Here, latency between successive accesses great cycles: 5+8+8+8. Using Table guide, designer should recognize that loading system must exceed 75%: 1(29-20) With only single 10BaseT channel SCC1 IDMA, loading well under limit just 23%: (10/22)*(25MHz/50MHz)=0.227. examine relationship between latency loading even further, will consider several system scenarios (assuming clocks latency) then determine impact added latency comparable 860T system.
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Example
860's loaded when handling HDLC channels MHz. (Based Table Appendix User's Manual: When latency increases clocks 860T system discussion above), loading must below 75%. Starting from this value, calculate that handle HDLC channels, rather than [(49*0.064)/2.1]*25/50=0.75.
Example
50MHz configured half-duplex 10BaseT channel Mbps fullduplex HDLC channel, system with under clocks latency CPM, then utilization only 35%: evaluating same serial configuration 860T, which experience greater latency will again cycles calculate that maximum supported loading 75%: 1(29-20) Therefore, with actual loading well under limit,
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50MHz 860T will experience latency problem while supporting load consisting Ethernet channel 2Mbps HDLC channel, addition Fast Ethernet channel. course, system must also have adequate bandwidth support aggregate data throughput.)
Example
Some designs might include external master, such bridge device, MPC8xx bus. Just like 860's internal masters, this device must arbitrate access system order access memory subsystem. From perspective CPM, external master adds latency therefore reduces system's maximum supported loading.
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When 860's Module Configuration Register (SIUMCR) programmed internal arbitration, external master's arbitration request priority anywhere from highest priority lowest priority. Assuming priority level used case Tundra's Q-Span bridge device), external master always higher priority than 860's internal masters (with exception refresh controller). Furthermore, once 860's internal arbiter grants requesting external master, external device maintain assertion (Bus Busy) signal keep control external indefinitely. Therefore, designer should incorporate external logic interface external master ensure that this device will yield before causing serial channel underruns overruns starving CPU. Once limitation placed number cycles during which external master continuously control bus, user calculate latency that will experience when external master active part system. following sequence external master mastership characterizes 860T system with bursting external master (denoted EXT) that permitted only burst transaction during each tenure. will notice that round-robin internal masters continues despite presence external master which alters external mastership sequence. repeat this scenario, experience latency great cycles from access next, during time when multiple masters including external master -have access requests: 5+8+8+8+8+8+8+8=61. Consulting Table determine that maximum loading this system 48%: 0.5(61-50) 48.5. provide example capacity under these loading conditions, following equation illustrates that 50MHz 860T support HDLC channels 768kbps each still less than loaded:
Conclusion
impact boundary conditions worst-case scenarios described this paper will reduced future 860T designs with help enhancements current 860T.
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First, microcode will revised permit only buffer descriptor access, rather than consecutive accesses, intervene between accesses Fast Ethernet data. Another planned enhancement addition user-programmability water-mark FIFO that determines when transmitter begin transmission frame. allow greater latency without FIFO underrun, user select 128, bytes data FIFO starting point frame transmission. These design changes will occur next revision 860T silicon (Rev. currently targeted 1Q99. Until these enhancements implemented, designer must careful attention factors affecting 860T performance their impact proposed system design.
Freescale Semiconductor, Inc.
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MPC860T enhanced version MPC860 with added 10/100 Ethernet capability.

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