256Kx8 Super Power Voltage Full CMOS Static CMOS SRAM Revisi

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256Kx8 Super Power Voltage Full CMOS Static CMOS SRAM Revisi

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K6F2008V2M, K6F2008S2M, K6F2008R2M Family
256Kx8 Super Power Voltage Full CMOS Static
CMOS SRAM
Revision History
Revision History
Initial draft Revise Remove sTSOP1 from product Rename high power product power. ISB1=10.0mA(Max) super power version with special handling ISB1=1.0mA(Max) Remove 70ns 85ns part KM68F2000 Family Finalize Revise Change datasheet format Remove reverse type package from product Remove reseved speed bin(100ns)
Draft Date
October 1996 December 1996
Remark
Advance Preliminary
April 1997 March 1998
Final Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
256Kx8 Super Power Voltage Full CMOS Static FEATURES
Process Technology: Full CMOS Organization: 256Kx8 Power Supply Voltage K6F2008V2M Family: 3.6V K6F2008S2M Family: 3.3V K6F2008R2M Family: 2.7V Data Retention Voltage: 1.5V(Min) Three state output Compatible Package Type: 32-TSOP1-0820F
CMOS SRAM
GENERAL DESCRIPTION
K6F2008V2M, K6F2008S2M K6F2008R2M families fabricated SAMSUNGs advanced Full CMOS process technology. families support various operating temperature ranges have various package types user flexibility system design. families also supports data retention voltage battery back-up operation with data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed(ns) Standby (ISB1, Max) Operating (ICC2, Max) 60mA 55mA 30mA 10µA2) 15mA 60mA 55mA 30mA 15mA 32-TSOP1-F Type
K6F2008V2M-C K6F2008S2M-C K6F2008R2M-C K6F2008V2M-I K6F2008S2M-I K6F2008R2M-I Industrial(-40~85°C) Commercial(0~70°C)
3.0~3.6V 2.3~3.3V 1.8~2.7V 3.0~3.6V 2.3~3.3V 1.8~2.7V
701)/85@VCC=3.3±0.3V 85@VCC=3.0±0.3V 1201)/150@VCC=2.5±0.2V 3001)@VCC=2.0±0.2V 701)/85@VCC=3.3±0.3V 85@VCC=3.0±0.3V /150@VCC=2.5±0.2V @VCC=2.0±0.2V
parameter measured with 30pF test load. super power version with special handling.
DESCRIPTION
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
32-TSOP Type Forward
select
Memory array 1024 rows columns
Name
Function
Name
Function
I/O1 I/O8
CS1,CS Chip Select Input Output Enable Write Enable Input
I/O1~I/O8 Data Inputs/Outputs N.C. Power Ground Connection
Data cont
Circuit Column select
A0~A17 Address Inputs
Data cont
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
PRODUCT LIST
Commercial Temperature Products(0~70°C) Part Name K6F2008V2M-TC70 K6F2008V2M-TC85 K6F2008S2M-TC12 K6F2008S2M-TC15 K6F2008R2M-TC30 Function 32-TSOP 70ns, 3.3V, 32-TSOP 85ns, 3.3V, 32-TSOP 120/85ns, 2.5/3.0V, 32-TSOP 150/85ns, 2.5/3.0V, 32-TSOP 300ns, 2.0/2.5V,
CMOS SRAM
Industrial Temperature Products(-40~85°C) Part Name K6F2008V2M-TI70 K6F2008V2M-TI85 K6F2008S2M-TI12 K6F2008S2M-TI15 K6F2008R2M-TI30 Function 32-TSOP 70ns, 3.3V, 32-TSOP 85ns, 3.3V, 32-TSOP 120/85ns, 2.5/3.0V, 32-TSOP 150/85ns, 2.5/3.0V, 32-TSOP 300ns, 2.0/2.5V,
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout
Mode Deselected Deselected Output Disable Read Write
Power Standby Standby Active Active Active
means dont care (Must high states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Soldering temperature time Symbol VIN,VOU TSTG TSOLDER 260°C, 5sec (Lead Only) Ratings -0.2 3.6V
Unit
Remark K6F2008V2M-C, K6F2008S2M-C, K6F2008R2M-C K6F2008V2M-I, K6F2008S2M-I, K6F2008R2M-I
-0.2 4.0V
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability. VIN/VOUT=-0.2 3.9V K6F2008V2M Family. Maximum VCC=-0.2 4.6V K6F2008V2M Family.
Revision March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
RECOMMENDED OPERATING CONDITIONS
Item Supply voltage Ground Symbol Product K6F2008V2M Family K6F2008S2M Family K6F2008R2M Family Family K6F2008V2M Family K6F2008S2M Family Vcc=3.3±0.3V Vcc=3.0±0.3V Vcc=2.5±0.2V K6F2008R2M Family Input voltage Family Vcc=2.5±0.2V Vcc=2.0±0.2V -0.23) Typ2) 2.5/3.0 2.0/2.5
CMOS SRAM
Unit
Input high voltage
Vcc+0.22)
Note Commercial Product TA=0 70°C, unless otherwise specified Industrial Product TA=-40 85°C, unless otherwise specified Overshoot 1.0V case pulse width20ns Undershoot -1.0V case pulse width20ns Overshoot undershoot sampled, 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ICC1 Average operating current ICC2
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL
Test Conditions VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL, VIO=Vss IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL VIH, Read
Cycle time=1µs, 100% duty, =0mA, 0.2V, VCC-0.2V, VIN0.2V INVCC-0.2V
Read Write
551)
Unit
Vcc=3.3V@70ns Vcc=2.7V@120ns Vcc=2.2V@300ns 2.1mA Vcc=3.0/3.3V
Output voltage
0.5mA Vcc=2.5V 0.33mA Vcc=2.0V -1.0mA Vcc=3.0/3.3V
Output high voltage
-0.5mA Vcc=2.5V -0.44mA Vcc=2.0V
Standby Current(TTL) Standby Current(CMOS)
ISB1
CS1=VIH CS2=VIL, Other inputs=VIL
Vcc-0.2V, CS2Vcc-0.2V 0.2V, Other inputs=0~Vcc
1.The value measured Vcc=3.0±0.3V ICC2=60mA with 70ns Vcc=3.3±0.3V, this value 100% tested obtained statistically. Super power product with special handling.
Revision March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
OPERATING CONDITIONS
TEST CONDITIONS (Test Load Test Input/Output Reference)
Input pulse level: 2.2V Vcc=3.3V, 3.0V, 2.5V 1.8V Vcc=2.0V Input rising falling time: Input output reference voltage: 1.5V Vcc=3.3V, 3.0V 1.1V Vcc=2.5V 0.9V Vcc=2.0V Output load (See right):CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R23)
Including scope capacitance 1=3070W, =3150W V=2.8V VCC=3.0/3.3V =2.3V VCC=2.5V =1.8V VCC=2.0V
CHARACTERISTICS(Commercial product:TA=0 70°C, Industrial product: TA=-40 85°C
K6F2008V2M Family: Vcc=3.0~3.6V, K6F2008S2M Family: Vcc=2.3~3.3V, K6F2008R2M Family: Vcc=1.8~2.7V) Speed Bins Parameter List Symbol 70ns Read cycle time Address access time Chip select output Output enable valid output Read Chip select low-Z output Output enable low-Z output Chip disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write Write pulse width Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tCO1, tCO2 tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tWHZ 85ns 120ns 150ns 300ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V1) Vcc=3.0V, CS1Vcc-0.2V
Unit
data retention waveform
CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) CS20.2V(CS2 controlled) Super power product with special handling.
Revision March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1)
Address Data Previous Data Valid
(Address Controlled, CS1=OE=VIL, WE=VIH)
CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than (Min.) both given device from device device interconnection.
Revision March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
TIMING WAVEFORM WRITE CYCLE(2) (CS1
Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
TIMING WAVEFORM WRITE CYCLE(3) (CS1 Controlled)
Address tAS(3) tWP(2) tWP(1) Data Data Valid tCW(2) tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap high write begins latest transition among goes low, going high going write earliest transition among going high, going going high, measured from begining write write. measured from going going high write. measured from address valid beginning write. measured from write address change. WR(1) applied case write ends going high tWR(2) applied case write ends going low.
DATA RETENTION WAVE FORM
controlled
3.0/2.7/2.3/1.8V tSDR Data Retention Mode tRDR
2.2V CSVCC 0.2V
controlled
3.0/2.7/2.3/1.8V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (0820F)
CMOS SRAM
Units: millimeters(inches)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.00±0.20 0.787±0.008 8.00 0.315 0.25 0.010
8.40 0.331
0.50 0.0197
1.00±0.10 0.039±0.004 1.20 0.047 0.05 0.002
0.25 0.010
18.40±0.10 0.724±0.004 0.15
+0.10 -0.05
0~8°
0.45 ~0.75 0.018 ~0.030
0.50 0.020
0.004 1.10
0.006+0.004 -0.002
Revision March 1998

256Kx8 Super Power Voltage Full CMOS Static CMOS SRAM Revisi

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