AN2060 MPC860SAR Microprocessor ACAM Interface Application V
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AN2060
MPC860SAR Microprocessor ACAM Interface Application
V1.0 Initial release
Freescale Semiconductor, Inc.
V1.1 August 1998 Fixed bugs found during Verilog verification: changed match port logic non-inverting, corrected error register programming `Insert Value', `Delete Value'. V1.2 1/02 Reformat.
OVERVIEW
MPC860SAR supports demultiplexing received Acell stream into memory buffers each receive connection. order this, MPC860SAR must resolve identification information Acell headers into internally-used connection number. Header information considered doing this include VPI, VCI, GFC, PTI. MPC860SAR designer selects exactly which bits consider setting header mask register. There three methods resolving cell header information into connection numbers, including simple internal lookup table, two-level external address compression tables, external contentaddressable memory (CAM). first method adequate virtual circuit connections (VPCs VCCs). latter methods support 65536 virtual circuit connections. these two, address compression method lower-cost, less flexible, because requires designer limit VPI/VCI supported order limit size tables, carries some performance penalty. address compression method acceptable designer control assignment VPI/VCI, accept slight performance limitations. However, support maximum number virtual circuit connections with 100% flexibility assignment VPI/VCI with performance penalty, required. This document demonstrates interface. selected this application Motorola's 4Kx64 MCM69C232, which support 4096 virtual circuit connections. more connections required, larger Motorola CAMs multiple CAMs used with similar interface. following topics covered: Physical interface, MPC860SAR register configuration, MCM69C232 register configuration, Transaction timing diagrams.
This document contains information product under development. Motorola reserves right change discontinue this product without notice.
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1998 Motorola, Inc. Rights Reserved. Preliminary Document.
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Freescale Semiconductor, Inc. PHYSICAL INTERFACE
interface consists ports, Control Port Match Port. behavior these ports very different, actual fact they independent. However, MPC860SAR will only access port time, only external interface. main components interface include: Reset clocking signals, Control port, mapped chip-select controlled General Purpose Chip Select Machine (GPCM), Match port, mapped either: chip-select controlled MPC860SAR's User Programmable Machines (UPMs), chip-select controlled GPCM (with extra glue logic). NOTE
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interface described assumes 50MHz MPC860SAR operating fullspeed mode. fundamentals interface remain same other speed MPC860SAR half-speed mode, memory access wait-states modified appropriately. following diagram shows recommended interface reset, clocking, Control Port between MPC860SAR MCM69C232 CAM.
MPC860SAR
(unused) CLKOUT RD/WR A(28:30) D(0:31) pullup resistor (3.3 rail
MCM69C232
DTACK RESET A(2:0) DQ(15:0) Control Port
Figure Reset, clocking, control port interface
Reset Clocking
reset input driven general-purpose output from MPC860SAR. This allows MPC860SAR reset software, initialization fault recovery. clock input driven MPC860SAR's CLKOUT output. time writing, maximum clock frequency MCM69C232 50MHz.
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Control Port
control port 16-bit read/write port. only control signals required asserted with negated indicates read; asserted with asserted indicates write. This memory controller signal behavior accomplished General Purpose Chip Select Machine (GPCM). chip-select signal (CSx) MPC860SAR functions SEL, RD/WR signal MPC860SAR functions MCM69C232 CAM. control port only accessible 16-bit accesses. Therefore, address lines A(2:0) A(28:30) lines MPC860SAR, MPC860SAR used. Also, since only 16-bit writes will performed, signals specific byte lanes required. [The signals MPC860SAR cannot used signal MCM69C232 CAM, because signal must valid before asserts.]
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16-bit memory, control port maps data lines D(0:15) MPC860SAR's data bus. control port will only accessed MPC860SAR during initialization when MPC860SAR adds removes connections from CAM. These tasks performed user's software, MPC860SAR's Amicrocode. MCM69C232 includes line which optionally used alert user certain conditions within CAM. This function available designer, absolutely necessary therefore demonstrated this design. pulled DTACK signal unused pulled control port actually asynchronous port which responds with DTACK when commands completed. However, since match port being used simultaneously with control port, behavior this interface actually very deterministic. Since speed this control interface important system, possible design this interface worst-case timing this asynchronous port, without monitoring DTACK. 200ns allowed elapse between control port accesses, then user assured that each individual command completed before issuing next command. 50MHz system, this would entail programming GPCM control port's chip-select waitstates. This holds true commands except INITIALIZE TABLE. user desires INITIALIZE TABLE command, then MCM69C232 configured Interrupt Register signal when this command complete. This signal could used signal interrupt MPC860SAR upon completion this command.
Match Port
following sections describe different options interface between MPC860SAR MCM69C232 CAM.
Option Match port interface using
following diagram shows interface between MPC860SAR match port MCM69C232 using chip-select controlled User Programmable Machines (UPMs) MPC860SAR. advantages this interface are: Uses less glue logic, Enables optimized timing interface using external acknowledge signal.
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MPC860SAR
MPHY# ->A(28:29)
D(12:27) D(1:11) D(28:31) Logic
MCM69C232
Match Port MQ(15:0) MQ(26:16) MQ(31:28) MQ(27) LH/SM
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D(0)
GPLy UPWAIT
Note: Additional glue logic MPHY# required only MPHY operation desired. pullup resistor (3.3 rail
Figure Match port interface using
match port 32-bit read/write port. Accesses match port MCM69C232 from MPC860SAR consist write cycle followed read cycle. write cycle drives match data CAM, which latches data when LH/SM signal asserts. read cycle reads return data from there successful match). Completion match attempt indicated signal; success match indicated signal. match successful, return data will driven MCM69C232 controlled output enable signal control port being accessed during match port access (which will happen with MPC860SAR), MCM69C232 will assert signal eight clocks. Thus, maximum number clocks required read cycle eight; however, possible that read cycle could even shorter, since other intervening activity between write read could provide required eight clocks latency. Because match port data path receive cell traffic, desirable optimize timing accesses, rather than cycle length meet worst-case timing this transaction done with control port). This behavior accomplishable User Programmable Machine (UPM) MPC860SAR's memory controller.
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UPM's GPLy signals used LH/SM signals, respectively. programmed assert during write cycles GPLy during read cycles. read cycles, signal used UPWAIT signal UPM. When signal asserts, UPWAIT signal will read negated read cycle will allowed terminate. match port only accessible 32-bit accesses. match data written will 32-bit operands; return data read will 32-bit operands. Thus, byte-select BS(0:3) signals used this interface. signal active-low indication successful match, driven concurrently with MPC860SAR expects active-low indication successful match However, MPC860SAR will drive match data DQ31 MCM69C232 during writes match port. Therefore, tri-state buffers shown necessary appropriate signal drive direction GPLy used gate these tri-state buffers. arrangement data lines shown required enable `AMODE' functionality MCM69C232 CAM. This some implications user's software, which explained discussion `SET AMODE' command. MCM69C232 CAM's signal only required match data written requires more than 32-bit write transaction (i.e. more than bits). MPC860SAR's Amicrocode only performs 32bit write, unused pulled signal only used signal match when MCM69C232 `AMODE'. However, this interface explicit indication necessary; return data alone sufficient. Therefore, signal also unused pulled Multi-PHY operation MPC860SAR desired, then address signals must also considered part match data. However, bits data already VPI, VCI, GFC, PTI, bits. Therefore, Multi-PHY operation used, during match data write cycle address will appear A(28:29) MPC860SAR. These address lines should driven data bits match port, This will require some gated tri-state buffers, similar interface implemented. Because this feature will required majority applications, these buffers explicitly shown, indicated optional `Logic' diagram.
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Option Match port interface using GPCM
following diagram shows interface between MPC860SAR match port MCM69C232 using chip-select controlled General Purpose Chip Selects Machine (GPCM) MPC860SAR. advantage this interface that does require UPM, neither
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UPMs MPC860SAR happen available. disadvantage this interface that requires additional tri-state buffers.
MPC860SAR
MPHY# ->A(28:29)
D(12:27) D(1:11) Logic
MCM69C232
Match Port MQ(15:0) MQ(26:16) MQ(31:28) MQ(27) LH/SM
Freescale Semiconductor, Inc.
D(28:31) D(0)
Note: Additional glue logic MPHY# required only MPHY operation desired. pullup resistor (3.3 rail
Figure Match port interface using GPCM match port 32-bit read/write port. Accesses match port MCM69C232 from MPC860SAR consist write cycle followed read cycle. write cycle drives match data CAM, which latches data when LH/SM signal asserts. read cycle reads return data from there successful match). Completion match attempt indicated signal; success match indicated signal. match successful, return data will driven MCM69C232 controlled output enable signal control port being accessed during match port access (which will happen with MPC860SAR), MCM69C232 will assert signal eight clocks. Thus, maximum number clocks required read cycle eight. Thus, possible program chipselect MPC860SAR accommodate this worst-case timing MCM69C232 done with control port). This behavior accomplishable General Purpose Chip Select Machine (GPCM) MPC860SAR's memory controller.
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GPCM's serves gaiting signal MPC860SAR's signals, which serve MCM69C232 CAM's LH/SM signals, respectively. selection gated LH/SM signal arbitrary; WE(0:3) signals could used. match port only accessible 32-bit accesses. match data written will 32-bit operands; return data read will 32-bit operands. signal active-low indication successful match, driven concurrently with MPC860SAR expects active-low indication successful match However, MPC860SAR will drive match data DQ31 MCM69C232 during writes match port. Therefore, tri-state buffers shown necessary appropriate signal drive direction gated signal used gate these tri-state buffers. arrangement data lines shown required enable `AMODE' functionality MCM69C232 CAM. This some implications user's software, which explained discussion `SET AMODE' command. signal only required dynamic handshaking this match port interface. However, this interface been programmed worst-case timing, instead using dynamic handshaking. Therefere, used pulled MCM69C232 CAM's signal only required match data written requires more than 32-bit write transaction (i.e. more than bits). MPC860SAR's Amicrocode only performs 32bit write, unused pulled signal only used signal match when MCM69C232 `AMODE'. However, this interface explicit indication necessary; return data alone sufficient. Therefore, signal also unused pulled Multi-PHY operation MPC860SAR desired, then address signals must also considered part match data. However, bits data already VPI, VCI, GFC, PTI, bits. Therefore, Multi-PHY operation used, during match data write cycle address will appear A(28:29) MPC860SAR. These address lines should driven data bits match port, This will require some gated tri-state buffers, similar interface implemented. Because this feature will required majority applications, these buffers explicitly shown, indicated optional `Logic' diagram.
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MPC860SAR REGISTER CONFIGURATION AParameters
following parameters must parameter each Achannel that will CAM: Receiver State (SRSTATE) Sets operating mode receiver. EXT=1 (extended channel mode), ACP=0 (CAM used channel lookup). Address (CAMADD) this parameter address match port MPC860SAR's memory map. CAMADD must divisible mapped memory controller 64KB region.
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Header Mask (HMASK) This mask determines which bits header (GFC, VPI, VCI, PTI, CLP) used channel number lookup CAM. user should these bits accordance with their desired application.
Memory-Mapping Control Port
control port mapped chip-select signal which controlled GPCM MPC860SAR's memory controller. smallest memory region mappable chip-select 64KB; this minimum memory size should selected chip-select. assertion chip-select signal been programmed delay clock cycles (via TRLX ACS(0:1) bits order assure that, during write cycles, data valid before (SEL) asserts MCM69C232 CAM. programming registers this chip-select should follows:
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Base Register (BRx)
BA(0:16) Sets base address CAM's control port. only address lines A(28:30) used CAM's control port, this will the16-byte register MCM69C232 throughout 64KB region. these bits point unused 64KB region memory map. 17:19 AT(0:2) optionally used limit access certain address types. This feature normally unused, these bits zero. 20:21 PS(0:1) control port 16-bit port. These bits must binary PARE Used enable parity generation/checking this chip-select. this zero. Used write-protect memory mapped this chip-select. this zero. 24:25 MS(0:1) Selects mechanism used controlling this chip-select. this case, will GPCM. these bits binary 26:30 Reserved Activates this chip-select. this one. 0:16
Option Register (ORx)
AM(0:16) Sets size memory selecting which bits will used addresscomparison. memory size chip-select 64KB minimum setting these bits ones. 17:19 ATM0:2) Mask used with AT(0:2) bits enable address-type protection this memory. This feature normally unused. these bits zero disable this feature. CSNT/SAM this case, this sets chip-select negate timing this chip-select. this zero. 21:22 ACS(0:1)/G5LA,G5LS this case, these bits chip-select assertion timing this chip-select. these bits binary Enables/disables bursting this chip-select. control port burstable, this one. 24:27 SCY(0:3) GPCM used this chip-select, these bits number wait-states this chip-select. wait-states should provide minimum 200ns cycle time when accessing control port. 50MHz bus, cycle length should clocks. Setting TRLX=1 0:16
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below causes wait-states programmed SCY[0:3] double. Therefore, ten-clock cycle, (SCY[0:3]x2)+2 equals ten. Therefore, these bits binary 0100. SETA Selects whether generated internally externally. Select internal setting this zero. TRLX Sets relaxed timing this chip-select. this EHTR Inserts null cycle memories with long disable times. this zero. Reserved
Memory-Mapping Match Port
match port mapped chip-select which controlled MPC860SAR's memory controller. memory controller control this chip-select with either GPCM, previously shown. Register programming both options presented here.
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Option Match port interface using
This option uses User Programmable Machines (UPM) MPC860SAR's memory controller control match port. This either UPMA UPMB; register descriptions below, used place-holder. smallest memory region mappable chip-select 64KB; this minimum memory size should selected chip-select. programming registers this chip-select should follows:
Base Register (BRy)
0:16 BA(0:16) Sets base address CAM's match port. address lines used CAM's match port, this will match port MCM69C232 throughout 64KB region. these bits point unused 64KB region memory map. This base address must match value CAMADD MPC860SAR's Aparameters. 17:19 AT(0:2) optionally used limit access certain address types. This feature normally unused, these bits zero. 20:21 PS(0:1) match port 32-bit port. These bits must binary PARE Used enable parity generation/checking this chip-select. this zero. Used write-protect memory mapped this chip-select. this zero. 24:25 MS(0:1) Selects mechanism used controlling this chip-select. this case, will UPMA UPMB. these bits binary binary 26:30 Reserved Activates this chip-select. this one.
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Option Register (ORy)
0:16 AM(0:16) Sets size memory selecting which bits will used addresscomparison. memory size chip-select 64KB minimum setting these bits ones. 17:19 ATM0:2) Mask used with AT(0:2) bits enable address-type protection this memory. This feature normally unused. these bits zero disable this feature. CSNT/SAM this case, this sets initial state address-multiplexing this chipselect. this zero. 21:22 ACS(0:1)/G5LA,G5LS this case, these bits behavior GPL5 line this UPM. GPL5 used this interface. these bits binary Enables/disables bursting this chip-select. match port burstable, this one. 24:27 SCY(0:3) GPCM used this chip-select, these bits number wait-states this chip-select. GPCM used this chip-select, these bits zero. SETA Selects whether generated internally externally. Select internal setting this zero. TRLX Sets relaxed timing this chip-select. This don't-care UPM. this zero. EHTR Inserts null cycle memories with long disable times. This don't-care UPM. this zero. Reserved
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Machine Mode Register (MyMR)
PTA(0:7) Sets period refresh timer this UPM. doesn't need refresh, this don't-care. these bits zero. PTAE Enables/disables refresh timer this UPM. this zero. 9:11 AMy(0:2) -Sets address multiplexing size this UPM. Address muliplexing used CAM. these bits binary 000. Reserved 13:14 DSA(0:1) Sets period disable timer between accesses this UPM. delay needed, these bits binary Reserved 16:18 G0CLA Determines which address line GPL0, this feature used. This features used, these bits binary 000. GPL_y4DIS Enables/disables GPL_y4, allowing this signal used UPWAIT. UPWAIT required this interface. this one. 20:23 RLFy(0:3) -Sets number iterationsof loops UPM's read patterns. Loops used patterns, these bits binary 0000. 24:27 WLFy(0:3) -Sets number iterationsof loops UPM's write patterns. Loops used patterns, these bits binary 0000. 28:31 TLFy(0:3) -Sets number iterationsof loops UPM's refresh patterns. Refresh performed this UPM, these bits binary 0000.
words
following patterns should programmed words appropriate Only single-beat read single-beat write patterns used. burst patterns, refresh pattern, exception patterns need initialized. 50MHz bus, words words should programmed
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Single-beat read: 0xFFFFCC04 0xFFF3DC04 0XFFF3CC00 0XFFF7CC05 Single-beat write: 0xFFFFCC04 0x0FFFCC04 0X3FFFCC00 0xFFFFCC05
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Option Match port interface using GPCM
This option uses General Purpose Chip Select Machine (GPCM) MPC860SAR's memory controller control match port. smallest memory region mappable chip-select 64KB; this minimum memory size should selected chip-select. programming registers this chip-select should follows:
Base Register (BRy)
BA(0:16) Sets base address CAM's match port. address lines used CAM's match port, this will match port MCM69C232 throughout 64KB region. these bits point unused 64KB region memory map. This base address must match value CAMADD MPC860SAR's Aparameters. 17:19 AT(0:2) optionally used limit access certain address types. This feature normally unused, these bits zero. 20:21 PS(0:1) match port 32-bit port. These bits must binary PARE Used enable parity generation/checking this chip-select. this zero. Used write-protect memory mapped this chip-select. this zero. 24:25 MS(0:1) Selects mechanism used controlling this chip-select. this case, will GPCM. these bits binary 26:30 Reserved Activates this chip-select. this one. 0:16
Option Register (ORy)
0:16 AM(0:16) Sets size memory selecting which bits will used addresscomparison. memory size chip-select 64KB minimum setting these bits ones. 17:19 ATM0:2) Mask used with AT(0:2) bits enable address-type protection this memory. This feature normally unused. these bits zero disable this feature. CSNT/SAM this case, this sets timing chip-select negation. this (thus programming chip-select negate clock early). 21:22 ACS(0:1)/G5LA,G5LS this case, these bits timing chip-select assertion. these bits binary (thus programming chip-select assert clock late). Enables/disables bursting this chip-select. match port burstable, this one. 24:27 SCY(0:3) Since GPCM used this chip-select, these bits number waitstates this chip-select. Cycle length should eight clocks. Setting TRLX=1 below causes
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wait-states programmed SCY[0:3] double. Therefore, eight-clock cycle, (SCY[0:3]x2)+2 equals eight. Therefore, these bits binary 0011. SETA Selects whether generated internally externally. Select internal setting this zero. TRLX Sets relaxed timing this chip-select. this (thus providing extra clock before chip-select assertion). EHTR Inserts null cycle memories with long disable times. This isnot necessary MCM69C232 CAM. this zero. Reserved
MCM69C232 REGISTER CONFIGURATION
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Operation Register
Refer MCM69C232 documentation complete command set. `SET GLOBAL MASK REGISTER' COMMAND [WARNING: sense this mask register opposite normal mask registers;1 indicates ignore this bit, indicates this bit]. lower bits these lower bits will contain channel number, will returned upon successful match. upper bits $00000000 (i.e. mask match data presented CAM). Masking unwanted bits will done MPC860SAR's microcode MPC860SAR's HMASK register, necessary with Global Mask Register. `SET AMODE' COMMAND match port interface been designed enable `AMODE' MCM69C232. `AMODE', MCM69C232 perform matching either basis. order enable matching `AMODE', order data bits MPC860SAR MCM69C232 arranged particular fashion. This because MCM69C232 expects data lines MQ(15:0). MPC860SAR's match data places data bits 12-27, which would correspond data lines MQ(19:4) data connected normally. data lines effectively shifted MPC860SAR MCM69C232 match port interface, such that: D(12:27) connect MQ(15:0) D(1:11) connect MQ(26:16) connects MQ27 (and shown diagram) D(28:31) connect MQ(31:28) There software implications this data-bit arrangement which pertain `INSERT VALUE', `DELETE VALUE', related commands. `INSERT VALUE', `DELETE VALUE', RELATED COMMANDS arrangement data bits this interface requires user registers following manner when issuing `INSERT VALUE', `DELETE VALUE', related commands: Register Bits15-13=PTI, 12=CLP, Bits 11-0=GFC/VPI Register Bits 15-0=VCI
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Register Upper order bits channel number (match return data), shifted right Register Lower order bits channel number (match return data), shifted left example, order route cells with GFC/VPI 5F2, 9A26, binary 010, channel number 3752, write 45F2, 9A26, 2000, 0375. Because arrangement data lines, match data (i.e. 3752) will returned MPC860SAR match port data lines D(16:31). `SET FAST ENTRY MODE' COMMAND VERSUS `SET BUFFERED ENTRY MODE' COMMAND Buffered Entry mode recommended normal operation. Fast Entry mode could used initialization, using Fast Entry mode requires INITIALIZE TABLE command, issues with which described below.
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`INITIALIZE TABLE' COMMAND physical interface control port MCM69C232 uses normal worst-case timing 200ns command transaction order avoid monitoring DTACK signal. However, 200ns worst-case timing does apply INITIALIZE TABLE command; could longer. user desires INITIALIZE TABLE command, then MCM69C232 configured Interrupt Register signal when this command complete. This signal could used signal interrupt MPC860SAR upon completion this command.
Error Code Register
Check error conditions Error Code Register after control operations.
Interrupt Register
Though shown interface, interrupts (signalled IRQ) used signal MPC860SAR certain conditions. This configured Interrupt Register.
TRANSACTION TIMING DIAGRAMS Control Port Timing
access control port performed user software, initialization adding deleting entries CAM.
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50MHz bus, timing read write accesses shown below:
100ns (CLKOUT) A2:0 (A28:30) B22b SEL* (CSx*) (RD/WR*) tSHQZ DATA DTACK* B12a B11a 200ns
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Figure MCM69C232 Control Port Read Access
(CLKOUT) A2:0 (A28:30) B22b SEL* (CSx*) (RD/WR*) DATA DTACK* B12a B11a tSHQZ 100ns 200ns
Figure MCM69C232 Control Port Write Access APPLICATION NOTE More Information This Product, www.freescale.com MOTOROLA
Freescale Semiconductor, Inc. Match Port Timing
access match port performed MPC860SAR's Amicrocode. microcode performs write match data) followed read return data from CAM). These accesses necessarily back-to-back; other higher-priority masters take between these accesses.
Option Match port interface using
50MHz bus, timing write read accesses shown below: (CLKOUT) 50ns
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B31b B11a
LH*/SM* (CSy*) DATA
Figure MCM69C232 Match Port Write Access using (writing match data
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100ns
(CLKOUT) tKHMC (UPWAIT) tKHMS tGLMQX DATA (GPLy*) B12a B11a Figure MCM69C232 Match Port Read Access using (reading return data from CAM) B33a tKHMQV
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Option Match port interface using GPCM
50MHz bus, timing write read accesses shown below. timing diagrams include propagation delay through external logic, shown tPD. (CLKOUT) DATA B12a B11a B22a GATEWE* (CSy*) LH*/SM* Figure MCM69C232 Match Port Write Access using GPCM (writing match data CAM) B28a B28b 100ns
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100ns
(CLKOUT)
tKHMS tKHMQV tGLMQX B12a B11a
DATA
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GATEOE* (CSy*)
B22a
Figure MCM69C232 Match Port Read Access using GPCM (reading return data from CAM)
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