Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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K6F1016V3M, K6F1016S3M, K6F1016R3M Family
Super Power Voltage Full CMOS Static
CMOS SRAM
Revision History
Revision History
Initial draft Revise Erase 100ns part from KM616FS1000 Family 150ns part KM616FS1000 Family 32-sTSOP1 package high power version ISB1=5.0µA(Max) Change VDR(Min) 1.5V Finalize Concept change high power version power version ISB1=5.0µA(Max) Change super power version with special handling ISB1=1.0µA(Max) Reduce Icc1 Read 15mA 10mA Write 25mA 20mA Revise Change datasheet format Erase reverse type package Revise 48-µBGA type package
Draft Date
March 1996 June 1996
Remark
Advance Preliminary
December 1996
Final
February 1998
Final
1999
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision 1999
K6F1016V3M, K6F1016S3M, K6F1016R3M Family
FEATURES
Process Technology: Full CMOS Organization: 64Kx16 Power Supply Voltage K6F1016V3M Family: 3.0V~3.6V K6F1016S3M Family: 2.3V~3.3V K6F1016R3M Family: 1.8V~2.7V Data Retention Voltage: 1.5V(Min) Three state output status Compatible Package Type: 44-TSOP2-400F, 48-µBGA-6.00x8.00
CMOS SRAM
64Kx16 Super Power Voltage Full CMOS Static
GENERAL DESCRIPTION
K6F1016V3M, K6F1016S3M K6F1016R3M families fabricated SAMSUNGs advanced Full CMOS process technology. families support various operating temperature ranges user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6F1016V3M-C K6F1016S3M-C K6F1016R3M-C K6F1016V3M-I K6F1016S3M-I K6F1016R3M-I Industrial(-40~85°C) Commercial(0~70°C) Operating Temperature Range 3.0~3.6V 2.3~3.3V 1.8~2.7V 3.0~3.6V 2.3~3.3V 1.8~2.7V Speed(ns) 701)/85@VCC=3.3±0.3V /85@VCC=3.0±0.3V /150@VCC=2.5±0.2V 3001)@VCC=2.0±0.2V /85@VCC=3.3±0.3V 701)/85@VCC=3.0±0.3V 1201)/150@VCC=2.5±0.2V 3001)@VCC=2.0±0.2V
Standby (ISB1, Max)
Operating (ICC2, Max) 80mA 80mA 50mA
Type
44-TSOP2 Forward
5µA2)
20mA 80mA 80mA 50mA 20mA 44-TSOP2 Forward 48-µBGA
parameter measured with 30pF test load. Super power product=1µA with special handling. Availiable parts 100ns@VCC=3.0±0.3V, 150ns@V CC=2.5±0.2V 300ns@VCC=2.0±0.2V with 30pF test load.
DESCRIPTION
I/OI I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9
48-µBGA View
I/O9 I/O10 I/O11 I/O12 I/O2 I/O4 I/O1 I/O3
FUNCTIONAL BLOCK DIAGRAM
gen.
Precharge circuit.
Memory array 1024 rows columns
44-TSOP2 Forward
select
I/O15 I/O16
I/O13 I/O14
I/O5 I/O6
I/O7
I/O1~I/O8
I/O8
9~I/O16
Data cont Data cont Data cont
Circuit Column select
Name A0~A15
Function Chip Select Input Output Enable Input Write Enable Input Address Inputs
Name
Function Lower Byte(I/O1~8) Upper Byte(I/O9~16) Power Ground
Control logic
I/O1~I/O16 Data Inputs/Outputs
N.C. Connection
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision 1999
K6F1016V3M, K6F1016S3M, K6F1016R3M Family
PRODUCT LIST
Commercial Temperature Products(0~70°C) Part Name K6F1016V3M-TB70 K6F1016V3M-TB85 K6F1016S3M-TB12 K6F1016S3M-TB15 K6F1016R3M-TB30 Function 44-TSOP2 70ns, 3.3V, 44-TSOP2 85ns, 3.3V, 44-TSOP2 120/70ns, 2.5/3.0V, 44-TSOP2 150/85ns, 2.5/3.0V, 44-TSOP2 300ns, 2.0/2.5V, K6F1016R3M-TF30 K6F1016R3M-ZF30
CMOS SRAM
Industrial Temperature Products(-40~85°C) Part Name K6F1016V3M-TF70 K6F1016V3M-TF85 K6F1016S3M-TF12 K6F1016S3M-TF15 K6F1016S3M-ZF15 Function 44-TSOP2 70ns, 3.3V, 44-TSOP2 85ns, 3.3V, 44-TSOP2 120/70ns, 2.5/3.0V, 44-TSOP2 150/85ns, 2.5/3.0V, 48-µBGA, 2.5V/3.0V, 150/100ns 44-TSOP2 300ns, 2.0/2.5V, 48-µBGA, 1.8V/2.5V, 300ns
FUNCTIONAL DESCRIPTION
I/O1~8 High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Active Active Active Active Active Active Active Active
means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Soldering temperature time Symbol VIN,VOUT TSTG Ratings -0.2 3.6V
Unit
Remark K6F1016V3M-C, K6F1016S3M-C K6F1016R3M-C K6F1016V3M-I, K6F1016S3M-I, K6F1016R3M-I
-0.2 4.0V3)
TSOLDER 260°C, 5sec(Lead Only)
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability. VIN/VOUT=-0.2 3.9V K6F1016V3M Family. VCC=-0.2 4.6V K6F1016V3M Family.
Revision 1999
K6F1016V3M, K6F1016S3M, K6F1016R3M Family
RECOMMENDED OPERATING CONDITIONS
Item Symbol Product K6F1016V3M Family Supply voltage K6F1016S3M Family K6F1016R3M Family Ground Family K6F1016V3M Family K6F1016S3M Family Vcc=3.3±0.3V Vcc=3.0±0.3V Vcc=2.5±0.2V K6F1016R3M Family Input voltage Family Vcc=2.5±0.2V Vcc=2.0±0.2V -0.23) 2.5/3.0 2.0/2.5
CMOS SRAM
Unit
Input high voltage
Vcc+0.22)
Note Commercial Product TA=0 70°C, unless otherwise specified Industrial Product TA=-40 85°C, unless otherwise specified Overshoot 1.0V case pulse width 20ns Undershoot -1.0V case pulse width 20ns Overshoot undershoot sampled, 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ICC1 Average operating current ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIL 2.1mA Vcc=3.0/3.3V Output voltage 0.5mA Vcc=2.5V 0.33mA Vcc=2.0V -1.0mA Vcc=3.0/3.3V Output high voltage -0.5mA Vcc=2.5V -0.44mA Vcc=2.0V Standby Current(TTL) Standby Current(CMOS) ISB1 CS=VIH, Other inputs=V CSVcc-0.2V, Other inputs=0~Vcc VIN=Vss CS=VIH OE=VIH WE=VIL, VIO=Vss IIO=0mA, CS=VIL, VIN=VIL VIH, Read Cycle time=1µs, 100% duty, IIO=0mA, CS0.2V, VIN0.2V VINVCC-0.2V Read Write Test Conditions Unit
Vcc=3.3V@70ns Vcc=2.7V@120ns Vcc=2.2V@300ns
Super power product=1µA with special handling.
Revision 1999
K6F1016V3M, K6F1016S3M, K6F1016R3M Family
OPERATING CONDITIONS
TEST CONDITIONS (Test Load Test Input/Output Reference)
Input pulse level: 2.2V Vcc=3.3V, 3.0V, 2.5V 1.8V Vcc=2.0V Input rising falling time: Input output reference voltage: 1.5V Vcc=3.3V, 3.0V 1.1V Vcc=2.5V 0.9V Vcc=2.0V Output load (See right):CL=100pF+1TTL CL=30pF+1TTL VTM3) R12)
CMOS SRAM
CL1)
R22)
Including scope capacitance =3070, 2=3150 V=2.8V CC=3.0/3.3V =2.3V CC=2.5V =1.8V CC=2.0V
CHARACTERISTICS (Commercial product:TA=0 70°C, Industrial product: TA=-40 85°C
K6F1016V3M Family: Vcc=3.0~3.6V, K6F1016S3M Family: Vcc=2.3~3.3V, K6F1016R3M Family: Vcc=1.8~2.7V)
Speed Bins Parameter List Symbol 70ns 85ns 100ns 120ns 150ns 300ns Units
Read cycle time Address access time Chip select output Output enable valid output Read Access Time Chip select low-Z output Output enable low-Z output Chip disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write pulse width Write Valid Write Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tOLZ, tBLZ tOHZ, tBHZ tWHZ
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CSVcc-0.2V Vcc=3.0V data retention waveform
Unit
Super power product=1µA with special handling.
Revision 1999
K6F1016V3M, K6F1016S3M, K6F1016R3M Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1)
Address Data Previous Data Valid
CMOS SRAM
(Address Controlled, CS=OE=VIL, WE=VIH, or/and LB=VIL)
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address
tBHZ tOLZ tBLZ Data Valid tOHZ
Data
High-Z
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision 1999
K6F1016V3M, K6F1016S3M, K6F1016R3M Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
High-Z
TIMING WAVEFORM WRITE CYCLE(2) Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision 1999
K6F1016V3M, K6F1016S3M, K6F1016R3M Family
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends going high.
DATA RETENTION WAVE FORM
controlled
3.0/2.7/2.3/1.8V tSDR Data Retention Mode tRDR
2.2V CSVCC 0.2V
Revision 1999
K6F1016V3M, K6F1016S3M, K6F1016R3M Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (400F)
CMOS SRAM
Units: millimeters(inches)
0~8° 0.25 0.010 0.45 ~0.75 0.018 0.030
11.76 ±0.20 0.463 ±0.008
10.16 0.400
18.81 MAX. 0.741 18.41 ±0.10 0.725 ±0.004
0.05 0.15 0.002
0.50 0.020
1.00 ±0.10 0.039 ±0.004 0.805 0.032 0.35 ±0.10 0.014 ±0.004 0.80 0.0315 0.05 MIN. 0.002
1.20 MAX. 0.047
0.10 0.004
Revision 1999
K6F1016V3M, K6F1016S3M, K6F1016R3M Family
PACKAGE DIMENSIONS
BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch
View Ball Bottom View
CMOS SRAM
Units: millimeters
Ball
SRAM
Elastomer Side View Detail 0.25/Typ. Detail
0.55/Typ.
0.32/Typ.
Elastomer 0.42/Typ. Notes. Bump counts: 48(8row 6column) Bump pitch: (x,y)=(0.75 0.75)(typ.) tolerence +/-0.050 unless otherwise specified. Typ: Typical coplanarity: 0.08(Max) Revision 1999
5.90 7.90 0.30
0.75 6.00 3.75 8.00 5.25 0.35 0.80 0.55 0.25
6.10 8010 0.40 0.81 0.08

Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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