Application Note MPC8260 SDRAM Timing Diagram Motorola NetCo
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Order Number: MPC8260 1.0, 8/2000
Application Note
MPC8260 SDRAM Timing Diagram
Motorola NetComm, Austin
Introduction
timing diagrams generated based simulations. MPC8260 provides SDRAM interface local bus. machines provide necessary control function signals JEDEC-compliant SDRAM devices. timing diagrams organized access Local access Read-Modify-Write Cycle SDRAM ARTRY cycle
Access
access partitioned sub-groups: single MPC8260 mode external mode (60x compatible).
This document contains information product under development Motorola. Motorola reserves right change discontinue this product without notice. Motorola, Inc., 2000. rights reserved.
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SDRAM Timing Diagram
1.1.1 Single MPC8260 Mode single MPC8260 mode entered clearing HardResetConfiguration[EBM] during configuration. Under this mode, MPC8260 only master device system. internal memory controller controls devices external bus. signals used slave device because addresses have memory timing, address/data tenure timing. Assemble Language Example: Single Beat Read/Write
Setup addis r2,r0,0xfff0 r2,r2,0x0c40 addis r1,r0,0x0f01 r1,r1,0x010c 0x0000(r1) Setup addis r2,r0,0x0100 r2,r2,0x1841 addis r1,r0,0x0f01 r1,r1,0x0108 0x0000(r1) PSDMR Mode Register Write addis r2,r0,0x9800 r2,r2,0x9602 addis r1,r0,0x0f01 r1,r1,0x0100 0x0090(r1) first write SDRAM mode addis r2,r0,0x0100 r2,r2,0x0000 0x0008(r2) PSDMR normal addis r2,r0,0x8000 r2,r2,0x9602 0x0090(r1) single write 0x0100_0008 addis r2,r0,0x0100 r2,r2,0x0000
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SDRAM Timing Diagram
0x0008(r2) single read from 0x0100_0018 0x0018(r2) Burst Read/Write IDMA Setup addis r2,r0,0xffff r2,r2,0x2cc0 addis r1,r0,0x0f01 r1,r1,0x010c 0x0000(r1)
#Setup addis r2,r0,0x0100 r2,r2,0x1841 addis r1,r0,0x0f01 r1,r1,0x0108 0x0000(r1) PSDMR Mode Register Write addis r2,r0,0x9b4c r2,r2,0x9512 addis r1,r0,0x0f01 r1,r1,0x0100 0x0090(r1) First write SDRAM mode addis r2,r0,0x0100 r2,r2,0x0000 0x0008(r2) PSDMR normal addis r2,r0,0x834c r2,r2,0x9512 0x0090(r1) PDIRC addis r2,r0,0x0000 r2,r2,0x0100 addis r1,r0,0x0f01 r1,r1,0x0d40 0x0000(r1) PPARC
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SDRAM Timing Diagram
addis r2,r0,0x8000 r2,r2,0x0300 addis r1,r0,0x0f01 r1,r1,0x0d44 0x0000(r1) PSORC addis r2,r0,0x0000 r2,r2,0x0300 addis r1,r0,0x0f01 r1,r1,0x0d48 0x0000(r1)
PODRC addis r2,r0,0x0000 r2,r2,0x0200 addis r1,r0,0x0f01 r1,r1,0x0d4c 0x0000(r1) RCCR 0000 0000 addis r2,r0,0x0000 r2,r2,0x0000 addis r1,r0,0x0f01 r1,r1,0x19c4 0x0000(r1) IDMA1_BASE 1000h addis r2,r0,0x0000 r2,r2,0x1000 addis r1,r0,0x0f01 r1,r1,0x87fe 0x0000(r1) base address memory access addis r1,r0,0x0f01 r1,r1,0x1000 start 2000h addis r2,r0,0x0000 r2,r2,0x2000 0x0000(r1) addis r2,r0,0x0000 r2,r2,0x0070
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SDRAM Timing Diagram
0x0002(r1) IBDPTR addis r2,r0,0x0000 r2,r2,0x2000 0x0004(r1) DPR_BUF addis r2,r0,0x0000 r2,r2,0x4000 0x0006(r1)
#SS_MAX 0x0a addis r2,r0,0x0000 r2,r2,0x0060 0x000a(r1) 0x0e addis r2,r0,0x0000 r2,r2,0x0060 0x000e(r1) 0x16 addis r2,r0,0x0000 r2,r2,0x0060 0x0016(r1) ISTATE 0x28 addis r2,r0,0x0000 r2,r2,0x0000 0x0028(r1) base address memory access addis r1,r0,0x0f00 r1,r1,0x2000 addis r2,r0,0x8868 r2,r2,0x1000 0x0000(r1) Data length addis r2,r0,0x0000 r2,r2,0x022a 0x0004(r1)
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SDRAM Timing Diagram
source buffer pointer addis r2,r0,0x0100 r2,r2,0x0000 0x0008(r1) destination buffer pointer addis r2,r0,0x0100 r2,r2,0x0100 0x000c(r1) base address memory access addis r1,r0,0x0f00 r1,r1,0x4000
START IDMA1 addis r2,r0,0x1e81 r2,r2,0x0009 addis r1,r0,0x0f01 r1,r1,0x19c0 0x0000(r1)
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SDRAM Timing Diagram
1.1.1.1 access single MPC8260 mode, single beat read.
CLKIN ADDR
column0
column1
DATA
SDRAS
SDCAS
PSDVAL
Page Miss
Page
PSDMR[ACTTORW] 011, PSDMR[CL]=2
Figure
access single MPC8260 mode, single beat read
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SDRAM Timing Diagram
1.1.1.2 access single MPC8260 mode, single beat write.
CLKIN ADDR
column0
column1
DATA
SDRAS
SDCAS
PSDVAL Page Miss Page
PSDMR[ACTTORW] 011, PSDMR[CL]=2
Figure access single MPC8260 mode, single beat write
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SDRAM Timing Diagram
1.1.1.3 access single MPC8260 mode, burst read (burst length=8).
CLKIN ADDR
column0
column1
DATA
SDRAS
SDCAS
PSDVAL
Page Miss
Page
PSDMR[ACTTORW] 010, PSDMR[CL]=2, PSDMR[BL]=1(Busrt Length=8)
Figure
access single MPC8260 mode, burst read
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SDRAM Timing Diagram
1.1.1.4 access single MPC8260 mode, burst write (burst length=8).
CLKIN ADDR
column0
column1
DATA
SDRAS
SDCAS
PSDVAL
Page Miss
Page
PSDMR[ACTTORW] 010, PSDMR[CL]=2, PSDMR[BL]=1(Busrt Length=8)
Figure
access single MPC8260 mode, burst write
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SDRAM Timing Diagram
1.1.2 External Mode (60x compatible) 60x-compatible mode entered setting HardResetConfiguration[EBM] during configuration. Under this mode, lower bits address memory controlled baddr[27:31]. Note that baddr[29:31] muxed with other signals. muxing controlled SIUMCR[L2CPC]. baddr[29:31] function chosen when L2CPC bits configuration word during power programming directly SIUMCR after configuration. Additional controls available 60x-compatible mode: External address latch enable PSDAMUX External address multiplexing control (asserted=row, negated=column) BNKSEL[0-2]- Bank select address allow internal bank interleaving. Note: external mode, signals added better illustrate nature access.
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SDRAM Timing Diagram
1.1.2.1 access 60x-compatible mode, single beat read.
CLKIN ADDR
addr1
addr2
DATA
PSDAMUX AACK
PSDVAL
SDRAS
SDCAS
Page Miss PSDMR[ACTTORW] 011, PSDMR[CL]=2 Page
Figure 60x-compatible mode, single read
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SDRAM Timing Diagram
1.1.2.2 access 60x-compatible mode, single beat write.
CLKIN ADDR
addr1
addr2
DATA
PSDAMUX AACK
PSDVAL
SDRAS
SDCAS
Page Miss Page PSDMR[ACTTORW] 011, PSDMR[CL]=2
Figure 60x-compatible mode, single write
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SDRAM Timing Diagram
1.1.2.3 access 60x-compatible mode, burst read (burst length=4).
CLKIN ADDR addr2
addr1
DATA
PSDAMUX AACK
PSDVAL
SDRAS
SDCAS
Page Miss Page PSDMR[ACTTORW] 011, PSDMR[CL]=2
Figure 60x-compatible mode, burst read
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SDRAM Timing Diagram
1.1.2.4 access 60x-compatible mode, burst write (burst length=4).
CLKIN ADDR addr2
addr1
DATA
PSDAMUX AACK
PSDVAL
SDRAS
SDCAS
Page Miss PSDMR[ACTTORW] 011, PSDMR[CL]=2 Page
Figure 60x-compatible mode, burst write
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SDRAM Timing Diagram
Local Access
Local access functions same both Single MPC8260 mode 60x-compatible mode. Local signals: Local Address Local Data LSDRAS LSDCAS LDQM
Local address pins muxed with signals. Local function those pins chosen setting HardResetConfiguration[L2CPC] during configuration programming them after configuration.
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SDRAM Timing Diagram
1.2.1 local access, single beat read.
CLKIN L_ADDR
column0
column1
LCL_D
LSDRAS
LSDCAS
LDQM Page Miss Page
LSDMR[ACTTORW] 011, LSDMR[CL]=2
Figure
Local bus, single read
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SDRAM Timing Diagram
1.2.2 local access, single beat write.
CLKIN L_ADDR
column0
column1
LCL_D
LSDRAS
LSDCAS
LDQM Page Miss Page
LSDMR[ACTTORW] 011, LSDMR[CL]=2
Figure Local bus, single write
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SDRAM Timing Diagram
1.2.3 local access, burst read (burst length=8).
CLKIN L_ADDR
column0
column1
LCL_D
LSDRAS
LSDCAS
LDQM Page Miss Page
LSDMR[ACTTORW] 010, LSDMR[CL]=2, LSDMR[BL]=1(Busrt Length=8)
Figure
Local bus, burst read
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SDRAM Timing Diagram
1.2.4 local access, burst write (burst length=8).
CLKIN L_ADDR
column0
column1
LCL_D
LSDRAS
LSDCAS
LDQM Page Miss Page
LSDMR[ACTTORW] 010, LSDMR[CL]=2, LSDMR[BL]=1(Busrt Length=8)
Figure
Local bus, burst write
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SDRAM Timing Diagram
Read-Modify-Write Cycle
SDRAM programmed read-modify-write parity checking correction checking, every write access memory that less than port size will cause read-modify-write cycle automatically.
Note:
Figure Figure cycle caused 32-bit write 64-bit port. Figure: cycle caused 16-bit write 32-bit port.
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SDRAM Timing Diagram
1.3.1 access single MPC8260 mode, Read-Modify-Write Cycle
CLKIN ADDR
column
DATA
SDRAS
SDCAS
PSDVAL Read Write
PSDMR[ACTTORW] 011, PSDMR[CL]=2
Figure
single MPC8260 mode, Read-Modify-Write cycle
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SDRAM Timing Diagram
1.3.2 access 60x-compatible mode, Read-Modify-Write Cycle.
CLKIN ADDR
addr1
DATA
PSDAMUX AACK
PSDVAL
SDRAS
SDCAS
Read Write PSDMR[ACTTORW] 011, PSDMR[CL]=2
Figure
60x-compatible mode, Read-Modify-Write cycle
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SDRAM Timing Diagram
1.3.3 Local access, Read-Modify-Write Cycle
CLKIN L_ADDR LCL_D
column
LSDRAS
LSDCAS
LDQM Read Write
LSDMR[ACTTORW] 011, LSDMR[CL]=2
Figure
local bus, Read-Modify-Write cycle
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SDRAM Timing Diagram
ARTRY cycle
60x-compatible mode, address transfer terminated with requirement retry ARTRY asserted during address tenure through cycle following AACK. assertion causes entire transaction (address data tenure) rerun.
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SDRAM Timing Diagram
1.4.1 access 60x-compatible mode, ARTRY cycle
CLKIN ADDR
addr
addr
DATA
Data
Data
PSDAMUX AACK ARTRY
PSDVAL
SDRAS
SDCAS
Figure 60x-compatible mode, ARTRY cycle
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MPC8260
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