Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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K6F1016S4M, K6F1016R4M Family
Super Power Voltage Full CMOS Static
CMOS SRAM
Revision History
Revision History
Initial draft controls standby mode Finalize Remove KM616FU1010 Family Remove TSOP2 reverse type KM616FU1010 Family
Draft Date
July 1996
Remark
Preliminary
March 1998
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision February 1998
K6F1016S4M, K6F1016R4M Family
FEATURES
Process Technology: Full CMOS Organization: x16bit Power Supply Voltage KM616FS1010 Family: 2.3V~3.3V KM616FR1010 Family: 1.8V~2.7V Data Retention Voltage: 1.5V(Min) Three state output status Compatible Package Type: 44-TSOP2-400F
CMOS SRAM
GENERAL DESCRIPTION
K6F1016S4M K6F1016R4M families fabricated SAMSUNGs advanced Full CMOS process technology. families support various operating temperature ranges have various package types user flexibility system design. families also support data retention voltage battery backup operation with data retention current.
64Kx16 Super Power Voltage Full CMOS Static
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed(ns) 701)/85@VCC=3.0±0.3V 1201)/150@VCC=2.5±0.2V 1.8~2.7V 2.3~3.3V 1.8~2.7V @VCC=2.0±0.2V /85@VCC=3.0±0.3V 1201)/150@VCC=2.5±0.2V @VCC=2.0±0.2V
Standby (ISB1, Max)
Operating (ICC2, Max) 80mA 50mA
Type
K6F1016S4M-C K6F1016R4M-C K6F1016S4M-I K6F1016R4M-I
Commercial(0~70°C)
2.3~3.3V
5µA2)
20mA 80mA 50mA 20mA
44-TSOP2 Forward
Industrial(-40~85°C)
parameter measured with 30pF test load. Super power product=1µA with special handling.
DESCRIPTION
I/OI I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9
FUNCTIONAL BLOCK DIAGRAM
gen.
Precharge circuit.
Memory array 1024 rows columns
44-TSOP2 Forward
select
1~I/O8
Data cont Data cont Data cont
Circuit Column select
I/O9~I/O16
Name A0~A15
Function Chip Select Input Output Enable Input Write Enable Input Address Inputs
Name
Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8)
Control logic
I/O1~I/O16 Data Inputs/Outputs
N.C. Connection
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision February 1998
K6F1016S4M, K6F1016R4M Family
PRODUCT LIST
Commercial Temperature Products(0~70°C) Part Name K6F1016S4M-TB12 K6F1016S4M-TB15 K6F1016R4M-TB30 Function 44-TSOP2 120/70ns, 2.5/3.0V, 44-TSOP2 150/85ns, 2.5/3.0V, 44-TSOP2 300ns, 2.0/2.5V,
CMOS SRAM
Industrial Temperature Products(-40~85°C) Part Name K6F1016S4M-TF12 K6F1016S4M-TF15 K6F1016R4M-TF30 Function 44-TSOP2 120/70ns, 2.5/3.0V, 44-TSOP2 150/85ns, 2.5/3.0V, 44-TSOP2 300ns, 2.0/2.5V,
FUNCTIONAL DESCRIPTION
I/O1~8 High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Deselected Output Disabled Lower Byte Upper Byte Word Read Lower Byte Upper Byte Word Write
Power Standby Standby Active Active Active Active Active Active Active
means dont care.(Must high states.)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Soldering temperature time Symbol VIN,VOUT TSTG TSOLDER Ratings -0.2 3.6V -0.2 4.0V 260°C, 5sec(Lead Only) Unit Remark K6F1016S4M-C, K6F1016R4M-C K6F1016S4M-I, K6F1016R4M-I
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision February 1998
K6F1016S4M, K6F1016R4M Family
RECOMMENDED OPERATING CONDITIONS
Item Supply voltage Ground Symbol Product K6F1016S4M Family K6F1016R4M Family Family K6F1016S4M Family Input high voltage K6F1016R4M Family Input voltage Family Vcc=3.0±0.3V Vcc=2.5±0.2V Vcc=2.5±0.2V Vcc=2.0±0.2V -0.23) 2.5/3.0 2.0/2.5
CMOS SRAM
Unit
Vcc+0.22)
Note Commercial Product TA=0 70°C, unless otherwise specified Industrial Product TA=-40 85°C, unless otherwise specified Overshoot 1.0V case pulse width 20ns Undershoot -1.0V case pulse width 20ns Overshoot undershoot sampled, 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ICC1 Average operating current ICC2
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, =VIL
Test Conditions VIN=Vss CS=VIH OE=VIH WE=VIL, VIO=Vss IIO=0mA, CS=VIL, VIN=VIL VIH, Read
Cycle time=1µs, 100% duty, IO=0mA, CS0.2V, VIN0.2V VINVCC -0.2V
Read Write Vcc=3.3V@70ns Vcc=2.7V@120ns Vcc=2.2V@300ns
Unit
2.1mA Vcc=3.0V Output voltage 0.5mA Vcc=2.5V 0.33mA Vcc=2.0V -1.0mA Vcc=3.0V Output high voltage -0.5mA Vcc=2.5V -0.44mA Vcc=2.0V Standby Current(TTL) Standby Current(CMOS) ISB1 CS=VIH LB=UB=VIH, Other inputs=VIL
CSVcc-0.2V LB=UBVcc-0.2V, CS0.2V, Other inputs=0~Vcc
Super power product=1µA with special handling.
Revision February 1998
K6F1016S4M, K6F1016R4M Family
OPERATING CONDITIONS
TEST CONDITIONS
(Test Load Test Input/Output Reference)
CMOS SRAM
VTM3) R12)
Input pulse level 2.2V Vcc=3.0V, 2.5V 1.8V Vcc=2.0V Input rising falling time Input output reference voltage 1.5V Vcc=3.0V 1.1V Vcc=2.5V 0.9V Vcc=2.0V Output load (See right) :CL=100pF+1TTL CL=30pF+1TTL
CL1)
R22)
Including scope capacitance =3070, 2=3150 V=2.8V CC=3.0V =2.3V CC=2.5V =1.8V CC=2.0V
CHARACTERISTICS (Commercial product :TA=0 70°C, Industrial product TA=-40 85°C
K6F1016S4M Family Vcc=2.3~3.3V, K6F1016R4M Family Vcc=1.8~2.7V) Speed Bins Parameter List Symbol 70ns Read cycle time Address access time Chip select output Output enable valid output Read Access Time Chip select low-Z output Output enable low-Z output Chip disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write pulse width Write Valid Write Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tLZ, tBLZ tOLZ tOHZ, tBHZ tWHZ 85ns 120ns 150ns 300ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CSVcc-0.2V Vcc=3.0V data retention waveform 5.02) Unit
CSVcc-0.2V(CS controlled) LB=UBVcc-0.2V, CS0.2V(LB, controlled) Super power product=1µA with special handling.
Revision February 1998
K6F1016S4M, K6F1016R4M Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1)
Address Data Previous Data Valid
CMOS SRAM
(Address Controlled, CS=OE=VIL, WE=VIH, or/and LB=VIL)
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address
tBHZ tOLZ tBLZ Data Valid tOHZ
Data
High-Z
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision February 1998
K6F1016S4M, K6F1016R4M Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
High-Z
TIMING WAVEFORM WRITE CYCLE(2) Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision February 1998
K6F1016S4M, K6F1016R4M Family
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends going high.
DATA RETENTION WAVE FORM
controlled
2.7/2.3/1.8V tSDR Data Retention Mode tRDR
2.2V CSVCC 0.2V LB=UBVcc-0.2V LB/UB
Revision February 1998
K6F1016S4M, K6F1016R4M Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (400F)
CMOS SRAM
Unit millimeter(inch)
0~8° 0.25 0.010 0.45 ~0.75 0.018 0.030
11.76 ±0.20 0.463 ±0.008
10.16 0.400
18.81 MAX. 0.741 18.41 ±0.10 0.725 ±0.004
0.05 0.15 0.002
0.50 0.020
1.00 ±0.10 0.039 ±0.004 0.805 0.032 0.35 ±0.10 0.014 ±0.004 0.80 0.0315 0.05 MIN. 0.002
1.20 MAX. 0.047
0.10 0.004
Revision February 1998

Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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