Multi Service Access Line Card Application Note Preliminary Draft
|
|
|
Top Searches for this datasheet
Multi Service Access Line Card Application Note
Preliminary Draft
HCLMSP-AN/D
More Information This Product, www.freescale.com
Motorola Network Processors
Application Note
Table Contents
Modification History Overview.4 Definitions, Acronyms Abbreviations Related Documents Application Mapping Network processor architecture.9 Data Paths Network processor components Processing.17 Statistics Management 4).21 6).32 Recirculation (CP3).35 IPv4 Segmentation 7.10 Reassembly 9).50 7.11 Classifier 7.12 processing switching (CP11) 7.13 MPLS (CP12).67 7.14 MLPPP 7.15 AAL1-Tx 7.16 AAL-1 7.17 Fabric Port 7.18 Table Lookup Unit.88 7.19 Buffer Management Unit.95 7.20 Queue Management Unit 7.21 configurations CPs, FP.97 7.22 A.99 HOST PROCESSOR ARCHITECTURE .103 HOST PACKET I/O.104 Resources.104 Packet Reception.104 Packet Transmission .105 CONSOLE COMMAND SHELL COMMANDS .105 10.1 Application Control.105 10.2 Table Maintenance Display .106 10.3 Link Configuration Status .106 10.4 Channel configuration Status .107 10.5 Configuration Status.107 10.6 Configuration Status.107 10.7 Configuration Status .107 10.8 Statistics .108 HOST PROCESSOR NETWORK PROCESSOR INTERFACE .108 11.1 PPP.108 11.2 ML-PPP .109 11.3 .110 11.4 IMA.110 11.5 A.111 IMPLEMENTATION DETAILS.111 12.1 ML-PPP .111
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
12.2 Soft Queues.111 HOST REFERENCE.114 13.1 Table .114 13.2 Link, Channel, .128 13.3 API.131 13.4 AAPI .135 13.5 .135 13.6 Control .136 13.7 Port .138 13.8 .140 13.9 SEGMENTATION .141 13.10 REASSEMBLY .141 13.11 MPLS .142 13.12 RECIRCULATION .143 13.13 SWITCHING .143 Appendix Optimizations done application .145
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
Modification History
Date Author Department Changes
06-Feb-03 14-Feb-03
Technologies Technologies
Networking Networking
14-Mar-03
J.Bednarek
Motorola, C-Port
Draft version. Additional information added Q-3, Performance calculations, IMEM/DMEM estimates, ATM, QoS, Host APIs Changes draft SNDF
Overview
This document describers design Multi Service Access (MSA) line card. intended audiences this document system architects, hardware designers, software designers, testers programmers line card based C-Port network processor family. reader this document expected have fair understanding C-3e architecture associated co-processor such (Traffic Management Coprocessor) with basic understanding C-Port Family Adapters Twister) (Mt-21) used design line card. line card application provides multiple services different ports. connected Twister Mt-21 chips. twister Mt-21 chip have T1/E1 interfaces supporting upto channels.(note, Mt-21 support even higher channels, 2048, this example, assuming 1000 channels). Feature Overview Standards Support This application supports following features:
T1/E1 interfaces supporting channels header processing reassembly MLPPP segmentation reassembly AAL1/5 segmentation reassembly ACell switching switching IPv4 Unicast Routing interfaces (PPP/ATM/FR) Multi-Protocol Label Switching (MPLS) interfaces Ingress Egress packet processing MPLS IntServ DiffServ ATraffic Management MPLS
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
line card intended work stack cards connected switching fabric communication with other cards well line cards that terminate ATMs. host module manages maintains statistics entire system. communication host with line cards through interface. Figure helps understanding intended line card.
Line card
interfaces
Aover SONET
Ainterfaces
Host Processor card
Switching Fabric
Figure card within access platform
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
Definitions, Acronyms Abbreviations
Abbreviation AAL-1 AABE CIDR CPRC DLCI DWRR HDLC ICMP ML/PPP MPLS NLPID Description AAdaptation Layer AAdaptation Layer Available Rate Assured Forwarding Address Resolution Protocol Asynchronous Transfer Mode ATraffic Management Best effort Beginning Message. Constant Rate Channel Classless Inter Domain Routing Common Part Indicator. Channel Processor RISC core. Cyclic Redundancy Check. Data Link Connection Identifier Dynamic Weighted Round Robin Expedited Forwarding Message. Forwarding Equivalence class Frame Relay High Level Data Link Control Header Error Control. Hash Trie Key. Internet Control Message Protocol Control Protocol. Internet Protocol Link Control Protocol Logical Link Control Local Management Interface Longest Prefix Match. Label switched path Management Information Block Multi-Link Multi-Protocol Label Switching Maximum transmission Unit Network Control Protocol Network Layer Protocol Operation, Administration Maintenance. Protocol Data Unit. Behavior Point Point Protocol Quality Service
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note RARP Reverse Address Resolution Protocol
Abbreviation SNAP VPCI
Description Random Early Discard Resource Management. Round Robin Service Data Unit. Subnetwork Access Protocol. Transport Control Protocol Time Division Multiplexing Table Lookup Unit. Traffic Management Co-Processor Type Service Time Live User-to-User Interface. AVirtual Connection Virtual Output Port AVirtual Path Virtual Path Identifier/Virtual Channel Identifier Weighted Fair queueing
Related Documents
This section lists down various documents used reference while developing this application notes. Line card software requirement specifications from C-Port. Guide C-Ware Applications, CST2.2 ACell Switch Application Guide, 2.1.1 791, Internet Protocol 1332, Internet Protocol Control Protocol (IPCP) 1471, Definitions Managed Objects Link Control Protocol Point-to-Point Protocol 1473, Definitions Managed Objects Network Control Protocol Point-to-Point Protocol 1661, Point Point Protocol (PPP) 1812, Requirements Version Routers 1990, Multilink Protocol (MP) 2427, Multiprotocol Interconnect over Frame Relay 2474, Definition Differentiated Services Field Field) IPv4 2475, Architecture Differentiated Services 2597, Assured Forwarding Group
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 2598, Expedited Forwarding 2702, Requirements Traffic Engineering Over MPLS 2684, Multi Protocol Encapsulation over AAdaptation Layer 2697, Single Rate Three Color Marker I.361, B-ISDN ALayer Specification I.363.1, B-ISDN AAdaptation Layer Specification: Type I.363.5, B-ISDN AAdaptation Layer Specification: Type I.610 B-ISDN Operation Maintenance Principles Functions AForum, Inverse Multiplexing A(IMA) Specification Version Frame Relay 10/100 Ethernet Switch Router Application Guide, CST2.1 C-ware User guide DiffDocQ-512003.doc Functionality Comparison Between "Old" Design Projected FPGA RFC3034 -Use Label Switching Frame Relay Networks specification 2702 Requirements traffic engineering over MPLS RFC3270 Multi-protocol label switching support differentiated services 3031 Multi-protocol label switching architecture 3032 MPLS label stack encoding Draft-ietf-mpls-ttl-04.txt Time Live Processing MPLS networks. 3035 MPLS using switching
Application Mapping
This application comprised many software components, each which divided into smaller components. functional partitioning software depicted figure with clustering re-circulation information. partitioning designed handle 1024 channels cluster. C-3e chosen implementing line card processing power T1/E1 line interfaces match also used managing traffic management Aand MPLS.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
T1/E1 Twister Mt-21
Cluster
ReCirc
Cluster ASEG ARAS
Classifier
C-3e
T1/E1 Cluster Twister Mt-21 Cluster MPLS MLPPP AAL1Tx AAL1 Queues traffic mgmt required) Initialization Host Communication AMPLS
UL-2
Host State Machine Statistics Mgmt Access
Byte Level Recirculation
Figure line card functional mapping C-3e
Network processor architecture
application consists many software components. component executes host other components execute various within C-3e. Each software components provides subset features application. Mapping between software components shown figure data paths between these components conceptualized group busses. this context, combined queues buffer memory forward data between components. queue number analogous address bus. Each buses implies different buffer descriptor format (for TDM, MPLS, on). traffic originating from channels will HDLC Transparent Chunk based channel configuration. HDLC traffic will further identified traffic traffic. buffer buffer descriptor specify interface component. Table below lists each components describes their interface. component have
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note multiple interfaces therefore multiple entries table. Unless specified otherwise table, port field indicates output port length field indicates number bytes buffer. various buffer formats described section 7.19 buffer descriptor formats described appropriate sections.
Component Buffer Format BT_ATM, BT_MPLS_FR, BT_MPLS_PPP, BT_MPLS_ABT_MPLS BT_HDLC BT_TDM_TRANSPARENT BT_ABT_HDLC BT_ADescriptor format AComments Only header field required
MPLS Transparent Chunk AN/A A
Only header field required Port indicates outport which maps group; only header field required Port indicates input port Port indicates input port Port indicates input port; reassembly will performed Only mcClass field required; segmentation will performed Port indicates input port; forwarding will performed Port indicates input port; encapsulation will removed forwarding performed
BT_IMA_CP, BT_IMA_FILLER BT_ABT_HDLC, BT_PPP, BT_MLPPP BT_IPV4, BT_CONTEXT_STATE, BT_NCP_xxx BT_IPV4 BT_HDLC, BT_PPP
AML-PPP
MPLS
Segmentation Reassembly
BT_MPLS_FR, BT_MPLS_PPP, BT_MPLS_ABT_FR BT_MPLS_PPP, BT_MPLS_FR, BT_MPLS_IPV4, BT_MPLS_ABT_IPV4 BT_A
MPLS
MPLS
Buffer type identifies egress port interface type.
A
EgressQueue field required. Port indicates input port; AAL-5 reassembly will performed
AAL-1
BT_IPV4 BT_TDM_TRANSPRENT BT_A
A
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
AAL-1 UL-2 Host BT_TDM_TRANSPRENT BT_ABT_ABT_AAll others AAAN/A
Port indicates input port; only header field required Port indicates input port
Data Paths
This section explains about various data paths originating from T1/E1 interfaces, flowing through other components going through T1/E1 interfaces. Twisters (Mt-21) supported this application.
6.1.1 Data Paths frames
This section describes conceptualized data flows frame received chunks will reassembled frame recirculated other component finally transmitted AAL5 chunks detailed flow shown figure described follows. frame received HDLC chunks gets reassembled identified frame based channel configuration. Then will enqueued queue further processing. component performs DLCI lookup. Based lookup response, will enqueue frame into queue MPLS queue. switching, will modify header (with DLCI value) enqueue into appropriate queue. component dequeues frame from queue, removes header enqueues packet into destination queue (TDM recirculation queue ASegmentation queue MPLS queue queue determined lookup port lookup result. MPLS removes header exists) from frame, performs label processing then enqueues packet destination queue (TDM recirculation queue ASegmentation queue queue traffic queue determined MPLS lookup result. Asegmentation component will segment packet into AAL5 cells, inserts Aheader enqueues these cells appropriate queue traffic queue. recirculation component encapsulates packet into frame, enqueues final transmission over channel. dequeues HDLC frame( frame frame, differentiation made between frame) Acells from queue. transmits chunks size bytes. ATM, each cell will into chunk. PPP, segments frame into chunks. treatment needed, packets will enqueued traffic queue from classifier ASegmentation MPLS components applying various parameters. provides marking/dropping, policing traffic shaping packet based configured traffic parameters.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note will enqueue conformant packets into queue. Non-conformant packets will either discarded marked.
Figure Data paths frames
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
6.1.2 Data Paths frames
This section describes data flow frames received chunks will reassembled frame recirculated other component finally transmitted AAL5 chunks detailed flow shown figure described follows. frame received HDLC chunks gets reassembled identified frame based channel configuration. Then will enqueued queue MLPPP queue MPLS queue component based protocol field frame. component dequeues frame from queue, removes header enqueues packet into destination queue (TDM recirc queue ASegmentation queue MPLS queue queue determined lookup port lookup result. MPLS removes header exists) from frame, performs label processing then enqueues packet destination queue (TDM recirc queue ASegmentation queue queue traffic queue needed)) determined MPLS lookup result. MLPPP component dequeues from queue, removes MLPPP encapsulation from frame, reassembles MLPPP fragments enqueues reassembled fragment queue. Asegmentation component will segment packet into AAL5 cells, inserts Aheader enqueues these cells appropriate queue traffic queue. recirculation component encapsulates packet into frame, enqueues final transmission over channel. dequeues frame frame AAL5 cells from queue. transmits chunks size bytes. ATM, each cell will into chunk. PPP, segments frame into chunks. treatment needed, packets will enqueued traffic queue from classifier ASegmentation MPLS components applying various parameters. provides marking/dropping, policing traffic shaping packet based configured traffic parameters. will en-queue conformant packets into queue. Non-conformant packets will either discarded marked.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
Figure Data paths frames
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
6.1.3 Flows Acells
This section describes data flow Acells received Acells will recirculated other component finally transmitted AAL5 chunks detailed flow shown figure described follows. Acells received chunks These will enqueued queue (Aswitching) queue. AAL5 cells enqueued into reassembly queue that performs table lookup send VPI/VCI values into reassembly queue. Areassembly component will de-queue reassembles cells into AAL5 PDU. will then enqueued into queue MPLS queue, component dequeues reassembled AAL5 from queue, enqueues into destination queue (TDM recirc queue ASegmentation queue MPLS queue queue needed)) determined lookup port lookup result. MPLS performs label processing then enqueues packet destination queue (TDM recirc queue ASegmentation queue queue traffic queue needed)) determined MPLS result entry. Asegmentation component will segment packet into AAL5 cells, modifies AAL5 header (with VPI/VCI) enqueues these cells queue traffic queue needed). recirc component encapsulates packet into frame, enqueues final transmission over channel. dequeues frame frame AAL5 cells from queue. transmits chunks bytes. ATM, each cell will into chunk. PPP, segments frame into chunks. needed, packets will enqueued traffic queue from classifier ASegmentation MPLS components applying various parameters. provides marking/dropping, policing traffic shaping packet based configured traffic parameters. will en-queue conformant packets into queue. Non-conformant packets will either discarded marked.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
Figure Data paths ACells
Network processor components
This section describes each features applications detail explains each component resource within used provide applications' features. Executive Processor RISC Core (XPRC) general-purpose processor that provides management, control, exception processing functions. controls boot configuration, initialization system components.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Channel Processors (CPs) components most closely associated with processing data from physical interface. There organized four clusters, each which contains four CPs. Each cluster performs several functions that processing data packets.
program partitioned into distinct `initialization' `main' executables. After loading running initialization executable, main executable loaded overlayed initialization executable, reducing IMEM used run-time. This partitioning scheme uses available IMEM resource fullest.
7.1.1 Initialization Program
initialization executable performs service initialization, configures system resources, loads CPs. particular, initialization executable does following: Allocates buffer pools. Allocates configures queues. Configures fabric port. Configures interfaces. Loads CPs. Defers main executable program. Arrays parameter values used initialize buffer pools queues. arrays made macros defined top-level configuration file (config.h).
7.1.2 Main Program
main executable completes necessary initialization starts before entering main loop. particular, main executable does following: Prints application banner including version number Restores offline table data. Offline table data used initialize tables without host intervention simulation purposes. Initializes correction table Starts enables fabric port. Starts some SDPs Initializes processing component. Initializes host communication component Enters main loop
main loop within performs processing handling described section "OAM processing" host communication updating statistics.
Processing
cells received forwarded processing. support application includes following: Forward Performance Monitoring Receive Monitoring
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Blocks user cells limited number VCCs (128) monitored errors flow. BIP-16 generated cell payloads each block where block size configurable. block size defaulted cells. receiver checks parity received block data compares results with received BIP-16. number errors determined written statistics counter indicated
processing uses table described section 7.18.4.
7.2.1
support performance monitoring. processors following: 7.2.1.1 RxSync RxSync processor performs following functions: Determines CRC-10 each cell received (regardless whether cell not) forwards pass-fail notification RxByte processor. RxSync configurable through control space. 7.2.1.2 RxByte RxByte processor performs following functions: Determines whether F4/F5 cell been received indicates this extract space. Writes cell payload overhead extract space. Forwards CRC-10 pass/fail indication through extract space. Determines BIP-16 value each cell received writes this value extract space. Determines whether user cell been received writes this information extract space.
7.2.2
performs higher level processing data packets support -FPM. 7.2.2.1 Initialization During initialization, entry table initialized. 7.2.2.2 Receive receive thread handles incoming data packets performs specific operations. Specifically, does following:
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Checks whether received cell where being performed. This information stored table (the oamPm field). this cell user cell, does following: XORs current value BIP-16 into table running total user cells. Increments masks CurrentBlockValue (ranges from BlockSize-1). received cell user cell, then code checks whether cell been received. type cell, cell forwarded Otherwise, does following: Compares CurrentBip16 value with value received Cell. these values XOR-ed, number bits indicates number errors. number bits determined through lookup into 16-byte table (where each byte table indicates number bits index) each nibble (oamPmErrTab). information used update TotalBip16Errs counter.
7.2.3 Data Structures
7.2.3.1 OamPmTable This processor maintains performance monitoring state information following data structure:
Bytes
TotalBip16Errs CurrentBip16 SeqnumExpect
CurrentBlockValue blockSize
totalBip16Errs count BIP-16 errors calculated currentBlockValue number cell current block currentBip16 value BIP-16 calculated blockSize block size cells) seqNumExpect expected sequence number received unused
Statistics Managem
XPRC maintains statistics applications. Periodically, updates host with statistics available user. passes statistics storage pointer CP's initialization. update statistics maintained time. XPRC only 16kB DMEM shared across CPs, time update host should depend amount storage, which needed store statistics. synchronize between updating DMEM updating host, following implementation used:
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note maintains banks each DATA section (data section which accessible CPs). keeps shuffling pointer between these data banks periodically, that time updating host, should access update other bank 8KB. list statistics maintained channel basis follows: chRxChunks Number received chunks chRxPdus Number received PDUs chRxBytes Number received bytes chRxLenErrs Number chunks having invalid length (e.g. short chunk, long chunk) chRxCrcErrs Number chunks having invalid chRxBip8Errs Number chunks having BIP8 errors chRxInvalidErrs Number chunks having other errors chRxFlowChunks Number Flow chunks chRxLookupErrs Number chunks that caused lookup failure chTxChunks Number transmitted chunks chTxPdus Number transmitted PDUs chTxBytes Number transmitted bytes List statistics: IpInReceives Total number packets received module IpInHdrErrors number input datagrams discarded errors their headers. IpForwDatagrams Number input datagrams forwarded IpOutPayloadErrors Number packets discarded payload errors IpOutInvalidPortErrors Number packets discarded because route entry mapped invalid egress port. IpOutNoRoutes Number datagrams discarded because route could found transmit them their destination following statistics provided basis maximum 2048) AAL5 Errors Over Sized PDUs AAL5InReceives Within DMEM, following calculation time number bits used hold values, implemented: Generally, assign bits store value each statistic parameter, total sufficient hold parameters. some parameters have removed from this list statistics (or) statistics have provided using table support. AAL5 statistics parameters removed, total sufficient hold parameters. Calculating time updating host: channel, chunks received second i.e., bytes second. bits used chRxChunks, then will have update host after every chunk. That works around milliseconds.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
implement components application. Channel Processors directly connected Twister Mt-21 from outside world. number channels supported 2048 (1024 each component). channel carry ATM/FR/PPP traffic. Chunk size support this application 64-bytes.
7.4.1 RxSDP
receives data from Twister Mt-21 receive direction from Twister Mt-21 transmit direction. chunks that will originate from Twister Mt-21 will either HDLC chunks. During initialization phase itself interfaces will configured Since possible differentiate HDLC frames RxByte, CPRC will differentiate chunks based channel information filled extract space. channel will stored extract space RxByte processor. channel configuration stored DMEM, which used identifying protocol running that channel. functions provided each component processors described below. 7.4.1.1 RxByte RxByte processor performs following: Checks recirculation mode. Non-recirculation mode, receives bytes from RxSync processor. also writes previously dropped chunks counter extract space. Initializes DroppedChunks registers Reads chunk type, channel channel type into extract space. Reads UserValid, HDLC chunk length, HDLC UserInd (SOP/non-SOP) into extract space User chunks. (Chunk type will determine whether user chunk flow chunk). Reads HDLC crcInd into extract space. flow chunk, Verifies flow control chunk valid Writes flow control chunk count extract space. Indicates processing complete CPRC. user chunk, check channel type determine whether HDLC chunk Achunk. HDLC chunks HDLC chunks, check whether chunk non-SOP. chunk, Write first bytes after chunk header into extract space. reason writing bytes into extract space both need bytes eight bytes respectively specify header information packet MPLS packet). done that RxCPRC start processing based extract space values.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Send remaining bytes payload chunk DMEM. non-SOP chunk, sets done RxCPRC sends remaining bytes payload chunk DMEM. When data9 received, writes chunk status code extract space switches scope.
Achunks Achunks, launches lookup into AVPI/VCI table user cells. Identifies reports OAM/RM cells. Writes cell header extract space also. Writes Acell payload extract space also. Sets done RxCPRC sends remaining bytes cell payload chunk DMEM. When data9 received, writes chunk status code extract space switches scope. Transparent chunks transparent chunks, writes channel (port) extract space. done that RxCPRC start processing based extract space values. Sends remaining bytes payload chunk DMEM. When data9 received, writes chunk status code extract space switches scope.
7.4.2 (CP0 CP4)
performs higher level processing chunks. functions provided each components described below: 7.4.2.1 Initialization component initializes data structures registers used Specifically, does following: Initializes statistics chunk reassembly control structures Initializes RxSDP control space, control blocks ring registers AVPI/VCI table lookups. 7.4.2.2 Chunk Processing handles incoming Acells HDLC frames Transparent chunks. Specifically, does following: HDLC Waits done that completed header processing necessary information into extract space. Make pointer (chRxCCBPtr) Control block DMEM. chRxCCBPtr will depict chunks reassembly information DMEM. Processes chunk based chunk type (flow control user) extract space after checking errors.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note User chunk, differentiate HDLC frame chunks based Channel filled extract space channel configuration information.
processing chunk, Allocate buffer reassembling chunks Destination queue will processing queue. header information properly interpreting extract space. Write header into channel control block (chRxCCBPtr). Initiate payload transfer from DMEM SDRAM error indicated chunk. Update buffer offset channel control block (chRxCCBPtr) incrementing with chunk length. non-SOM chunks, retrieve reassembly state information (buffer handle buffer offset) from channel control block (chRxCCBPtr) initiate payload transfer from DMEM SDRAM error indicated chunk. Also, update buffer offset channel control block (chRxCCBPtr). chunk, build descriptor with buffer handle, buffer length header (DLCI value). En-queue processing queue. processing chunk, Read 4-byte header from extract space check protocol length. protocol 1-byte byte. least significant first protocol byte cleared, then protocol will bytes. buffer type following based protocol field value: value 0x0021, bufferType will BT_IPV4 value 0x0821, bufferType will BT_MPLS value 0x003d, bufferType will BT_MLPPP Read 4-bytes MLheader from extract space MLPPP. Allocate buffer determine destination queue based buffer type. destination queues will IP_QUEUE, MPLS_QUEUE MLPPP_QUEUE Write bufferHandle, destination queue MLheader into control block (ChRxCCBPtr). Buffer offset will SOM.
Initiate payload transfer from DMEM SDRAM error indicated chunk. Update buffer offset channel control block (chRxCCBPtr) incrementing chunk length. non-SOM chunks, retrieve reassembly state information (buffer handle buffer offset) from channel control block (chRxCCBPtr) initiate payload transfer from DMEM SDRAM error indicated chunk. Also update buffer offset channel control block (chRxCCBPtr). chunk, build queue descriptor en-queue destination queue taken from channel control block (chRxCCBPtr). port buffer
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note type will filled with concatenation input channel BT_HDLC descriptor. MPLS inIfType_action will filled MPLS_PPP. Gives scope back SDP.
ARx: component handles Acells. Specifically, does following: Waits AVPI/VCI lookup complete Lookup failure causes cell dropped statistics counter incremented. Allocates buffer initiates payload transfer from DMEM SDRAM. Builds descriptor with forwarding information from lookup response Waits payload transfer complete. Determines whether being performed this user cells, read current BIP16 value from extract space with current value. Update fields. cells, check BIP16 maintain count total BIP16 errors. cells other than AAL-5 AAL-1, launches port table lookup. Waits port lookup complete En-queues descriptor egress queue queue indicated port lookup AAL-5 cells, with lookup response from table, decision made AAL-5 MPLS switched. With last AAL-5 cell, fills descriptor with information required MPLS processing. reassembly module forwards this information MPLS processing module. AAL-1 cells, build descriptor with following fields: AAL1 header from extract space egress port vcIndex from lookup response. AAL-1 cells, destination queue AAL1Rx queue. En-queues descriptor destination queue Transparent chunk processing: This component handles transparent chunks. Specifically, does following Fetch egress port Acell header from channel control block indexed channel Allocates buffer initiates payload transfer from DMEM SDRAM. Builds descriptor with AAL1 information (egress port, egress cell header). Waits payload transfer complete. En-queues descriptor AAL1Tx queue
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
7.4.3 Data Structures
7.4.3.1 Extract Space RxByte writes information about data-grams into extract space typedef volatile struct int16u chnkType_chanId; int8u chanType; int8u userValid; int8u flowChunkCnt; int8u chunkStatus; int8u droppedChunks;
union struct CellHeader header; int16u bip16; int8u encodedPti; int8u payload[48]; }atm; struct int8u userInd; int8u crcInd; int8u chunkLength; int32u header1; int32u header2; int16u header3; }hdlc; proto; TdmExtract; explanations above-mentioned fields will follows: chnkType_chanId bitmap defined follows: chnkType specifies chunk type( user chunk flow chunk -11: unused. chanId specifies input channel chanType specifies channel type (HDLC/ATM). userValid specifies user valid indicator. flowChunkCnt specifies flow chunk counter. chunkStatus specifies chunk status (good chunk). droppedChunks number dropped chunks. userInd user indicator (BOM/COM/EOM). crcInd indicator (for CRC16 CRC32 calculation). chunkLength specifies chunk length. header1, header2, header3 HDLC header information could PPP)
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.4.3.2 Cell header cell header AAAL-5 cell. EncodedPti field identify Apayload type. atmPayload bytes AAL-5 cells. Control Block
state maintained DMEM) each HDLC frame being reassembled following data structure: Note: Some fields this block replaced maintain egress port Acell header every transparent channel configured.
Byte Offset
chBufHandle chBufOffset chMlHeader chDestQ
typedef struct BsBufHandle chBufHandle; int16u chBufOffset; int16u chDestQ; int32u chMlHeader; TdmRxCCB; explanations above-mentioned fields will follows: chBufHandle: specifies handle reassembled buffer. chBufOffset: specifies offset reassembled buffer. chDestQ: destination queue where chunk will en-queued. This field corresponds `egressPort' case transparent chunks. chMlHeader: header/FR header PPP/FR respectively. This field corresponds A`cellHeader' case transparent chunks.
7.4.3.3 Descriptor Structure following data structure descriptor en-queued.
Byte Offset
bufHandle Length AppData AppData Port_bufType
typedef struct BsBufHandle bufHandle; int16u length;
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note int16u union port_bufType; int8u byte[8]; int16u hword[4]; int32u word[2]; AtmDescData atm; FrDescData frameRe; SegDescData seg; TdmDescData tdm; MlPppDescData mlPpp; MplsDescData mpls; Aal1TxDescData aal1Tx; Aal1RxDescData aal1Rx; appData; DescriptorMsg;
explanations above-mentioned fields will follows: bufHandle specifies handle reassembled buffer. length specifies chunk length. port_bufType specifies input port buffer type next module. appData Application specific data (FR/PPP/ATM/Transparent TDM).
7.4.3.4 Ring Slots needs launch lookups following tables various packet processing: Table Port Table. table lookup uses these slots: request slot response slot Port table lookup uses these slots: Port table request slot Port table response slot
7.4.4 statistics
typedef struct int16u chRxChunks; int16u chRxPdus; int16u chRxBytes; int16u chRxBip8Errs; Acells int16u chRxLenErrs; int16u chRxInvalidErrs; int16u chRxCrcErrs; int16u chRxFlowChunks;
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note int16u int16u int16u int16u TdmStats; chRxLookupErrs; chTxChunks; chTxPdus; chTxBytes; //for Acells
description each field given below. chRxChunks Number received chunks chRxPdus Number received PDUs chRxBytes Number received bytes chRxLenErrs Number chunks having invalid length (e.g. short chunk, long chunk) chRxCrcErrs Number chunks having invalid chRxBip8Errs Number chunks having BIP8 errors chRxInvalidErrs Number chunks having other errors chRxFlowChunks Number Flow chunks chRxLookupErrs Number chunks that caused lookup failure chTxChunks Number transmitted chunks chTxPdus Number transmitted PDUs chTxBytes Number transmitted bytes
implement processing. transmit direction, this processor handles outgoing cells from other Aprocesses sends them round robin fashion among several links group. generates filler cells maintains link group state machines necessary connections. receive direction, processor receives cells from links performs synchronization reconstruct Acell stream. handles filler cells maintains link group state machines necessary connections. component does SDP.
7.5.1
Since component does SDP, this section filled
7.5.2
component uses three threads perform task, namely, Receive thread Transmit threads. 7.5.2.1 Receive Receive thread processes cells received from links following manner: Waits descriptor available queue then de-queues Determines group link based input port from descriptor. cells, does following: Initiates transfer cell payload from SDRAM local DMEM.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note cell stuffed cell, dropped. link state machine based link state information from cell. group state machine based group state information from cell. frame synchronization state machine. frame sync, cell link differential delay queue filler cell. filler user cells, frame synchronization been attained link active, cell link differential delay queue. Uses round robin determine which link differential delay queue group service. Removes cell from link differential delay queue does following: cell filler cell, dropped. cell user cell, en-queued next processing block (AAL1, ATM, etc.) determined data descriptor. Switches next context. Loops waits next descriptor.
7.5.2.2 Transmit Input Transmit Input thread de-queues cells puts them transmit soft queues following manner: Waits descriptor available queue, then de-queues Determines group based output port from descriptor. Puts user cell transmit soft queue group Switches next context Loops waits next descriptor. 7.5.2.3 Transmit Output Transmit Output thread runs group cell rate. each tick group cell rate clock, thread does following: Determines link within group, which should receive next cell. This done round robin fashion among active usable links group. time send cell link, group state cell storage updated current link cell transferred SDRAM buffer DMA. descriptor built en-queued queue target link. Otherwise, link active state user cell available transmit soft queue link, descriptor user cell removed from soft queue en-queued queue target link. Otherwise, filler cell en-queued queue target link. Updates link group state link group which cell just sent. Switches next context. Loops waits next tick.
7.5.3 Data Structures
component uses following data structures maintain state translate data.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.5.3.1 ImaLinkState link state structure saves state information each available ATDM links. structure following format:
Byte Offset
LinkId feState txFrameSeqNum
flags frameSync numIcpValid
rxState frameOffset numIcpErrors
txState rxFrameSeqNum numIcpInvalid
linkId link number flags bitmask defined follows: b7-5: unused link valid received link valid failure receive failure occurred fault receive fault occurred fault transmit fault occurred inhibit link being inhibited rxState value link state machine txState value link state machine feState values link state machine defects frameSync value frame synchronization state machine frameOffset offset within frame which cell should appear rxFrameSeqNum expected received frame sequence number txFrameSeqNum frame sequence number transmitted numIcpValid number consecutive frames with valid cells used frame synchronization numIcpErrors number consecutive frames with error cells used frame synchronization numIcpInvalid number consecutive frames with invalid cells used frame synchronization
7.5.3.2 ImaGroupState group state structure saves state information each groups. structure following format:
Byte Offset 0-11 16-47
icpCell linkIdAlloc linkIdToLinkMap frameLen state change rxchangenum txChangeNum suffLinks flags rxOamLabel
feState numLinks rxImaId
explanation fields given below: icpCell cell sent thread linkIdAlloc bitmap indicating which link
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note linkIdToLinkMap[32] mapping from link link state storage structure frameLen length frame (32, 128, 256) state group state machine state feState group state machine state change flag indicating next cell transmitted will have change rxChangeNum received status control sequence number txChangedNum next status control sequence number transmit cell numLinks number active links suffLinks number active links needed leave insufficient links state flags bitmap follows: b7-1: unused inhibit group being inhibited rxOamLabel received label cell rxImaId received cell
7.5.3.3 ImaParams parameters structure stores information that controls behavior unit. host other management agent these parameters. structure following format:
Byte Offset
alpha
beta
gamma
Alpha number consecutive invalid cells that must received before frame synchronization lost Beta number consecutive errored cells that must received before frame synchronization lost Gamma number consecutive valid cells that must received before frame synchronization declared
7.5.3.4 ImaPortToGroupMap port group array bytes MAX_TDM_CHANNELS (1024 cluster) long. index into array port number value array elements group which port belongs. port does belong group, value IMA_INVALID_GROUP. 7.5.3.5 ImaPortToLinkMap port link array bytes MAX_TDM_CHANNELS long. index into array port number value array elements link state index associated with port. This index used index link state structure array. 7.5.3.6 Merge space This information need provided because SDPs going used
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.5.3.7 Extract Space This information need provided because SDPs going used 7.5.3.8 Descriptor information available 7.5.3.9 None Ring Slots
7.5.4 Issues/Enhancements
component placed CPs. This because DMEM size required component.
implement components application.
7.6.1 TxSDP
TxSDP moves data from Mt-21 chip. functions provided each component processors described below. 7.6.1.1 TxByte TxByte processor performs following functions part interface: Reads bytes chunk header information from merge space transmits chunk header. Sets chunk length counter. channel type HDLC, reads payload bytes from DMEM transmits them. Transmits padding bytes (zero) last until chunk length counter reaches zero ASOM chunks, reads Acell header from merge space adds transmits. AOAM cells, generates CRC-10. transparent chunks, read payload bytes from DMEM transmits them. merge9 with last byte. Switches scope CPRC.
7.6.2 (CP2 CP6)
performs higher level processing chunks. functions provided each components described below: 7.6.2.1 Initialization component initializes data structures registers used Specifically, does following: Initializes statistics chunk segmentation control structures
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Initializes TxSDP control space control blocks
7.6.2.2 Chunk Transmit output thread handles outgoing cells datagrams. Specifically, does following: Check channels round robin manner credits available (chFlowChunksAvail). state information current channel i.e. pointer chTxCCBPtr which points channel control block DMEM. This control block will contain segmentation state information. chFlowChunksAvail true, check whether this channel process segmenting into chunks i.e. transmitting chunks PDU. next chunk will transmitted. segmentation progress, incoming descriptor will de-queued from queue. Note that descriptor would have been en-queued Recirculation (CP3 encapsulation) module (CP11 switching) Asegmentation (CP8) AAL1 Tx(CP14 AAL1 Rx(CP15) After de-queuing, segmentation state will updated with values fetched from descriptor. Segmentation state values updated are: Buffer Handle, Buffer offset, length port buffer type taken from incoming descriptor. Offset will filled zero PortBufferType will checked determine incoming module i.e. from which module come (BT_Aor BT_TRANSPARENT others) that will segment accordingly. portBufferType BT_TRANSPARENT, transparent chunk from AAL1 fills merge space with chanId_chanType, chunkLength. portBufferType BT_ATM, Acell hence will switched. portBufferType other than BT_ATM, frame needs segmented into number chunks based channel length chTxCCBPtr. segmenting into chunks, chunk length bytes) will calculated based offset ChTxCCBPtr (for first chunk, offset will Also chunk length less than bytes, will flag stating that last chunk. offset chTxCCBPtr will incremented chunk length next chunk. waits scope available from SDP. fills merge space with chanId_chanType, chunkLength userInd. ATM, fills cell header also into merge space. then waits payload transfer previous chunk complete. initiates payload transfer from SDRAM DMEM that chunk. chunk, frees buffer associated with previous chunk resets state information chTxCCBPtr) PDU.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
7.6.3 Data Structures
7.6.3.1 Merge space writes information about datagrams into merge space. data structure merge header looks like following. typedef volatile struct int16u chanId_chanType; int8u userChunkLength; int8u userInd; union struct CellHeader atmHeader; int8u atmPayload[48]; }atm; struct int8u pad1; }hdlc; struct int32u header; int8u headerLen; }pppRecirc; }proto; int8u pad[8]; TdmMerge; explanations above-mentioned fields will follows: chanId_chanType bitmap defined follows: unused. chanId specifies input channel b3-1 chanType specifies channel Type (ATM/HDLC/Transparent) unused.
userChunkLength chunk length (1-64 bytes) userInd specifies user chunk indicator (SOM/COM/EOM) atmHeader ACell header atmPayload bytes Acells.
7.6.3.2 Control Block state maintained DMEM) segmentation each outgoing channel stored following data structure:
Byte Offset
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
chBufHandle chBufOffset ChFlowChunksAvail chLength
typedef struct BsBufHandle chBufHandle; int16u chBufOffset; int16u chLength; int8u chFlowChunksAvail; TdmTxCCB;
explanations above-mentioned fields will follows: ChBufHandle specifies Buffer handle that transmitted. ChBufOffset specifies offset chunk buffer. chLength: specifies chunk length. ChFlowChunksAvail specifies counts credits available each channel. Pad: unused.
7.6.3.3 Descriptor Structure descriptor structure same structure defined section 7.4.3.3
7.6.4 Statistics
statistics structure same structure defined section 7.4.4
Recirculation (CP3)
used recirculate frames destined (CP2/CP6) transmission. purpose header header descriptor PPP/FR frame before transmission.
7.7.1
adds header frame. functions provided each component processors described below. Only RxByte TxByte used this purpose. 7.7.1.1 TxByte TxByte processor performs following functions: Reads channel from merge space transmits first byte chunk. Read Buftype from merge space. will also differentiate between Buftype BT_IP_FR BT_MPLS_FR, will frame.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note PPP, Reads header length from merge space, then reads that many bytes from header field merge space transmits these. Reads first bytes header (that contains DLCI values) from merge space transmits these. bufferType BT_IP_FR, transmits control byte (0x00) NLPID (0xcc) byte. bufferType BT_MPLS_FR, construct SNAP header encapsulation bytes transmit these bytes. Reads remaining payload from DMEM until data9 observed. Switches scope.
7.7.1.2 RxByte RxByte processor performs following functions: Receives bytes from TxByte processor. first byte chunk contains channel This written extract space header ready indicated rxStatus register. bytes written DMEM. When data9 received, switches scope.
7.7.2
manages recirculation. that want transmit PPP/FR frames, en-queue their packets recirculation that PPP/FR header added frame before transmission. 7.7.2.1 Initialization initialization component initializes data structures registers used Specifically, does following: Initializes statistics chunk control structures. Initialize control space, Tx/Rx control blocks. Indicate RxSDP recirculation portion code. 7.7.2.2 RxCPRC receive component handles incoming packets from SDP. Specifically, does following: Waits indication header processing completion. Creates descriptor with buffer handle length. En-queues packets based upon channel indicated extract space. Allocates buffer, sets block gives scope back SDP.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.7.2.3 TxCPRC transmit component services Recirculation egress queue (all traffic which needs header inserted frame gets en-queued here). This then passes chunks SDP. Specifically, does following: De-queues packet descriptor from Recirculation egress queue. This descriptor would have been en-queued MPLS channel processors. Waits scope available from SDP. Gets channel (input port) buffer type from descriptor. Buffer type following. BT_IP_FR: frame originates from module BT_MPLS_FR: frame originates from MPLS module Otherwise frame originating from IP/MPLS module Determines protocol type based buffer type. processing: buffer type BT_IP_PPP BT_MPLS_PPP, Determines 4-byte header including protocol, calculates header length. Fills channel BufType, header header length into merge space. processing: buffer type BT_IP_FR BT_MPLS_FR Fill channel BufType header information (2-bytes containing DLCI) from descriptor into merge space. Sets engine with buffer handle from descriptor. Initiates payload transfer from SDRAM DMEM gives scope SDP. Frees buffer from previous transmit this scope.
7.7.3 Data Structures
7.7.3.1 Merge space merge space structure defined below.
Byte Offset
chanId_chanType BufType header
userChunkLength header
userInd
explanations above-mentioned fields will follows chanId_chanType bitmap defined follows:
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note unused. chanId specifies input channel b3-1 chanType specifies channel Type (ATM/HDLC/Transparent) unused.
UserChunkLength: specifies length user chunk. UserInd: specifies user chunk indicator (BOM/COM/EOM) BufType: specifies type buffer. header: specifies DLCI value congestion control information. Pad: unused
Byte Offset
chanId_chanType userChunkLength BufType header header PPPheaderLen
userInd
explanations above-mentioned fields will follows chanId_chanType bitmap defined follows: unused. chanId specifies input channel b3-1 chanType specifies channel Type (ATM/HDLC/Transparent) unused. UserChunkLength: specifies length user chunk. UserInd: specifies user chunk indicator (BOM/COM/EOM) BufType: specifies type buffer. header: specifies header information. headerLen: specifies length header. Pad: unused
7.7.3.2 Extract space extract space structure defined below.
Byte Offset
chanId
explanations above-mentioned fields will follows ChanId: specifies channel Pad: unused.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.7.3.3 Descriptor descriptor structure same structure defined section 7.4.3.3.
IPv4
implements IPv4 (Layer forwarding) component application. routing process forwarding frames layer based upon Destination Address DA). advantage routing that used between dissimilar network media types. This application covers routing over Frame Relay PPP/MLPPP. Assumptions notes use: header options will recognized. Fragmentation reassembly supported Lookup launched Application generates types ICMP messages, which based events that happen data path: ICMP Time exceeded ICMP destination unreachable address provided appData parameters shared (Host Communication Area) structure. passes this address initialization descriptor. uses this source address generated ICMP messages.
7.8.1
configured byte level re-circulation. re-circulates packet remove HDLC/PPP/FR encapsulation present validates header. also launches destination address lookup retrieve forwarding parameters datagram. 7.8.1.1 TxByte TxByte processor performs following functions: Receives datagram from through DMEM. Based Buffer Type, following operations done: BT_HDLC/BT_PPP/BT_FR: strips respective headers does parsing BT_IP: Parses header Sends control information about datagram RxByte processor, including buffer handle, buffer type, input port. Sends datagram RxByte processor. Sends packet byte which indicates errors non-zero. Switches scope waits more data available DMEM. writes information about datagrams needing re-circulation into merge space TxByte processor processing. data structure defined section 7.8.3.1. TxByte processor configurable through control space.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.8.1.2 RxByte RxByte processor performs following functions: Waits receive scope become available. Receives control information from TxByte processor places extract space. Validates header including version header length checksum field. header valid, launches lookup destination address header valid, places error code header status field extract space does launch lookup. error, verification decrement operations done checksum modification done updated accordingly Streams remaining payload DMEM writes payload status field extract space. Switches scope waits another become available. RxByte processor writes information about recirculated datagrams into extract space processing. data structure defined section 7.8.3.2. RxByte configurable through control space.
7.8.2
forwarding component uses threads perform task, namely, input thread output thread. initialization code starts threads. Each these described next. 7.8.2.1 Initialization component does following things during initialization: Creates input output threads. Initializes route lookup launched SDP. Initializes both scopes giving ownership. Starts byte loop back mode. Jumps first thread. 7.8.2.2 Input Thread input thread handles incoming datagrams. Specifically, does following: Monitors queue. De-queues descriptor. Increments statistics counter Waits transmit scope available from SDP. Fills merge space with data from descriptor including buffer handle input port. Waits previous transfer complete. Begins transfer current buffer being processed. Switch context next thread.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Loops beginning wait another descriptor.
7.8.2.3 Output Thread output thread handles outgoing datagrams. Specifically, does following: Waits scope become available from SDP. Begins transfer from DMEM SDRAM buffer indicated extract space. Checks header errors, occurred, drops packet increments ipInHdrErrors counter. error because expiry, ICMP time expired message sent source. Waits route lookup complete lookup fails, drops packet increments ipOutNoRoutes counter. Send ICMP destination unreachable message source. lookup response indicates that packet MPLS switched, then Fills information from route lookup Destination queue MPLS_QUEUE Else Launches lookup port indicated route lookup response. Waits port lookup complete, port invalid, drops packets increments ipOutInvalidPortError counter. Fills descriptor using information from route port lookups. Waits payload transfer complete. Check payload error, drops packet increments ipOutPayloadError counter. Sends descriptor appropriate destination determined lookups. enabled then sends descriptor queue based port table entry. Increments ipForwDatagrams counter Switches context next thread. Loops beginning wait another scope available.
7.8.3 Data Structures
7.8.3.1 Merge space writes information about datagrams needing recirculation into merge space TxByte processor processing. data structure following format:
Byte Offset
bufHandle port_bufType
bufHandle handle buffer being recirculated port_bufType bitmask defined follows: b15-5: port input port which this datagram received
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note b4-0: bufType type buffer being recirculated (could BT_IPv4, BT_FR ,BT_PPP) unused Extract Space
7.8.3.2
RxByte writes information about re-circulated datagrams into extract space processing. Entire header moved into extract space. first bytes data structure following format:
Byte Offset
port_bufType
bufHandle headerError
payloadError
bufHandle handle buffer being recirculated port_bufType bitmask defined follows: b15-5: port input port which this datagram received b4-0: bufType type buffer being recirculated (could BT_IPv4)
format next part extract space
Byte Offset 28-44
vers_hlen
protocol srcaddr destaddr
flags_fragOffset
vers_hlen header version length type service total length identification field frags_fragOffset fragmentation flags offset time live protocol protocol header checksum srcaddr source address destaddr destination address unused
7.8.3.3 Queue Descriptor information queue allocated module communicate with other XPRC. Queue descriptor structure follows:
Byte Offset
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
BufHandle Length appData appData Port_bufType
explanation each field follows: bufHandle handle buffer this descriptor describes length length data buffer port_bufType field structure follows: b15-5: port ingress port egress port depending descriptor type b4-0: bufType type buffer appData application specific data defined below: Application specific data, union int8u byte[8]; int16u hword[4]; int32u word[2]; AtmDescData atm; FrDescData frameRe; SegDescData seg; TdmDescData tdm; MlPppDescData mlPpp; MplsDescData mpls
appData field have different interpretations depending outgoing interface type. AappData field following format:
Byte Offset
cellHeader VcIndex egressQueue
explanation each field follows: cellHeader cell header (VPI/VCI) apply egress vcIndex index associated with egress VPI/VCI egressQueue egress queue, necessary cell passes through several processing blocks appData field following format:
Byte Offset
McClass
Flags
Egress Queue
explanation each field follows: mcClass class ML-PPP's egressQueue egress queue, necessary packet passes through several processing blocks MPLS appData field following format:
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
Byte Offset
LabelSwap HopCount InIfType_action AppHdrData Index
LabelPush EgressQueue
explanation each field follows: LabelSwap Label swapped LabelPush Label added InIfType_action- MPLS action performed HopCount count decremented shim header Egress queue Queue assigned egress interface AppHdrData ACell header case egress Ainterface header interface. VcIndex index Ainterface AAL-5 unused FrameRelay appData field following format:
Byte Offset
FrHeader EgressQueue
explanation each field follows: FrHeader DLCI value EgressQueue Final Queue unused 7.8.3.4 Counters module these counters statistics purpose; it's stored XPRC's shared DMEM. S.No Counter Purpose ipInReceives Total number packets received module IpInHdrErrors number input datagrams discarded errors their headers. IpForwDatagrams Number input datagrams forwarded IpOutPayloadError Number packets discarded payload errors IpOutInvalidPortError Number packets discarded because route entry mapped egress port which invalid temporarily made inaccessible) IpOutNoRoutes Number datagrams discarded because route could found transmit them their destination 7.8.3.5 Ring Slots IPv4 uses these slots: IPv4 route request slot
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note IPv4 route response Port request slot Port response slot
Segmentation
implements AAL5 segmentation module. This gets message descriptors with bufType IPv4/MPLS.
7.9.1
configured byte level re-circulation. streams packet accumulates CRC. AAL5 cells, adds necessary bytes make length multiple creates trailer. then delivers fixed size chunks CPRC. first chunk SDU, launches port table lookup, whose results used CPRC determine destination queue. does interleave segmentations completely segments delivers CPRC before proceeding next SDU. accumulates payload packets. 7.9.1.1 TxByte TxByte processor performs following operations every packet: Reads segType, pduSize from merge space. Sends them RxByte processor. Read merge space fields following Send them RxByte processor. Initialize counter with negative payload size. Start sending payload bytes, incrementing counter each byte sent out. Accumulate each transmitted byte. Stop when counter hits 0xff. Initialize counter with number bytes. Start transmitting zeroes, incrementing this counter every zero byte transmitted. Accumulate each zero byte. Stop when counter hits 0xff. trailer should sent AAL-5 SDU. Send UUI, payload length, accumulating them. send four bytes CRC. This completes AAL5 trailer. Release transmit scope wait data available from TxByte gets payload information from merge space defined section 7.9.3.1. TxByte configurable through control space. 7.9.1.2 RxByte RxByte processor performs following sequence operations: Receive segType, pduSize from TxByte copy them extract space. Clear lastCell flag. Receive atmEgressQueue destQueue from TxByte write them extract space. Receive egress port from TxByte launch port table lookup. Initialize counter Counter1 with negative pduSize(0xc1).
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Stream payload bytes stage area. Increment Counter1 every byte transmitted. When Counter1 hits 0xff, hand current scope over CPRC. data-9 seen time payload, next step. Wait next scope become available back previous step. payload, data TxByte sets Data-9 bit. When this seen, last cell flag true. Copy current value Counter1 numBytesLastPdu field hand current scope over CPRC. packet segmentation complete this point, wait more data available from TxByte
RxByte processor writes information about incoming cells into extract space processing. data structure described section 7.9.3.2. RxByte configurable through control space
7.9.2
segmentation component uses threads perform task, namely, input thread output thread. initialization code starts threads. Each these described next. 7.9.2.1 Initialization initialization phase segmentation does following: Initializes buffer pools. Creates contexts input output threads Initializes ring message registers used RxByte launching port lookup. Setup engines initializes scopes. Enables SDPs 7.9.2.2 Input Thread input thread handles incoming datagrams. Specifically, does following: De-queue message descriptors from input queue Reads length packet segmented. Determines size Calculate number cells that would generated this SDU. Calculates necessary bytes that should added packet make size multiple bytes. Allocates scope Writes packet buffer handle, egress port egress queue from packet descriptor length merge space. Free scope, thus starting processing this packet. 7.9.2.3 Output Thread output thread handles outgoing datagrams. This logical function gets Acells from en-queues them appropriate destination queue. Specifically, carries following sequence operations: Allocate scope read extract space.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Check scope `new_sdu' flag set. set, then would have launched port table lookup. Read egress queue from extract space. Wait port table lookup results. enabled port, destination queue queue from port table lookup. enabled destination queue same egress queue from table lookup. Create message descriptor with bufType BT_ATM. buffer handle that cell delivered en-queue destination queue.
7.9.3 Data Structures
7.9.3.1 Merge space writes information about outgoing packets merge space TxByte processing. data structure following format:
Byte Offset
SegType PduSize PayloadLength PadLength CellHeader EgressPort AtmEgressQueue DestQueue
typedef struct int8u segType; int8u pduSize; int8u uui; int8u cpi; int16u payloadLength; int8u padLength; int8u pad; CellHeader cellHdr; int16u egressPort; int16u atmEgressQueue; int16u destQueue; SegMergeSpace; segType indicates whether packet segmented AAL5 (SEG_AAL5) pduSize specifies size chunks into which packet segmented (always AAL5) specifies user-to-user information reserved, zero payloadLength size packet padLength number zero bytes that need added payload Reserved
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
cellHdr specifies egress cell header used AAL5 egressPort destination port number atmEgressQueue specifies final queue that should used reach Aport destQueue specifies immediate destination queue from segmentation
7.9.3.2 Extract Space RxByte writes information about re-circulated datagrams into extract space processing. data structure following format:
Byte Offset
SegType
PduSize
egressPort destQueue
atmCellHdr AtmEgressQueue LastCell NumBytesLastPdu
typedef struct int8u segType; int8u pduSize; int8u uui; int8u pad; int32u atmCellHdr; int16u egressPort; int16u atmEgressQueue; int16u destQueue; int8u lastCell; int8u numBytesLastPdu; SegExtractSpace; segType indicates whether delivered chunk AAAL-5 cell payload pduSize specifies size Acell (always AAAL-5 cells) -zero Acells specifies user-to-user information that arrived with packet being segmented atmCellheader specifies egress cell header used AAL-5. EgressPort destination port number. atmEgressQueue final queue number used reach egress port destQueue specifies queue number which cell packet should transmitted lastCell specifies numBytesLast size last APDU
7.9.3.3 Descriptor information following data structure descriptor:
Byte Offset
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
bufHandle Length appData port_bufType
typedef struct BsBufHandle bufHandle; int16u length; int16u port_bufType; 15:5 port, bufType union int8u byte[8]; int16u hword[4]; int32u word[2]; AtmDescData atm; FrDescData frameRe; SegDescData seg; TdmDescData tdm; MlPppDescData mlPpp; MplsDescData mpls; appData; DescriptorMsg; bufHandle reassembly buffer handle length chunk length port_bufType input port buffer type next module appData Application specific data.
AppData segmentation following format: typedef struct SegDescData_s CellHeader cellHeader; int8u flags_cpsPduLen; flags; cpsPduLen int8u pad; int16u egressQueue; SegDescData;
Byte Offset
CellHeader Flags_cpsPduLen egressQueue
7.9.3.4 Ring Slots segmentation launches lookup into Port Table. uses following slots: Request Slot: Response Slot:
7.9.4 Issues/Enhancements
None
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
7.10 Reassembly
AAL5 re-assembly module implemented incoming message descriptor have different buffer types distinguishing between various packet types. buffer type BT_Aindicates that Acell descriptor needs processed AAL5 reassembly, while buffer types BT_MPLS_FR, BT_MPLS_PPP BT_MPLS_Aindicate that this last Acell MPLS packet reassembled MPLS packet information contained descriptor passed MPLS processing.
7.10.1
reassembly configured byte level loop back. performs payload initiates transaction append current cell packet SDU. non-last cell packet, initiates table update using command non-last mode. table indexed vcIndex. last cell SDU, command used last mode verify accumulated CRC. results come back ring examined CPRC. Specifically, functions performed each components described below: 7.10.1.1 TxByte TxByte processor performs following functions: Wait scope from CPRC Initialize accumulator. Forward bytes that contain MPLS related information MPLS packet. RxByte this takes care collect bytes prior collecting other bytes. Forward rasType, eom_offset, vcCidIndex, numalignedBytes numUnalignedByteCount RxByte. rasType indicates whether AAL5 AAL5_MPLS. VcCidIndex holds vcIndex value AAL5. field holds flag indicating whether this last cell packet. NumUnalignedBytes will always zero AAL5. Initialize counter Counter1 (with 0xc1) value numAlignedBytes. AAL5, this parameter always Initialize another counter Counter2 (with value 0xc2) numBytesPartialPayload. Start sending partial payload bytes from merge space, incrementing Counter2 every byte. When this counter hits 0xff, unaligned bytes would have been sent. Accumulate partial every byte transmitted. start sending payload bytes, incrementing Counter1 every byte accumulate CRC. Stop accumulating when counter hits 0xff. Send remaining payload bytes. These unaligned bytes will recirculated next packet. Hence should computed these bytes. After sending payload bytes, partial accumulated thus sent. this point TxByte done with processing cell. gives scope CPRC waits next cell/packet.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note writes information about cells reassembled into merge space TxByte processing. data structure described section 7.10.3.1. TxByte processor configurable through control space. 7.10.1.2 RxByte RxByte processor performs following functions: Wait extract scope from CPRC. Streams bytes, which contain information relevant MPLS packet processing Stream rasType, eom, vcCidIndex, pduLength numUnalignedByteCount extract space. pduLength aligned byte count received from TxByte. Make scope available CPRC, setting L1_DONE flag. Start streaming payload into staging area. CPRC will setup transfer into SDRAM correct offset. counter determine when payload ends. Copy last bytes payload into extract space structures uui, cpi, length CRC. case this last cell, CPRC will need this information forwarding this packet CPRC. This information should also staging area. After payload ends, next bytes accumulated CRC. Initiate command using this CRC. Mark scope status flags L2_DONE, thus giving trailer CPRC. Wait another scope available from CPRC. RxByte writes information about PDUs being reassembled into extract space processing. data structure described section 7.10.3.2. RxByte processor configurable through control space.
7.10.2
reassembly component uses threads perform task, namely, input thread output thread. initialization code starts threads. Each these described next. 7.10.2.1 Initialization initialization phase segmentation does following: Initializes buffer pools. Creates contexts input output threads Initializes ring message registers used RxByte Table. Setup engines initializes scopes. Enables SDPs 7.10.2.2 Input Thread input thread handles incoming datagrams. Specifically, does following: De-queues input Acell descriptors
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Checks buffer type incoming AAL-5 SDU. Buffer Type hold following values: BT_ATM: indicates packet AAL-5 PDU. fills merge space with information required RxByte reassemble Acells output thread. BT_MPLS_ATM: indicates AAL-5 MPLS switched egress interface Ainterface. BT_MPLS_PPP: indicates AAL-5 MPLS switched egress interface interface. BT_MPLS_FR: indicates AAL-5 MPLS switched egress interface interface.
AAL-5 SDUs which MPLS switched, there additional bytes information which needs sent across MPLS processing module after cells reassembled. These bytes information follows: LabelSwap (2-Bytes) LabelPush (2-Bytes) Egress Port buffer type (2-Bytes) count MPLS action (2-Bytes) Egress cell header egress interface Ainterface (4Bytes).These bytes streamed TxSDP before other information. Starts packet releases scope merge space.
7.10.2.3 Output Thread output thread handles outgoing reassembled AAL-5 SDUs. Specifically, performs following activities: Maintains rasList structure track re-assembly state array 1024 RasList structures maintained DMEM. This array indexed vcIndex from table input cell's VCI. vcIndex AAL5 VCCs hence restricted range 1023]. Each element this array initialized with valid buffer handle offset zero. After receives cell AAL-5 reassembly, locates state entry rasList array, using cell's vcIndex. buffer handle this specifies SDRAM buffer which this cell needs appended. offset specifies length AAL-5 reassembled far. This cell needs written `offset' location within SDRAM buffer. Reads extract space updates offset corresponding rasList array entry. Flag extract space, current completed. When this flag set, output thread performs following operations: Reads rasType indicates MPLS switched SDU.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note type RAS_MPLS_ATM, then fills descriptor 12-bytes information MPLS processing module. Wait results from TLU: accumulates each table, using command mode. last cell, issues command with last option. Upon getting this command, first accumulates command then checks accumulated indicates success. returns ring success response success ring error otherwise. response success, message descriptor created SDU. then waits deliver aal5 trailer. trailer contains length, aal5 CRC. fills length field message descriptor using length field from trailer dispatches message descriptor CPRC. then sets offset field rasList entry zero allocates buffer next this VCC. response indicates failure, means that AAL5 suffered errors transit should discarded. offset zero that next this reuse current SDRAM buffer. descriptor case valid SDUs then queued appropriate queue. MPLS Switched SDUs, queues MPLS else module. maximum permitted size restricted 2048 bytes application. offset field rasList entry exceeds 2048, discarded. that exceeds 2048 bytes, subsequent Acells appended last bytes buffer when output thread finds offset exceed 2048, always copies current cell into last bytes. When last cell this arrives, cell copied into last bytes offset then zero. This effectively discards makes buffer available next SDU. Frees scope RxSDP
7.10.3
Data Structures
7.10.3.1 Merge space writes information about outgoing packets merge space TxByte processing. data structure following format:
Byte Offset
rasType Eom_offset NumAlignedBytes NumUnalignedBytes
vcCidIndex NumBytes pduLen PartialPayload PartialPayload PartialPayload PartialPayload PartialPayload
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
AppData AppData AppHdrData
typedef struct{ int8u rasType; int8u eom_offset; int16u vcCidIndex; int8u numAlignedBytes; int8u numUnAlignedBytes; int8u numBytesPartialPayload; int8u pduLen; int8u partialPayload[16]; Partial Payload int16u data[4]; int32u appHdrdata; RasMergeSpace;;
rasType 0x00 AAL5 0x01 MPLS Switched AAL-5 0x00 this last cell 0x80 last cell vcCidIndex Index numAligned number bytes data stream that should transferred SDRAM numUnAligned number bytes data stream that will transferred extract space numBytesPartial number unaligned bytes from previous Acells pduLen size APDU partialPayload[16] unaligned bytes from previous APDU AppData application specific data MPLS switched AAL-5 AppHdrData egress cell header.
7.10.3.2 Extract Space RxByte writes information about recirculated datagrams into extract space processing. data structure following format:
Byte Offset
vcCidIndex PayloadLength
rasType PduLength
Eom_offset NumUnalignedBytes PartialPayload PartialPayload PartialPayload PartialPayload AppData AppData
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
AppHdrData
typedef struct int8u rasType; int8u eom_offset; int16u vcCidIndex; int8u pduLength; int8u numUnAlignedBytes; int8u reserved[2]; int8u uui; int8u cpi; int16u payloadLength; int32u crc; int8u partialPayload[15]; int16u descData[4]; int32u appHdrData; RasExtractSpace;
rasType 0x00 AAL5 0x01 MPLS Switched AAL-5 0x00 this last cell 0x80 last cell vcCidIndex index pduLength size APDU numUnAligned number unaligned bytes extract space unused user-to-user indication from AAL5 trailer reserved payloadLength size reassembled AAL5 CRC-32 from AAL5 trailer partialPayload[15] unaligned bytes from current APDU AppData application specific data MPLS switched AAL-5 AppHdrData egress cell header
7.10.3.3 RasList RasList structure used track re-assembly state array 1024 structures with following format:
Byte Offset
BufHandle Offset
bufHandle handle buffer which cells being reassembled Offset offset reassembly buffer which next cell should placed
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.10.3.4 Descriptor information following data structure descriptor, which en-queued de-queued:
Byte Offset
bufHandle Length appData appData port_bufType
typedef struct BsBufHandle bufHandle; int16u length; int16u port_bufType; 15:5 port, bufType union int8u byte[8]; int16u hword[4]; int32u word[2]; AtmDescData atm; FrDescData frameRe; SegDescData seg; TdmDescData tdm; MlPppDescData mlPpp; MplsDescData mpls; appData; DescriptorMsg; bufHandle reassembly buffer handle length chunk length port_bufType input port buffer type next module appData Application specific data.
7.10.3.5 Ring Slots reassembly launches command into table. uses following slots purpose: Request Slot Response Slot
7.10.4
None
Issues/Enhancements
7.11 Classifier
CP10 implements Classifier component that provides classification quality service specified 2474,RFC 2475, 1633, 2211 2212) that will configured TMC. implemented DiffServ IntServ This component does SDP. uses single CPRC perform classification DiffServ IntServ ingress queues system. Classifier CPRC input queue every egress port. This component
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note uses multiple fields from TCP/UDP headers determine traffic category (i.e., flow packet) sends that will apply appropriate marking shaping strategy Currently, design supports IPv4 only.
7.11.1
Initialization
initialization mentioned section 7.1.1.
7.11.2
Host Configurations
Host responsible perform configurations shown figure configures following parameters map. Since total number channels supported Each channel consists traffic queues both DiffServ IntServ treatment. i.e. four queues channel will either used DiffServ IntServ based flow table. DiffServ will support queues, queue Best effort queue channel. Whereas IntServ will support guaranteed service traffic queues controlled load service traffic queues. These traffic queues configured flow table using field. total number traffic queues supported (for either DiffServ IntServ) Level2 scheduler (each having inputs) will configured each channel. will need level2 schedulers normal path. Discard path will also need scheduler. Total number level2 schedulers 2K+1 Each Level1 scheduler will consist inputs. total number incoming inputs will total number level1 schedulers 2K/1K level, mandatory have level0 scheduler hierarchy. Total number VOPs created will normal path discard path. VOPs created every T1/E1 interface. VOPs also created inter communication. related configuration steps given here. configurations other C-3e components given section 7.21.2. configuration steps starting from bottom hierarchy (i.e. from level scheduler traffic queues) described follows. Initializes using qsTmcInitialize Creates level0 scheduler with input legs using qsTmcSchedCreate Creates discard path follows: Creates level2 scheduler with input using qsTmcSchedCreate Creates discard queue using qsTmcTrafficQueueCreate associates with level2 scheduler created above. Creates discard path using qsTmcVopCreate() associates with first level0 scheduler. Creates parent buffer pool buffer pool associated with using qsTmcBufferPoolCreate(). These buffer pools will used traffic queues. Creates 2-level1 schedulers each having 1024 (1K) input legs. These schedulers will feed level0 scheduler. maximum number level1 schedulers (having inputs) supported Q-5.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Creates 2K-level2 schedulers each having input legs that will receive input descriptor from four traffic queues four scheduler queues. Each scheduler queue mapped with traffic queue. This mapping shown figure 3.0. DiffServ treatment, input descriptor originate from traffic queue traffic queue best effort traffic queue that will configured flow table. IntServ treatment originate from either guaranteed service traffic queues control load service queues configured flow table. These schedulers will feed level1 scheduler. number level2 schedulers supported 18K. following traffic parameters will configured each level2 scheduler each traffic flow. DiffServ treatment CBS: Committed Burst Size EBS; Excess Burst Size Increment; number tokens added into token buckets every tick Current token bucket size committed bursts Current token bucket size excess bursts CIR; Committed Information Rate LastUpdateTime; Last time when traffic seen this flow IntServ treatment (Guaranteed service parameters) Token Bucket Rate Token Bucket size Peak data rate Policed Unit Policed Unit Rate SlackTerm IntServ treatment (Controlled load service parameters) Token Bucket Rate Token Bucket size Peak data rate Policed Unit Policed Unit
Creates discard blocks using qsTmcDiscardCreate() associates these with discard queue created above step. These discard blocks follows: Discard block1 Type: Single token bucket (qsDiscTypeSingBucket) Discard parameters: 1b1Limit 1b1Increment Discard block2 Type: (qsDiscTypeRED). Discard parameters: probabilityMax
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Creates traffic queues that will pass traffic hierarchy associates these queues with buffer allocated above. also associates queues with discard blocks. channel will have traffic queues. number traffic queues supported 128K. different VOPs normal path have been created section 7.21.2. configures among these VOPs with each traffic paths. Enables configuration using qsTmcEnqueueEnable(). Communicates with indicate that configuration done.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
Level0 scheduler inputs)
Level1 schedulers (Each having inputs)
different VOPs (For each
Level2 schedulers
Discard queue
port) DiffServ queues queues -1BE queues IntServ Guaranteed load queues Controlled load queues
Token Bucket Discard Block
Egress
Discard Block
Classification
Ingress
queue
Figure configuration DiffServ IntServ
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.11.3 7.11.3.1 Initialization Classifier component does following things during initialization: Creates input output threads. Initializes flow table lookup. Communicates with indicate that enabled. Jumps ingress thread. 7.11.3.2 Ingress Thread packet descriptor de-queued from queue. Packets coming CPRC already have complete header. first bytes packet contain protocol headers. They transferred into DMEM buffer using bsBufferRead(). specific header fields that should used determine traffic category (that flow) packet specified Multi Field (MF) mask. They shown Figure
Figure DiffServ Multi field bitmask
header fields specified mask concatenated form 14-byte lookup key. exact match table flow table) maintained table, match these keys flow DiffServ PHB. Ingress performs following functions: Dequeues packet descriptor from queue. Gets port queue from incoming descriptor enqueued component. This queue denotes base traffic queue. component would have queue performing port lookup sent into classifier component. Forms 14-byte lookup based 5-tuple fields packet header. Launches flow table lookup.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Repeats above steps packets that present Queue.
7.11.3.3 Egress Thread After launching flow table lookup, context switches from ingress thread egress thread, which waits results flow table lookup. performs following functions. Waits flow table lookup completed. Gets traffic queue offset based lookup result. Flow table gives appropriate traffic queue offset corresponding treatment. treatment will configured DiffServ IntServ flow table. case DiffServ, will denote Whereas case IntServ will denote guaranteed service control load service. Determines destination traffic queue follows: Destination traffic queue queue traffic queue offset queue will determined from incoming descriptor Ingress function. determines appropriate code point, updates header (stored SDRAM) using bsBufferWrite() function adjusts checksum accordingly. Enqueues packet descriptor into destination traffic queue using qsEnqueueExt().
7.11.4
Functionality
classifier component en-queues packet into traffic queue apply various parameters (DiffServ IntServ). component performs port table lookup base traffic queue corresponding port sends this queue information classifier component treatment needed. classifier then determines destination traffic queue based offset flow table finally enqueues descriptor into traffic queue. provides marking/dropping, policing traffic shaping packet based configured traffic parameters. will enqueue conformant packets into queue VOPs. Non-conformant packets will either discarded using discard path marked priority. Traffic parameters scheduling described host configuration section 7.11.2.
7.11.5
Data Structures
7.11.5.1 Descriptor information descriptor will used given section 7.8.3.3.
7.11.6
Byte Offset
Flow Table
destIp srcIp
Each entry flow table following format:
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note destPort egressPort flowId srcPort maskBits queueOffset
protocol
description each field follows: DestIp: destination address packet SrcIp: Source address packet DestPort: TCP/UDP destination port packet SrcPort: TCP/UDP source port packet protocol: protocol (TCP/UDP) packet egressPort: output port maskBits: number significant bits phb: forwarding behavior apply. will denote DiffServ (AF/EF/BE) IntServ (Guaranteed service/Control load service). flowId: Flow that defines packet flow queueOffset: Traffic queue offset
7.11.7
Issues/Enhancements
Since total number channels supported 2048 egressPort field will require bits egressPort field flow table lookup size 1-byte because size limitation (max byte).
7.12 processing itching (CP11)
frame relay processing application distributed into (CP11 CP3). CP11 will perform switching will perform encapsulation. packets, which belong will queued CP11 decides whether packet needs MPLS, processing. packets that originate from MPLS module, which have pass through interface, need header insertion, which will carried CP3. CP11 used re-circulate frames destined transmission. main functions are: Launch lookup based DLCI value from descriptor. Based response, en-queue packets appropriate queue MPLS) needed. Perform switching properly modifying header with outgoing DLCI value. Properly en-queue modified buffer EgressQueue.
7.12.1
configured byte-level re-circulation. adds header frame. functions provided each component processors described below.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.12.1.1 RxByte RxByte processor fills extract space based descriptor information sent TxByte processor streams modified payload output thread (receive side) .The RxByte processor performs following functions part recirculation: Waits receive scope available. Receives bytes from TxByte processor. first bytes payload contain egress_queue. This written extract space. next bytes contain outgoing port information buffer type information. This will also written extract space. packet length indicated next bytes. This written extract space header ready indicated rxStatus register. Stream remaining payload DMEM. When data9 (i.e., ninth incoming payload) received switches scope. 7.12.1.2 TxByte TxByte processor modifies header based information given input thread (transmit side) transmits remaining payload data RxByte processor. TxByte processor performs following functions part recirculation: Reads payload from DMEM until Data9 observed. Reads outgoing DLCI value from merge space modify existing value packet with value. congestion control information fields header zero. Transmit egress_queue, port_buftype length packet before payload data that RxByte receives places extract space. Sends payload data RxByte. Switches scope waits next packet available.
7.12.2
manages re-circulation. that want transmit frames, enqueue their packets re-circulation that header modified frame before transmission. 7.12.2.1 Initialization initialization component initializes data structures registers used following activities done during initialization: Initializes buffer pools. Creates input output threads. Initializes table lookup slots.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.12.2.2 Input Thread Input thread services traffic which needs header modification frame queued here. This passes frame SDP. De-queues descriptor information. Launch lookup based DLCI value from descriptor. lookup fails, silently drop packet. While waiting response, process next packet from queue. Based egress_port (from lookup response), en-queue packet MPLS queue. Depending whether packet goes MPLS build descriptor with appropriate fields. MPLS fields that need filled descriptor are: port_buftype, LabelsSwap, LabelPush, EgressQueue, HopCount, InIfType_action only port_buftype filled descriptor. packet switched, fill merge space with outgoing DLCI value (from lookup response) header information. Initiates payload transfer from SDRAM DMEM switches context next thread. Loops beginning wait another descriptor. Output Thread
7.12.2.3
output thread handles incoming packets from RxByte processor. Waits header processing completion RxByte processor indicated L1Done rxStatus register. Allocates buffer initiates payload transfer from DMEM SDRAM. Creates descriptor with buffer handle, buffer length port_bufType information. Enqueue descriptor appropriate destination based egress_queue. Switches context next thread. Loops beginning wait another scope available.
7.12.3
Data Structures
merge space Extract space structures used processing explained below: 7.12.3.1 Merge space writes information needed encapsulation descriptor fields used CPRC, into merge space. TxByte processor does encapsulation sends descriptor fields RxByte. data structure following format:
Byte Offset
FrHeader port_bufType Length
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note EgressQueue explanations above-mentioned fields will follows FrHeader: outgoing DLCI value. EgressQueue: specifies final queue. port_buftype Outgoing interface information buffer type Length Length packet. Pad: unused. 7.12.3.2 Extract Space RxByte processor writes descriptor information into extract space processing. data structure following format:
Byte Offset EgressQueue port_buftype Length
explanations above-mentioned fields will follows EgressQueue: specifies final queue. port_buftype: Outgoing interface information buffer type Length: Length packet. Pad: unused.
7.12.3.3 Descriptor information module will fill descriptor information used recirculation module processing. format descriptor will follows:
Byte Offset
BufHandle Length PortBufType
FrHeader explanations above-mentioned fields will follows BufHandle: Handle buffer being re-circulated. Length: specifies length buffer. Port_bufType: bitmask defined follows: b15-5: port output port which this datagram transmitted. b4-0: bufType type buffer being re-circulated egress port type (could BT_IPV4, BT_MPLS_FR,BT_FR) FrHeader: specifies DLCI value congestion control Information.
7.12.3.4 Ring Slots uses these slots Request slot Response slots
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
7.12.4
Issues/Enhancements
present congestion control information header processed. bytes address format DLCI (10-bit) supported now. module Extended support three (16-bit DLCI) four bytes (23-bit DLCI) address format DLCI.
7.13 MPLS (CP12)
CP12 implements MPLS component application. This component performs MPLS lookup operation (MPLS actions performed label encapsulation label switching). MPLS operation done based MPLS entry information (labelSwap, labelPush, MPLS action, hopCount) maintained different tables. tables mentioned below maps input frame/packet type (PPP table which MPLS entry maintained.
Input frame /packet type table from which lookup launched Notes
MPLS Table (This defined section 7.18.8) table
MPLS
This table also used action (which needs additional label lookup based next label stack) case MPLS packet over Aand
Table IPv4 Routing table
This table handle MPLS packets
ingress
label MPLS packet maps VPI/VCI Acell DLCI frame. Hence, lookup response table table MPLS entry information.
7.13.1
configured byte level re-circulation. re-circulates packet remove PPP/FR header, sends descriptor information used CPRC perform MPLS operation. 7.13.1.1 TxByte TxByte processor, removes PPP/FR header, sends descriptor information RxByte performs MPLS operation.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note MPLS operation involves addition removal shim header fields (LabelSwap, LabelPush, BOS, ttl) packet, TxSDP appropriate place chosen perform this functionality. TxCPRC writes information about MPLS data needed MPLS operation descriptor information queued respective module based egress port type) into merge space. data structure defined section 7.13.3.1. TxByte configurable through control space.
detailed flow Transmit Byte processing described below: Wait Transmit scope from CPRC. Removes FR/PPP header(if any) based header length value from Transmit CPRC. Sends following descriptor information merge space RxByte, rxAlgorithm Port_bufType (15:5 egress port, egress bufType) Packet header (CellHeader DLCI egressQueue. MPLS Operation done based MPLS command, whose functionality described below: MPLS command value from merge space save same temporary registers. Check command. command POP, number labels removed. Remove shim header repeat removal header until count reaches number labels removed. Jump check SWAP_PUSH command. Check SWAP_PUSH command. command SWAP_PUSH, Perform PUSH operation followed SWAP. PUSH operation, Construct MPLS header using `labelPush` from merge space, with zero value stored value. Finally, Jump SWAP operation. Else, Jump check SWAP command. Check SWAP command. command SWAP, Send `labelSwap` from merge space, stored value. Save Jump check presence shim header(s). Else, Jump check PUSH_PUSH command. Check PUSH_PUSH command. command PUSH_PUSH, Perform, PUSH operation next PUSH jumping PUSH operation. Send `labelPush `from merge space, with zero value stored value else, Jump check PUSH command. Check PUSH command. command PUSH, Send label pushed from merge space, (set only packets received from IPv4 module) stored value. Jump check presence shim header(s). Else, Jump check presence shim header(s). Check presence shim header based saved during MPLS operation. set, (i.e. presence more shim header) Stream shim header until last shim header reached. Update from merge space shim header(s). Else, Jump check POP_IPv4 command.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note
Check POP_IPv4 command based value BT_MPLS_IPv4.If POP_IPv4, update checksum from merge space header else jump stream remaining payload. Stream payload until Data9 last byte. Sends packet byte with Merge9 set. Switches scope waits next packet.
7.13.1.2 RxByte RxByte processor, extracts descriptor information performs NULL Label encapsulation MPLS packet over
RxByte processor writes information about descriptor into extract space RxCPRC processing. data structure defined section 7.13.3.2. RxByte configurable through control space. detailed flow RxByte processing described below: Waits receive scope become available. Receives descriptor information from TxByte places extract space. RxAlgorithm MPLS_NULL_LABEL, label passed with NULL label (only MPLS packet over ATM/FR) Streams remaining bytes DMEM Switches scope waits another become available.
7.13.2
MPLS component uses threads perform task, namely, input thread output thread. initialization code starts threads. Each these described following sections. 7.13.2.1 Initialization MPLS component does following things during initialization: Initializes buffer pools. Allocate buffers receive path. There data scopes handling inbound packets. Allocate buffer each data scope setup registers receiving data. Allocate buffers transmit path, which never used. This used simplify logic freeing buffers input thread. Creates input output threads Initializes MPLS Table lookup launched from TxCPRC. Initializes both scopes giving ownership. Enable SDP. Jumps first thread.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note 7.13.2.2 Input Thread Input thread fills merge space with MPLS forwarding information MPLS operation descriptor fields passed RxCPRC further processing. merge space information obtained from MPLS entry maintained different tables. (Refer section 7.18.8) detailed flow Input thread processing described below: Wait descriptor present queue then de-queues descriptor filled following components: MPLS over Apackets. MPLS over packets. MPLS over packets. packets entering MPLS domain. Note: cases except packets operations, descriptor holds necessary information fill merge space. Read first bytes SDRAM buffer Label Stack. Adjust buffer offset pointing start Label stack. input port type. (A/FR/PPP/IPv4) from descriptor. input port type ATM/FR/IPv4, perform following functions: from incoming packet input port type ATM/FR, extracted from shim header extracted from header input port type Ipv4). Decrement value with descriptor field `hopCount' Save updated value port_buftype. MPLS action check command. command Label stack with more than MPLS label, then flag perform additional label lookup. other cases, save MPLS information (labelSwap, labelPush, cmds, ttl, port_bufType) copied merge space.
input port type command (which needs additional lookup) perform following. Launch lookup with MPLS label shim Header. Wait MPLS lookup complete lookup fails, drop packet. Save some merge space information (port_bufType, TTL) from lookup response. action, repeat MPLS Label lookup. number operations performed stored least significant bits cmds field merge space. addition, more than MPLS operation like SWAP, PUSH also stored cmds field. (Refer merge space structure more details) Based MPLS action, save remaining merge space information (cmds-MPLS command, labelSwap, labelPush).
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note egress-port type A/FR, fill egressQueue header information (Cell Header Aand DLCI FR). Fill txAlgorithm with egressBufType Fill rxAlgorithm with MPLS_NULL_LABEL MPLS packet destined A/FR interface. MPLS command `POP_IPv4_LOOKUP', form checksum adjusted value. Fill headerLen with negation packet header length. Waits transmit scope available from SDP. Fills merge space from saved merge space. Waits previous transfer complete. Begins transfer current buffer being processed. Switch context next thread. Loops beginning wait another descriptor.
7.13.2.3 Output Thread output thread handles sending descriptor appropriate modules based egress port type (A/FR /PPP/IPv4). detailed flow Output thread processing described below:
Waits scope become available from SDP. Fills descriptor using information from extract space. Waits payload transfer complete. Allocates buffer initiates payload transfer from DMEM SDRAM. Sends descriptor appropriate destination based egress port type. Switches context next thread. Loops beginning wait another scope available
7.13.3
Data Structures
7.13.3.1 Merge space writes information needed MPLS operation descriptor fields used CPRC, into merge space. TxByte processor does MPLS operation sends descriptor fields RxByte processor. data structure following format:
Byte Offset
headerLen
txAlgorithm Label Push Label Swap rxAlgorithm appData appData
cmds
port_bufType
Pad-- unused
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note TxAlgorithm holds egressbuftype based which TxByte identifies MPLS action `POP_IPV4_LOOKUP' necessary action carried (i.e. updation checksum header performed). cmds MPLS command used TxByte Processor MPLS operation. Input thread sets these values based MPLS actions (For, POP_IPv4_LOOKUP action command set). least significant bits used command store number labels removed. Possible enumerated values shown below:
typedef enum MPLS_CMD_NONE 0x00, MPLS_CMD_ADD 0x10, MPLS_CMD_PUSH_PUSH 0x08, MPLS_CMD_SWAP 0x20, MPLS_CMD_SWAP_PUSH 0x40, MPLS_CMD_POP 0x80 MplsCommands; -time live labelPush -label added. labeSwap Label swapped.
above fields used MPLS operation TxByte processor. headerLen Length header (for bytes removed. holds negative value header length.
descriptor fields sent RxByte processor mentioned below: rxAlgorithm NULL label sent MPLS packet over Aand this field 0x10 MPLS CPRC. port_bufType bitmask defined follows: b15-5: port output port which this datagram transmitted. b4-0: bufType type buffer being re-circulated (could BT_MPLS_PPP, BT_MPLS_ATM, BT_MPLS_FR, BT_MPLS_IPv4) appData application specific data defined below appData field meaning specific processing block which been enqueued. There several formats appData field. segmentation appData field Ahas format: specified Section 7.4.3.3 appData field following format:
Byte Offset
frHeader egressQueue
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note frHeader DLCI value egressQueue Queue egress interface -unused
7.13.3.2 Extract Space RxByte processor writes descriptor information into extract space processing. data structure following format:
Byte Offset
AppData AppData
port_bufType
unused port_bufType bitmask defined follows: b15-5: port output port which this datagram transmitted. b4-0: bufType type buffer being recirculated (could BT_MPLS_PPP, BT_MPLS_ATM, BT_MPLS_FR, BT_MPLS_IPv4) appData application specific data defined below
appData field meaning specific processing block which been enqueued. There several formats appData field. segmentation appData field Ahas format specified section 7.9.3.3 FrDescData appData field format: specified section 7.13.3.1 7.13.3.3 Descriptor information MPLS Descriptor filled following components. MPLS over Apackets. MPLS over packets. MPLS over packets. ingress packet.
Note: cases except packets operations, descriptor holds necessary information perform MPLS operation.
Byte Offset
labelSwap hopCount inIfType_action appHdrData vcIndex
labelPush egressQueue
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note labelPush Label added. labeSwap Label swapped. hopCount value decremented ttl. inIfType_action MPLS action inIfType enumerated values MPLS action provided Section 7.13.3.1. enumerated values input interface type shown below. typedef enum MPLS_PPP=0x10, MPLS_ATM=0x20, MPLS_FR=0x30, MPLS_IPv4=0x40 portType; egressQueue egress queue packet. appHdrData header information (Cell Header Aand DLCI FR). vcIndex ndex used AAL-5 SARs index their tables. -Unused.
7.13.3.4 Ring Slots MPLS uses these slots: MPLS request slot MPLS response slot
7.14 MLPPP
CP13 implements ML-PPP application. This component segments datagrams into fragments transport over ML-PPP bundles provides multiple classes service. component also reassembles ML-PPP fragments forwards them next processing block. This uses ML-PPP remainder table discussed section 7.18.2
7.14.1
configured byte re-circulation provides byte level processing fragments including header parsing generation. RxBit, RxSync, TxBit used. 7.14.1.1 RxByte RxByte processor receives ML-PPP fragments from TxByte processor handles them differently depending whether segmentation reassembly needed. reassembly direction, RxByte processor does following: Waits receives reassembly operation code byte puts extract space. Receives control information (port, index, fragType, length) puts extract space. fragments, also receives bufType puts extract space. Indicates header processing done.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note fragments, streams payload bytes DMEM, switches scope, waits next operation code. non-EOM fragments, streams `length' bytes payload DMEM. Streams remaining payload bytes ring message register. When data9 received, fills count remaining bytes ring message register initiate write command send remainder bytes ML-PPP remainder table. Switches scope waits next operation code.
segmentation direction, RxByte processor does following:
Waits receives segmentation operation code puts extract. Receives port number puts extract. Indicates header processing done. Receives ML-PPP encapsulated fragment. Writes payload DMEM. When data9 received, switches scope waits next operation code.
RxByte processor communicates with through extract space. Extract space described section 7.14.3.1. RxByte processor configurable through control space. 7.14.1.2 TxByte TxByte processor transmits ML-PPP fragments RxByte processor. reassembly direction, TxByte processor does following: Waits scope available Send reassembly operation code RxByte processor. Sends control information RxByte including port, index, fragType from merge space. Removes HDLC, PPP, ML-PPP encapsulation from fragment. fragments, parses reassembled protocol field maps buffer type. Calculates length fragment including non-SOM fragments, including discarded framing bytes. Sends length, necessary send bufType RxByte processor Sends remainder bytes from merge space RxByte processor. Streams payload from DMEM RxByte processor. Transmits data9 with dummy byte indicate packet. Switches scope waits scope available again. segmentation direction, TxByte processor does following: Waits scope available Sends segmentation operation code RxByte processor. Sends port RxByte processor. Sends HDLC/PPP/ML-PPP header from merge space RxByte processor. Reads payload from DMEM sends number bytes specified merge space RxByte processor.
More Information This Product, www.freescale.com
Page
Motorola Network Processors
Application Note Transmits data9 with dummy byte indicate packet Switches scope waits scope available again.
TxByte processor communicates with through merge space. Merge space described section 7.14.3.2. TxByte processor configurable through control space.
7.14.2
manages en-queuing de-queuing ML-PPP fragments datagrams. also maintains state information necessary segmentation reassembly. addition, schedules packets segmentation.
7.14.2.1 Initialization initialization component initializes data structures registers used Specifically, does following: Initializes buffer pools. Creates contexts input, output, scheduler threads. Initializes ring message registers used RxByte processor. Sets engin
Other recent searches
SPB-7780-1510G - SPB-7780-1510G SPB-7780-1510G Datasheet
SPB-7780B-1510G - SPB-7780B-1510G SPB-7780B-1510G Datasheet
SPB-7780A-1510G - SPB-7780A-1510G SPB-7780A-1510G Datasheet
SPB-7780L-1510G - SPB-7780L-1510G SPB-7780L-1510G Datasheet
SPB-7780BL-1510G - SPB-7780BL-1510G SPB-7780BL-1510G Datasheet
SPB-7780AL-1510G - SPB-7780AL-1510G SPB-7780AL-1510G Datasheet
MJ2955 - MJ2955 MJ2955 Datasheet
LT1991 - LT1991 LT1991 Datasheet
LH28F160BJHE-TTLZE - LH28F160BJHE-TTLZE LH28F160BJHE-TTLZE Datasheet
HOP2000 - HOP2000 HOP2000 Datasheet
B220A - B220A B220A Datasheet
B230A - B230A B230A Datasheet
B240A - B240A B240A Datasheet
B250A - B250A B250A Datasheet
B260A - B260A B260A Datasheet
AIM104-RELAY8 - AIM104-RELAY8 AIM104-RELAY8 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
