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Implementing GMII Interface
Generation Date Revision Product Relevant version Description Distribution Author
12/2/01 C-5, C-Ware Software Toolset CST2.0 Describes C-5's implementation GMII port Customer Bing Cheng
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INTRODUCTION
GMII stands Gigabit Media Independent Interface. standard interface specified IEEE 802.3. purpose this interface provide simple interconnection between that independent physical media types. Many commercial Gigabit Ethernet devices GMII means communicate device. GMII become most common MAC-to-PHY interface Gigabit Ethernet applications. implement Gigabit Ethernet functions internally connect external devices GMII. This document intended describe works with Ethernet device GMII.
This document targeted Previous revisions fully support GMII interface. It's assumed that reader should have adequate knowledge architecture C-5.
GMII FUNDAMENTALS
signals GMII interface their directions shown Figure below. Refer IEEE 802.3 document more details.
TXD(7:0) TX_EN TX_ER GTX_CLK
RXD(7:0) RX_ER RX_DV RX_CLK
(C-5)
Figure GMII Signals shown, there total pins required GMII interface. Below brief description functionality these signals: GTX_CLK provides timing reference transfer TX_EN, TX_ER TXD. It's supplied device, which this case C-5. frequency nominally MHz. RX_CLK timing reference transfer RX_DV, RX_ER signals. usually recovers this clock from receive data from physical medium provides MAC. This clock derived from local clock (e.g. GTX_CLK) physical medium attached. frequency also nominally MHz. C-PORT CORPORATION PROPRIETARY CONFIDENTIAL
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TX_EN (Transmit Enable) used indicate that data present GMII transmission. asserted synchronously with first octet preamble remains asserted duration entire data frame. TXD(7:0) (Transmit Data) data signals that used supply bytealigned data transmission. TX_ER (Transmit Coding Error) used tell transmit illegal symbol code physical medium. RX_DV (Receive Data Valid) driven indicate presenting recovered decoded data RXD(7:0). It's asserted during entire data frame, provide envelope signal valid data frame including Preambles, Start Frame Delimiter (SFD) Frame Check Sequence (FCS) bytes. uses this signal delineate frame. RXD(7:0) (Receive Data) data signals present byte-aligned receive data MAC. Data byte these signals valid only when RX_DV asserted RX_ER de-asserted. RX_ER (Receive Error) used indicate detection illegal symbol code during reception frame (when RX_DV asserted), discard frame. It's used signal Carrier Extension when RX_DV de-asserted. (Carrier Sense) signal driven PHY. While operating half duplex mode, will assert when either transmit receive medium non-idle de-assert when both transmit receive media idle. While operating full duplex mode, behavior specified standard, hence ignored MAC. (Collision Detected) asserted upon detection collision medium when it's operating half duplex mode. While operating full duplex mode, behavior specified standard, hence ignored MAC.
Permissible code combinations TXD(7:0), TX_EN TX_ER defined follows.
TX_EN TX_ER TXD(7:0) 0x00 through 0xFF 0x00 through 0x0E 0x0F 0x10 through 0x1E 0x1F 0x20 through 0xFF 0x00 through 0xFF 0x00 through 0xFF Description Normal inter-frame Reserved Carrier Extend Reserved Carrier Extend Error Reserved Normal data transmission Transmit error propagation
Table
Permissible Code Combination
Permissible code combinations RXD(7:0), RX_DV RX_ER defined follows. C-PORT CORPORATION PROPRIETARY CONFIDENTIAL
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RX_DV
RX_ER
RXD(7:0) 0x00 through 0xFF 0x00 0x01 through 0x0D 0X0E 0x0F 0x10 through 0x1E 0x1F 0x20 through 0xFF 0x00 through 0xFF 0x00 through 0xFF
Description Normal inter-frame Normal inter-frame Reserved False Carrier indication Carrier Extend Reserved Carrier Extend Error Reserved Normal data reception Data reception error
Table
Permissible Code Combinations
There other signals defined management purpose, which shown Figure These signals MDIO. They provide means device access internal management registers device, that device configure well check status port. IEEE standard defines serial protocol applied these signals, where MDIO carries serial data provides clock reference serial data. Multiple devices share same management interface, each them needs assigned unique address.
GMII IMPLEMENTATION
Since data transfer rate GMII Gb/s each direction, need aggregation mode share load processing data stream this speed. Running aggregation mode, interface pins cluster combined used together implement 8-bit interface required GMII. more information aggregation mode, refer Network Processor Architecture Guide. There total pins within cluster, each cluster enough signals implement GMII interface. SDPs within cluster capable handling throughput full duplex Gigabit Ethernet port, function fully implemented cluster. However, CPRCs have enough cycles process both directions traffic concurrently, hence, wire speed operation cannot achieved. Another concern that IMEM space within cluster enough hold both transmit receive code. C-5e, with faster processors, improved architecture larger IMEM will likely solve these problems. current C-5, ensure support GMII interface line rate Gb/s full duplex), Gigabit Ethernet reference design uses clusters implement GMII interface. This application, where cluster handles transmission Gigabit Ethernet port other processes reception port, supports Layer Bridging Layer forwarding functions Gigabit Ethernet port. also have another reference application that C-PORT CORPORATION PROPRIETARY CONFIDENTIAL
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implements single cluster GMII interfaces. This application supports forwarding MPLS switching Gigabit Ethernet ports, ports line rate C-5.
Connections
implement GMII interface, pins configured operate LVTTL levels. GMII signals divided into groups, Group Group. Group includes GTX_CLK, TXD(7:0), TX_EN, TX_ER, COL. other signals, RX_CLK, RXD(7:0), RX_DV RX_ER Group. Whether cluster clusters used GMII interface, Group signals must connected lower-numbered cluster, Group signals must higher-numbered cluster. clusters used, they four clusters C-5.
Shown below connection GMII signals pins.
Name CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPm+2_0 CPm+2_1 CPm+2_2 CPm+2_3 CPm+2_4 CPm+2_5 CPm+2_6 CPm+3_0 GMII Signal Name GTX_CLK Used TXD(0) TXD(1) TXD(2) TXD(3) TX_EN Connect TXD(4) TXD(5) TXD(6) TXD(7) TX_ER Connect RX_CLK RXD(0) RXD(1) RXD(2) RXD(3) RX_DV Connect Signal Name Used TXCLK TXD(0) TXD(1) TXD(2) TXD(3) TX_EN Connect Used Used Used Used TX_ER Connect RX_CLK RXD(0) RXD(1) RXD(2) RXD(3) RX_DV Connect Direction
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CPm+3_1 CPm+3_2 CPm+3_3 CPm+3_4 CPm+3_5 CPm+3_6
RXD(4) RXD(5) RXD(6) RXD(7) RX_ER
Used Used Used Used RX_ER
Note: column above table single cluster used, used,
Table
GMII
Mode Register Configuration
order configure operate GMII MAC, following registers need SDP_Mode3, SDP_Mode4, SDP_Mode5 PIN_Mode. bits these registers need properly GMII interface function. There function that used this. function psEthernetportConfigure(), which part Protocol Services CPI. application software just need call this function each with proper parameters, registers mentioned above will configured appropriately. parameters that need specified include: processor configure, what type used (GMII, MII, RMII), whether need configure side, side both Therefore, software doesn't need deal with what value need programmed onto each register. Refer C-Ware User Guide details this function. settings these registers given reference Appendix section.
Auto-Negotiation Implementation
Most GMII devices support Auto-Negotiation, functioning device needs adjust operation according Auto-Negotiation results. communication results done management interface. 3.3.1 Management
serial interface port that implement MDIO management protocol specified standard. This interface used access management registers device. There 16-bit registers implemented GMII device. Some them specified required IEEE standard, some specific PHY. serial interface, write these registers configure well read from these registers check status gather statistics network port. speed serial interface programmable. also configured with without Preamble suppression, which specified IEEE standard. adjust C-PORT CORPORATION PROPRIETARY CONFIDENTIAL
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implementation some device market, provides option serial interface with turn around bits MDIO read operation. Note that standard requires turn around bits. these options configured through Serial Configuration Register. program, user simply call ksSerialBusConfigMdio() function these options. functions, ksMdioRead() ksMdioWrite() used access registers. some cases, it's desirable configure physical port operate certain mode, some devices need initialized before use. configure writing management registers initialization time command start Auto-Negotiation process. Most GMII devices programmed generate hardware interrupts connects upon changes certain status. interrupt input pin, XPUHOT that connect interrupt. Changes status will interrupt that program take appropriate measures. course, alternative find status changes polling. that case, program will implement timed loop that polls internal management registers periodically check status changes. serial port only accessible host processor (via address mapping bus). 3.3.2 Adjust Auto-Negotiation Results
Auto-Negotiation process where device negotiates with link partner reach most optimum operation mode between them. important options negotiate are: what speed data transported line; whether line full duplex half duplex; whether flow control (pause frames) applied link. Upon detection physical link, device automatically performs this process. result Auto-Negotiation stored management registers. access management registers check Auto-Negotiation result. only internal processor that access this serial port. reference application handles Auto-Negotiation that will read registers. thing changes operation mode physical interface, will send control message corresponding will make adjustment adapt operation mode. This adjustment simple setting control register complicated reloading different piece micro-code SDPs. 3.3.3 Switching interface
When device determines during Auto-Negotiation process that needs Mb/s speed, will switch type interface. also specified IEEE802.3 standard. differences between GMII data buses 4-bit wide clock output from device (see Table details). adjust these differences, mode registers need reprogrammed. Again, done calling function, psEthernetportConfigure() program. settings these registers when interface operates type given reference Appendix section.
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Moreover, CPRC needs load different microcode SDP. difference microcode TxBit RxBit processor code where data width differentiated.
Clock Signal Timing
GMII device requires clock timing reference signals, provides this clock GTX_CLK (CPn_0, where 12). clock input pin, CCLK6, which take reference clock. This clock source supplied each cluster provide individual transmit reference clock each GMII interface. side, expects provide clock reference RXD, RX_ER RX_DV signals. This clock signal driven RCLK (CPn+2_1, where 12). used this clock latch other input signals.
input output signal timing relative their reference clocks shown below.
GTX_CLK
TXD/TX_ER/ RX_EN
RCLK
RXD/RX_ER/ RX_DV
Figure GMII Signal Timing
Symbol Parameter Output delay Input setup time Input hold time Unit
Table
GMII Signal Timing Parameters
Implementation-specific Issues
Since function implemented microcode running SDPs, status control pins such RX_DV, RX_ER, CRC, COL, TX_EN TX_ER need accessed C-PORT CORPORATION PROPRIETARY CONFIDENTIAL
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controlled RxBit TxBit processors. table below outlines mapping these pins internal processor signals with mode register settings GMII interface.
Processor Signal RxBit PhyStatus0 PhyStatus1 TxBit PhyControl0 PhyControl1 TxBit PhyStatus0 PhyStatus1
GMII RX_DV RX_ER TX_EN TX_ER
Table
Processor Signal Mapping
clusters operatein aggregation mode GMII. this mode, RxBit processors cluster running four copies same piece code simultaneously. They process entire data stream. They delineate each data frame being received send stream RxByte processor. Therefore, RxByte processors cluster every frame from data stream. However, there hardware token being passed among them round robin fashion. Only processor token will process data frame that's currently being received send stream payload memory. Those don't have token just discard frame. After receiving entire frame, this RxByte processor releases token, that next RxByte processor will have token process next frame. That way, each RxByte processor only receives every frame. delineate data frames, every RxBit processor monitorsthe PhyStatus0 signal that represents RX_DV valid data. logic combination RX_DV*(~RX_ER) brought data Small FIFO, processor uses examine data check error every data byte received. This ensure data received examined fast enough wire speed operation GMII interface. RxBit processor also uses PhyStatus1 that represents RX_ER confirm error data within valid frame. direction, only TxBit processor operating. takes data frame from TxByte processors sends GMII interface with proper preambles delimiters. There hardware token being passed among TxByte processors round robin fashion. TxBit processor only take data from large FIFO TxByte processor currently owns token. Therefore, transmits frame from each TxByte processor round robin fashion. When there data frame transmitted, TxBit processor will generate IDLE patterns, also ensures minimum inserted between frames. Since TX_EN mapped PhyControl0 signal, when TxBit processor transmits frame, asserts PhyControl0 that TX_EN driven high duration frame. every byte sends out, choose assert de-assert TX_EN. PhyControl1 signal, which maps TX_ER, controlled same way, TxBit processor assert TX_ER data byte needs. COL, which mapped PhyStatus0 PhyStatus1 respectively, also examined TxBit processor. They only need considered when interface half duplex mode. Currently GMII microcode provided C-Port does support half duplex. C-PORT CORPORATION PROPRIETARY CONFIDENTIAL
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Because flexibility microcode programming, GMII function implemented different ways. current GMII microcode shipped with following characteristics: Carrier Extend Carrier Extend Error code never generated. TX_ER signal never asserted, will command send illegal symbols line purpose. will receive data only when RX_DV asserted. Therefore, False Carrier Indication, Carrier Extend Carrier Extend Error conditions ignored microcode. These errors counted. during reception normal packet (RX_DV asserted), RX_ER high clock cycle, packet will discarded. packet counted miss-alignment error now. code changed report this error more appropriate type. Half duplex operation 1000 10/100 Mbps supported. Both signals ignored microcode. have plans supporting half duplex this point time. user interested that, please consult with C-Port. There avoid underrun: using WaterMark feature, using byte processor processor handshaking mechanism. application program will Large FIFO Watermark value SDP_Mode4 Register. When number bytes sent Large FIFO exceeds this water mark value, TxBit processor will start transmitting data Large FIFO. when TxByte processor loads Large FIFO with enough data bytes, will TxByteToBit flag tell TxBit processor start sending data. Both solutions work ensure data frame will sent GMII continuously. Mechanism currently used microcode provided CPort.
Obviously, microcode modified easily more features change implementation. user should aware that change microcode alter behavior code, hence IEEE standard compliance will guaranteed. Note that microcode C-Port provides will tested InterOperability University Hampshire (test results provided upon request).
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APPENDIX
Shown below settings these registers cluster when this cluster used implement full duplex Gigabit Ethernet port (one GMII interface), where
Number CPn+0 Register Name SDP_Mode3 SDP_Mode4 SDP_Mode5 Setting GMII 0x00931941 0x00000000 0x10801940 0x005e407d 0x00931941 0x00000000 0x00801940 0x005e407c 0x00931941 0x00000000 0x00801940 0x001e4000 0x00931941 0x00000000 0x00801940 0x001e4000 Setting 0x00931141 0x00000000 0x10801140 0x005dc07d 0x00931141 0x00000000 0x00801140 0x005dc07c 0x00931141 0x00000000 0x00801140 0x001dc000 0x00931141 0x00000000 0x00801140 0x001dc000 enable bits RxSDP yet. Large FIFO Watermark used. TxBit processor enabled. enable bits RxSDP yet. Only Large FIFO Watermark bits set. TxBit processor enabled. enable bits RxSDP yet. Large FIFO Watermark used. TxBit processor enabled. Notes enable bits RxSDP yet. Large FIFO Watermark used. TxBit processor enabled base
PIN_Mode CPn+1 SDP_Mode3 SDP_Mode4 SDP_Mode5 PIN_Mode CPn+2 SDP_Mode3 SDP_Mode4 SDP_Mode5 PIN_Mode CPn+3 SDP_Mode3 SDP_Mode4 SDP_Mode5 PIN_Mode
Table
Register Settings Single Cluster Implementation
When clusters used implement Gigabit Ethernet port, setting clusters shown following table, where Here cluster implements cluster implements
Number CPn+0 Register Name SDP_Mode3 Setting GMII 0x00931941 Setting 0x00931141 Notes enable bits RxSDP yet.
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SDP_Mode4 SDP_Mode5 PIN_Mode CPn+1 SDP_Mode3 SDP_Mode4 SDP_Mode5 PIN_Mode CPn+2 SDP_Mode3 SDP_Mode4 SDP_Mode5 PIN_Mode CPn+3 SDP_Mode3 SDP_Mode4 SDP_Mode5 PIN_Mode CPm+0 SDP_Mode3 SDP_Mode4 SDP_Mode5 PIN_Mode CPm+1 SDP_Mode3 SDP_Mode4 SDP_Mode5 PIN_Mode CPm+2 SDP_Mode3 SDP_Mode4 SDP_Mode5 PIN_Mode CPm+3 SDP_Mode3 SDP_Mode4 SDP_Mode5
0x005e4000 0x00931941 0x005e4000 0x00931941 0x001e4000 0x00931941 0x001e4000 0x00000000 0x00000000 0x10801940 0x00801940 0x00000000 0x00000000 0x00801940 0x0056407c 0x00000000 0x00000000 0x00801940 0x00064000 0x00000000 0x00000000 0x00801940
0x005c0000 0x00931141 0x005c0000 0x00931141 0x001c0000 0x00931141 0x001c0000 0x00000000 0x00000000 0x10801140 0x0055c07d 0x00000000 0x00000000 0x00801140 0x0055c07c 0x00000000 0x00000000 0x00801140 0x0015c000 0x00000000 0x00000000 0x00801140
TxSDP used. TxSDP used.
enable bits RxSDP yet. TxSDP used. TxSDP used.
enable bits RxSDP yet. TxSDP used. TxSDP used.
enable bits RxSDP yet. TxSDP used. TxSDP used.
Turn processors RxSDP. Large FIFO Watermark used. TxBit processor enabled base
Turn processors RxSDP. Large FIFO Watermark used. TxBit processor enabled.
Turn processors RxSDP. Large FIFO Watermark used. TxBit processor enabled.
Turn processors RxSDP. Large FIFO Watermark used. TxBit processor enabled.
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PIN_Mode
0x00064000
0x0015c000
Table
Register Settings Dual Cluster Implementation
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