128K Super Power Voltage Full CMOS Static CMOS SRAM Revision
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K6F1008V2M, K6F1008S2M, K6F1008R2M Family
128K Super Power Voltage Full CMOS Static
CMOS SRAM
Revision History
Revision History
Initial draft Revise Erase 100ns from KM68FS1000 Family 150ns KM68FS1000 Family 32-sTSOP1 package high power version ISB1=5.0µA(Max) Change VDR(Min) 1.5V Finalize Concept change high power version power version ISB1=5.0µA(Max) Change super power version with special handling ISB1=1.0µA(Max) Icc1(Read) decrease Revise Change datasheet format Remove reverse type package from product Remove reserved speed bin(100ns) Revise type packaged product. Improved ICC2
Draft Date
March 1996 July 1996
Remark
Advance Preliminary
December 1996
Final
February 1998
Final
July 1998
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
CMOS SRAM
128K Super Power Voltage Full CMOS Static
FEATURES
Process Technology: Full CMOS Organization: 128K Power Supply Voltage K6F1008V2M Family: 3.0V 3.6V K6F1008S2M Family: 2.3V 3.3V K6F1008R2M Family: 1.8V 2.7V Data Retention Voltage: 1.5V(Min) Three state output Compatible Package Type: 32-SOP-525, 32-TSOP1-0820F, 32-TSOP1-0813.4F, 48-CSP
GENERAL DESCRIPTION
K6F1008V2M, K6F1008S2M K6F1008R2M families fabricated SAMSUNGs advanced Full CMOS process technology. families support various operating temperature range have various package types user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range K6F1008V2M-C K6F1008S2M-C K6F1008R2M-C K6F1008V2M-I K6F1008S2M-I K6F1008R2M-I Industrial(-40~85°C) Commercial(0~70°C) 3.0~3.6V 2.3~3.3V 1.8~2.7V 3.0~3.6V 2.3~3.3V 1.8~2.7V Speed(ns) Standby (ISB1, Max) Operating (ICC2, Max) 40mA 35mA 30mA 5µA2) 15mA 40mA 35mA 30mA 15mA 32-SOP 32-TSOP1 Forward 32-sTSOP1 Forward 48-CSP Type
701)/85@VCC=3.3±0.3V /85@VCC=3.0±0.3V 1201)/150@VCC=2.5±0.2V @VCC=2.0±0.2V 701)/85@VCC=3.3±0.3V /85/100@VCC=3.0±0.3V 1201)/150@VCC=2.5±0.2V @VCC=2.0±0.2V
parameter measured with 30pF test load. super power version with special handling.
DESCRIPTION
I/O1 I/O2 I/O3 I/O8 I/O7 I/O6 I/O5 I/O4 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
32-TSOP 32-sTSOP Type1-Forward
32-SOP
select
Memory array 1024 rows columns
I/O5 I/O6 I/O7 I/O8
I/O1
I/O1
I/O2
I/O8
Data cont Data cont
Circuit Column select
I/O3 I/O4
48-CSP VIEW
Control logic
Name
Function
Name
Function Output Enable Input Write Enable Input
Name
Function Power Ground
Name
Function
CS1,CS2 Chip Select Input N.C. Connection
1~I/O8 Data Inputs/Outputs A0~A16 Address Inputs
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
PRODUCT LIST
Commercial Temperature Products(0~70°C) Part Name K6F1008V2M-GC70 K6F1008V2M-GC85 K6F1008V2M-TC70 K6F1008V2M-TC85 K6F1008S2M-GC12 K6F1008S2M-GC15 K6F1008S2M-TC12 K6F1008S2M-TC15 K6F1008S2M-YC12 K6F1008S2M-YC15 Function 32-SOP, 70ns, 3.3V 32-SOP, 85ns, 3.3V 32-TSOP1 70ns, 3.3V 32-TSOP1 85ns, 3.3V 32-SOP, 120/70ns, 2.5/3.0V 32-SOP, 150/85ns, 2.5/3.0V 32-TSOP1 120/70ns, 2.5/3.0V 32-TSOP1 150/85ns, 2.5/3.0V 32-sTSOP1 120/70ns, 2.5/3.0V 32-sTSOP1 150/85ns, 2.5/3.0V
CMOS SRAM
Industrial Temperature Products(-40~85°C) Part Name K6F1008V2M-GI70 K6F1008V2M-GI85 K6F1008V2M-TI70 K6F1008V2M-TI85 K6F1008S2M-GI12 K6F1008S2M-GI15 K6F1008S2M-TI12 K6F1008S2M-TI15 K6F1008S2M-YI12 K6F1008S2M-YI15 K6F1008S2M-ZI15 K6F1008R2M-GI30 K6F1008R2M-TI30 K6F1008R2M-YI30 K6F1008R2M-ZI30 Function 32-SOP, 70ns, 3.3V 32-SOP, 85ns, 3.3V 32-TSOP1 70ns, 3.3V 32-TSOP1 85ns, 3.3V 32-SOP, 120/70ns, 2.5/3.0V 32-SOP, 150/85ns, 2.5/3.0V 32-TSOP1 120/70ns, 2.5/3.0V 32-TSOP1 150/85ns, 2.5/3.0V 32-sTSOP1 120/70ns, 2.5/3.0V 32-sTSOP1 150/85ns, 2.5/3.0V 48-CSP, 150/100ns, 2.5/3.0V 32-SOP, 300ns, 2.0/2.5V 32-TSOP1 300ns, 2.0/2.5V 32-sTSOP1 300ns, 2.0/2.5V 48-CSP, 300ns, 2.0/2.5V
K6F1008R2M-GC30 K6F1008R2M-TC30 K6F1008R2M-YC30
32-SOP, 300ns, 2.0/2.5V 32-TSOP1 300ns, 2.0/2.5V 32-sTSOP1 300ns, 2.0/2.5V
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout
Mode Deselected Deselected Output Disabled Read Write
Power Standby Standby Active Active Active
means dont care. (Must high states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Soldering temperature time Symbol VIN,VOUT TSTG TSOLDER 260°C, 5sec (Lead Only) Ratings -0.2 3.6V2) -0.2 4.0V
Unit
Remark
K6F1008V2M-C, K6F1008S2M-C, K6F1008R2M-C K6F1008V2M-I, K6F1008S2M-I, K6F1008R2M-I
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability. VIN/VOUT=-0.2 3.9V K6F1008V2M Family. Maximum VCC=-0.2 4.6V K6F1008V2M Family.
Revision July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
RECOMMENDED OPERATING CONDITIONS1)
Item Symbol Product
K6F1008V2M Family
CMOS SRAM
Vcc=3.3±0.3V Vcc=3.0±0.3V Vcc=2.5±0.2V -0.23)
2.5/3.0 2.0/2.5
Unit
Supply voltage
K6F1008S2M Family K6F1008R2M Family
Ground
Family
K6F1008V2M Family K6F1008S2M Family
Input high voltage
Vcc+0.22)
K6F1008R2M Family
Vcc=2.5±0.2V Vcc=2.0±0.2V
Input voltage
Family
Note Commercial Product 70°C, unless otherwise specified Industrial Product TA=-40 85°C, unless otherwise specified Overshoot 1.0V case pulse width 20ns Undershoot -1.0V case pulse width 20ns Overshoot undershoot sampled, 100% tested.
CAPACITANCE (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ICC1 Average operating current ICC2
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL
Test Conditions VIN=Vss 1=VIH CS2=VIL OE=VIH WE=VIL, VIO=Vss IIO=0mA, 1=VIL, CS2=VIH, VIN=VIL VIH, Read
Cycle time=1µs, 100% duty, IIO=0mA, CS10.2V, CS2VCC-0.2V, VIN0.2V VINVCC-0.2V
Read Write
351)
Unit
Vcc=3.3V@70ns Vcc=2.7V@120ns Vcc=2.2V@300ns 2.1mA Vcc=3.0/3.3V
Output voltage
0.5mA Vcc=2.5V 0.33mA Vcc=2.0V -1.0mA Vcc=3.0/3.3V
Output high voltage
-0.5mA Vcc=2.5V -0.44mA Vcc=2.0V
Standby Current(TTL) Standby Current(CMOS)
ISB1
1=VIH CS2=VIL, Other inputs=VIL
CS1Vcc-0.2V, CS2Vcc-0.2V 20.2V, Other inputs=0~Vcc
1.K6F1008V2M Family 40mA Super power product with special handling.
Revision July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
OPERATING CONDITIONS
TEST CONDITIONS (Test Load Test Input/Output Reference)
Input pulse level 2.2V Vcc=3.3V, 3.0V, 2.5V 1.8V Vcc=2.0V Input rising falling time Input output reference voltage 1.5V Vcc=3.3V, 3.0V 1.1V Vcc=2.5V 0.9V Vcc=2.0V Output load (See right) :CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance 1=3070, =3150 V=2.8V VCC=3.0/3.3V 2.3V VCC=2.5V 1.8V VCC=2.0V
CHARACTERISTICS(Commercial product :TA=0 70°C, Industrial product TA=-40 85°C
K6F1008V2M Family Vcc=3.0~3.6V, K6F1008S2M Family Vcc=2.3~3.3V, K6F1008R2M Family Vcc=1.8~2.7V)
Speed Bins Parameter List Symbol 70ns 85ns 100ns 120ns 150ns 300ns Units
Read cycle time Address access time Chip select output Output enable valid output Read Chip select low-Z output Output enable low-Z output Chip disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write Write pulse width Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tCO1, tCO2 tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tWHZ
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V
Unit
Vcc=3.0V, CS1Vcc-0.2V data retention waveform
CS1Vcc-0.2V, 2Vcc-0.2V(CS1 controlled) CS20.2V(CS2 controlled) Super power product with special handling.
Revision July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
Address Data Previous Data Valid
CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than (Min.) both given device from device device interconnection.
Revision July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
TIMING WAVEFORM WRITE CYCLE(2) (CS1 Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
TIMING WAVEFORM WRITE CYCLE(3) (CS1 Controlled)
Address tAS(3) tWP(2) tWP(1) Data Data Valid tCW(2) tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap high write begins latest transition among goes low, going high going low: write earliest transition among going high, going going high, measured from beginning write write. measured from going going high write. measured from address valid beginning write. measured from write address change. WR(1) applied case write ends going high tWR(2) applied case write ends going low.
DATA RETENTION WAVE FORM
controlled
3.0/2.7/2.3/1.8V tSDR Data Retention Mode tRDR
2.2V CS1VCC-0.2V
controlled
3.0/2.7/2.3/1.8V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
PACKAGE DIMENSIONS
PLASTIC SMALL OUTLINE PACKAGE (525mil)
CMOS SRAM
Units: millimeter(inch)
0~8°
14.12±0.30 0.556±0.012
11.43±0.20 0.450±0.008
20.87 0.822 20.47±0.20 0.806±0.008
2.74±0.20 0.108±0.008 3.00 0.118
13.34 0.525
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.80±0.20 0.031±0.008
0.10 0.004
+0.100 -0.050 +0.004
0.71 0.028
0.41
0.016 -0.002
1.27 0.050
0.05 0.002
Revision July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (0820F)
CMOS SRAM
Units: millimeter(inch)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.00±0.20 0.787±0.008 8.40 0.331 8.00 0.315 0.25 0.010
0.50 0.0197
1.00±0.10 0.039±0.004 1.20 0.047
+0.10 -0.05 0.006+0.004 -0.002
0.05 0.002
0.25 0.010
18.40±0.10 0.724±0.004
0.15
0~8°
0.45 ~0.75 0.018 ~0.030
0.50 0.020
THIN SMALL OUTLINE PACKAGE TYPE (0813.4F)
0.10 0.004
0.20 0.008
+0.10 -0.05 +0.004 -0.002
13.40 ±0.20 0.528 ±0.008
8.40 0.331 8.00 0.315
0.25 0.010
0.50 0.0197
1.00 ±0.10 0.039 ±0.004
0.25 0.010
11.80 ±0.10 0.465 ±0.004
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.05 0.002 1.20 0.047
0~8°
0.45~0.75 0.018~0.030
0.50 0.020
Revision July 1998
0.10 0.004
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (0820F)
View Ball Bottom View
CMOS SRAM
Units: millimeter(inch)
Ball
SRAM
Elastomer Side View Detail 0.25/Typ. Detail
0.55/Typ.
0.32/Typ.
Elastomer 0.3/Typ. Notes. Bump counts 48(8row 6column) Bump pitch (x,y)=(0.75 0.75)(typ.) tolerence +/-0.050 unless otherwise specified. Typical coplanarity: 0.08(Max) Revision July 1998
5.90 7.90 0.30
0.75 6.00 3.75 8.00 5.25 0.35 0.80 0.55 0.25
6.10 8.10 0.40 0.81 0.08
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