128Kx8 Super Power Voltage CMOS Static CMOS SRAM Revision Hi

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128Kx8 Super Power Voltage CMOS Static CMOS SRAM Revision Hi

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K6F1008U2A Family
128Kx8 Super Power Voltage CMOS Static
CMOS SRAM
Revision History
Revision
History
Design target Revise Finalize Change 1.5V Change test condition VCC=1.2 1.5V
Draft Data
November 1998 January 1999 February 1999
Remark
Advance Preliminary Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves right change specifications products. SAMSUNG Electronics will answer your questions. have questions, please contact SAMSUNG branch offices.
Revision February 1999
K6F1008U2A Family
CMOS SRAM
128Kx8 Super Power Voltage CMOS Static
FEATURES
GENERAL DESCRIPTION
K6F1008U2A families fabricated SAMSUNGs advanced full CMOS process technology. families support industrial temperature range have various package types user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
Process Technology: Full CMOS Organization: 128K Power Supply Voltage: 2.7~3.3V Data Retention Voltage: 1.5V(Min) Three state output status Compatible Package Type: 32-TSOP1-0813.4F 48-FBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed Standby (ISB1, Typ.) 0.5µA Operating (ICC1, Max) Type
K6F1008U2A-I
Industrial(-40~85°C)
2.7~3.3V
70/100ns
32-sTSOP1-F 48-FBGA
DESCRIPTION
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
32-sTSOP Type1-Forward
select
Memory array 1024 rows columns
I/O5 I/O6 I/O7 I/O8
I/O1 I/O2
I/O1
I/O3 I/O4
I/O8
Data cont
Circuit Column select
Data cont
48-CSP VIEW Name Function Name Function
CS1,CS Chip Select Inputs A0~A16 Output Enable Input Write Enable Input Address Inputs
I/O1~I/O8 Data Inputs/Outputs N.C. Power Ground Connection
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision February 1999
K6F1008U2A Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F1008U2A-YI70 K6F1008U2A-YI10 K6F1008U2A-FI70 K6F1008U2A-FI10 Function 32-sTSOP1 70ns, 3.0V 32-sTSOP1 100ns, 3.0V
CMOS SRAM
48-FBGA with ball, 70ns, 3.0V 48-FBGA with ball, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout
Mode Deselected Deselected Output Disabled Read Write
Power Standby Standby Active Active Active
means dont care (Must high states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT TSTG Ratings -0.2 3.6V -0.2 4.0V Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision February 1999
K6F1008U2A Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage
Note TA=-40 85°C, otherwise specified Overshoot: Vcc+2.0V case pulse width 20ns. Undershoot: -2.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
CMOS SRAM
Symbol -0.2
Vcc+0.22)
Unit
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Average operating current Output voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) Symbol ICC1 ICC2 ISB1 VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL, VIO=Vss IIO=0mA, CS1=VIL, 2=VIH, VIN=VIH
Cycle time=1µs, 100%duty, IO=0mA, 0.2V, Vcc-0.2V, IN0.2V Cycle time=Min, 100% duty, IIO=0mA, =VIL, CS2=VIH, VIN=VIH
Test Conditions
Unit
IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other inputs=VIH CS1Vcc-0.2V, CS2Vcc-0.2V CS20.2V, Other inputs=0~Vcc
Super power product=1µA with special handling.
Revision February 1999
K6F1008U2A Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Test Input/Output Reference)
Input pulse level: 2.2V Input rising falling time: Input output reference voltage: 1.5V Output load (See right): 100pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance R1=3070, =3150 V=2.8V
CHARACTERISTICS (Vcc=2.7~3.3V, TA=-40 85°C)
Speed Bins Parameter List Symbol Read cycle time Address access time Chip select output Output enable valid output Read Chip select low-Z output Output enable low-Z output Chip disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Write Write pulse width Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tCO1, tCO2 tOLZ tOHZ tWHZ 70ns 100ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR CS1Vcc-0.2V
Test Condition
Unit
Vcc=1.5V, CS1Vcc-0.2V
data retention waveform
Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) CS20.2V(CS2 controlled)
Revision February 1999
K6F1008U2A Family
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
Address Data Previous Data Valid
CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than (Min.) both given device from device device interconnection.
Revision February 1999
K6F1008U2A Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
CMOS SRAM
TIMING WAVEFORM WRITE CYCLE(2) (CS1
Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision February 1999
K6F1008U2A Family
TIMING WAVEFORM WRITE CYCLE(3) (CS2 Controlled)
Address tAS(3) tCW(2) tWP(1) Data Data Valid tCW(2) tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap high write begins latest transition among goes low, going high going write earliest transition among going high, going going high, measured from begining write write. measured from going going high write. measured from address valid beginning write. measured from write address change. applied case write ends going high tWR2 applied case write ends going low.
DATA RETENTION WAVE FORM
controlled
2.7V tSDR Data Retention Mode tRDR
2.2V CS1VCC 0.2V
controlled
2.7V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision February 1999
K6F1008U2A Family
PACKAGE OUTLINE
BALL FINE PITCH BGA(0.75mm ball pitch)
View Bottom View
CMOS SRAM
Units: millimeters
INDEX MARK 0.50 0.50
C1/2 Detail 0.25/Typ. 0.80/Typ. Notes. Bump counts: 48(8row 6column) Bump pitch (x,y)=(0.75 0.75)(typ.) tolerence +/-0.050 unless otherwise specified. Typical coplanarity: 0.08(Max)
Side View
5.90 6.90 0.30 0.20
0.75 6.00 3.75 7.00 5.25 0.35 1.05 0.80 0.25
6.10 7.10 0.40 1.20 0.30 0.08
Revision February 1999
0.30
K6F1008U2A Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (0813.4F)
CMOS SRAM
Units: millimeters(inches)
0.20 0.008
+0.10 -0.05 +0.004 -0.002
13.40 ±0.20 0.528 ±0.008
0.10 0.004
8.40 0.331 8.00 0.315
0.25 0.010
0.50 0.0197
1.00 ±0.10 0.039 ±0.004
0.25 0.010
11.80 ±0.10 0.465 ±0.004
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.05 0.002 1.20 0.047
0.45~0.75 0.018~0.030
0.50 0.020
Revision February 1999

128Kx8 Super Power Voltage CMOS Static CMOS SRAM Revision Hi

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