32Kx8 High-Speed CMOS Static (3.3V Operating). Operated Commercial Ind
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K6E0808V1E-C/E-L, K6E0808V1E-I/E-P
32Kx8 High-Speed CMOS Static (3.3V Operating). Operated Commercial Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev. Rev. Rev. History Initial release with preliminary. Release Final Data Sheet. Delete Preliminary. Relex Standby current. Item Previous Isb1 0.3mA Draft Data Aug. 1998 Sep. 1998 Remark Preliminary Final
Current 0.5mA
Remark L-ver. Normal
attached data sheets prepared approved SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications. SAMSUNG Electronics will evaluate reply your requests questions parameters this device. have questions, please contact SAMSUNG branch office near your office, call contact Headquarters.
Revision August 1998
K6E0808V1E-C/E-L, K6E0808V1E-I/E-P
FEATURES
Fast Access Time 12,15,20ns(Max.) Power Dissipation Standby (TTL) 20mA(Max.) (CMOS) 2mA(Max.) 0.5mA(Max.) L-ver. only Operating K6E0808V1E-12 70mA(Max.) K6E0808V1E-15 70mA(Max.) K6E0808V1E-20 70mA(Max.) Single ±0.3V Power Supply Compatible Inputs Outputs Fully Static Operation Clock Refresh required Three State Outputs Standard Configuration K6E0808V1E-J 28-SOJ-300 K6E0808V1E-T 28-TSOP1-0813,
CMOS SRAM
High-Speed CMOS Static (3.3V Operating)
GENERAL DESCRIPTION
K6E0808V1E 262,144-bit high-speed Static Random Access Memory organized 32,768 words bits. K6E0808V1E uses common input output lines output enable which operates faster than address access time read cycle. device fabricated using SAMSUNGs advanced CMOS process designed highspeed circuit technology. particularly well suited high-density high-speed system applications. K6E0808V1E packaged 300mil 28-pin plastic TSOP1 forward.
CONFIGURATION(Top View)
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
ORDERING INFORMATION
K6E0808V1E-C12/C15/C20 K6E0808V1E-I12/I15/I20 Commercial Temp. Industrial Temp.
TSOP1
FUNCTIONAL BLOCK DIAGRAM
Gen.
Pre-Charge-Circuit
Select
Memory Array Rows 64x8 Columns
I/O8 I/O7 I/O6 I/O5 I/O4
I/O1 ~I/O8
Data Cont. Gen.
Circuit Column Select
I/O1 I/O2 I/O3
FUNCTION
Name Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3V) Ground I/O8
Revision August 1998
K6E0808V1E-C/E-L, K6E0808V1E-I/E-P
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT TSTG Rating -0.5 -0.5
CMOS SRAM
Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operating sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
RECOMMENDED OPERATING CONDITIONS*(TA=0 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Voltage Symbol -0.3** VCC+0.3*** Unit
above parameters also guaranteed industrial temperature range. VIL(Min) -2.0(Pulse Width 8ns) 20mA. VIH(Max) VCC+2.0V(Pulse Width 8ns) 20mA.
OPERATING CHARACTERISTICS*(TA=0 70°C,VCC=3.3±0.3V, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol Test Conditions CS=VIH OE=VIH WE=VIL VOUT Min. Cycle, 100% Duty CS=VIL, VIL, IOUT=0mA 12ns 15ns 20ns Standby Current ISB1 Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V VIN0.2V IOL=8mA IOH=-4mA Normal L-ver Unit
Output Voltage Level Output High Voltage Level
above parameters also guaranteed industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O Test Conditions VI/O=0V VIN=0V Unit
Capacitance sampled 100% tested.
Revision August 1998
K6E0808V1E-C/E-L, K6E0808V1E-I/E-P
CHARACTERISTICS (TA=0 70°C, VCC=3.3±0.3V, unless otherwise note
TEST CONDITIONS*
Parameter Input Pulse Levels Input Rise Fall Times Input Output timing Reference Levels Output Loads
above test conditions also applied industrial temperature range.
CMOS SRAM
Value 1.5V below
Output Loads(A)
Output Loads(B) tHZ, tLZ, tWHZ, tOW, tOLZ tOHZ +3.3V
DOUT
1.5V
30pF*
DOUT 5pF*
Capacitive Load consists components test environment.
Including Scope Capacitance
READ CYCLE*
Parameter Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Chip Enable Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Chip Selection Power Time Chip Selection Power DownTime Symbol tOLZ tOHZ K6E0808V1E-12 K6E0808V1E-15 K6E0808V1E-20 Unit
above parameters also guaranteed industrial temperature range.
Revision August 1998
K6E0808V1E-C/E-L, K6E0808V1E-I/E-P
WRITE CYCLE*
Parameter Write Cycle Time Chip Select Write Address Setup Time Address Valid Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z Symbol tWP1 tWHZ K6E0808V1E-12 K6E0808V1E-15
CMOS SRAM
K6E0808V1E-20 Unit
above parameters also guaranteed industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address Data Previous Valid Data Valid Data
TIMING WAVEFORM READ CYCLE(2)
(WE=VIH)
Address tOLZ Data Current tLZ(4,5) Valid Data tOHZ tHZ(3,4,5)
Revision August 1998
K6E0808V1E-C/E-L, K6E0808V1E-I/E-P
NOTES(READ CYCLE)
CMOS SRAM
high read cycle. read cycle timing referenced from last valid address first transition address. tOHZ defined time which outputs achieve open circuit condition referenced levels. given temperature voltage condition, (Max.) less than (Min.) both given device from device device. Transition measured ±200mV from steady state voltage with Load(B). This parameter sampled 100% tested. Device continuously selected with CS=VIL. Address valid prior coincident with transition low. common applications, minimization elimination contention conditions necessary during read write cycle.
TIMING WAVEFORM WRITE CYCLE(1)
(OE= Clock)
Address tCW(3) tAS(4) Data High-Z tOHZ(6) Data High-Z(8) Valid Data tWP(2) tWR(5)
TIMING WAVEFORM WRITE CYCLE(2)
(OE=Low Fixed)
Address tCW(3) tAS(4) Data High-Z tWHZ(6) Data High-Z(8) Valid Data
(10)
tWR(5)
tWP1(2)
Revision August 1998
K6E0808V1E-C/E-L, K6E0808V1E-I/E-P
TIMING WAVEFORM WRITE CYCLE(3) Controlled)
Address tCW(3) tAS(4) Data tWP(2)
CMOS SRAM
tWR(5)
High-Z
tWHZ(6)
Valid Data
High-Z
Data
High-Z
High-Z(8)
NOTES(WRITE CYCLE) write cycle timing referenced from last valid address first transition address. write occurs during overlap write begins latest transition going going write ends earliest transition going high going high. measured from beginning write write. measured from later going write. measured from address valid beginning write. measured from write address change. applied case write ends going high. Read Mode during this period, pins output low-Z state. Inputs opposite phase output must applied because contention occur. common applications, minimization elimination contention conditions necessary during read write cycle. goes simultaneously with going after going low, outputs remain high impedance state. Dout read data address. When pins output state. input signals opposite phase leading output should applied.
FUNCTIONAL DESCRIPTION
means Dont Care.
Mode Select Output Disable Read Write
High-Z High-Z DOUT
Supply Current ISB, ISB1
Revision August 1998
K6E0808V1E-C/E-L, K6E0808V1E-I/E-P
PACKAGE DIMENSIONS
28-SOJ-300
CMOS SRAM
Units:millimeters/Inches
7.62 0.300
8.51 ±0.12 0.335 ±0.005
6.86 ±0.25 0.270 ±0.010
0.20 18.82 0.741 18.41 ±0.12 0.725 ±0.005 1.30 0.051 0.051 0.69 0.027
+0.10 -0.05
0.008+0.004 -0.002
3.76 0.148
0.10 0.004
0.95 0.0375
0.43
+0.10 -0.05
0.017 +0.004 -0.002
1.27 0.050
0.71
+0.10 -0.05
0.028+0.004 -0.002
28-TSOP1-0813.4F
0.10 0.004
+0.10 -0.05 +0.004 0.008 -0.002
0.20
13.40 ±0.20 0.528 ±0.008 0.425 0.017
8.40 0.331 0.55 0.0217 0.25 0.010 11.80 ±0.10 0.465 ±0.004
1.00 ±0.10 0.039 ±0.004 0.15 0.006
+0.10 -0.05 +0.004 -0.002
8.00 0.315
1.20 0.047
0.05 0.002
0~8° 0.45 ~0.75 0.018 ~0.030 0.50 0.020
Revision August 1998
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