SST31LF021 SST31LF021E SST31LF023 SST31LF023E SST31LF021 021E 023
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Mbit Flash Mbit Kbit SRAM ComboMemory
SST31LF021 SST31LF021E SST31LF023 SST31LF023E
SST31LF021 021E 023E2Mb Flash (x8) 256Kb SRAM (x8) ComboMemories
FEATURES:
Monolithic Flash SRAM ComboMemory SST31LF021/021E: 256K Flash 128K SRAM SST31LF023/023E: 256K Flash SRAM Single 3.0-3.6V Read Write Operations Concurrent Operation Read from write SRAM while Erase/Program Flash Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Flash (typical) SRAM Read Standby Current: (typical) Flash Sector-Erase Capability Uniform KByte sectors Fast Read Access Times: SST31LF021/023 Flash: SRAM: SST31LF021E/023E Flash: SRAM: Latched Address Data Flash Flash Fast Erase Byte-Program: Sector-Erase Time: (typical) Bank-Erase Time: (typical) Byte-Program Time: (typical) Bank Rewrite Time: seconds (typical) Flash Automatic Erase Program Timing Internal Generation Flash End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Command Package Available 32-pin TSOP (8mm 14mm)
PRODUCT DESCRIPTION
SST31LF021/021E/023/023E devices 256K CMOS flash memory bank combined with 128K CMOS SRAM memory bank manufactured with SST's proprietary, high performance SuperFlash technology. pinout standards available these devices. SST31LF021/023 conform JEDEC standard flash pinouts SST31LF021E/023E conforms standard EPROM pinouts. SST31LF021/021E/023/023E devices write (SRAM flash) with 3.0-3.6V power supply. monolithic SST31LF021/021E/023/023E devices conform Software Data Protect (SDP) commands EEPROMs. Featuring high performance Byte-Program, flash memory bank provides maximum Byte-Program time µsec. entire flash memory bank erased programmed byte-by-byte typically seconds, when using interface features such Toggle Data# Polling indicate completion Program operation. protect against inadvertent flash write, SST31LF021/021E/ 023/023E devices have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, SST31LF021/021E/023/023E devices offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years.
©2001 Silicon Storage Technology, Inc. S71137-02-000 5/01
SST31LF021/021E/023/023E operate independent memory banks with respective bank enable signals. SRAM Flash memory banks superimposed same memory address space. Both memory banks share common address lines, data lines, OE#. memory bank selection done memory bank enable signals. SRAM bank enable signal, BES# selects SRAM bank flash memory bank enable signal, BEF# selects flash memory bank. signal used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. command sequence protects data stored flash memory bank from accidental alteration. SST31LF021/021E/023/023E provide added functionality being able simultaneously read from write SRAM bank while erasing programming flash memory bank. SRAM memory bank read written while flash memory bank performs SectorErase, Bank-Erase, Byte-Program concurrently. flash memory Erase Program operations will automatically latch input address data signals complete operation background without further input stimulus
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Preliminary Specifications requirement. Once internally controlled Erase Program cycle flash bank commenced, SRAM bank accessed Read Write. SST31LF021/021E/023/023E devices suited applications that both nonvolatile flash memory volatile SRAM memory store code data. system applications, SST31LF021/021E/023/023E devices significantly improve performance reliability, while lowering power consumption, when compared with multiple chip solutions. SST31LF021/021E/023/023E inherently less energy during Erase Program than alternative flash technologies. When programming flash device, total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter Erase time, total energy consumed during Erase Program operation less than alternative flash technologies. monolithic ComboMemory eliminates redundant functions when using separate memories similar architecture; therefore, reducing total power consumption. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST31LF021/021E/023/023E devices also improve flexibility using single package common signals perform functions previously requiring separate devices. meet high density, surface mount requirements, SST31LF021/021E/023/023E devices offered 32-pin TSOP packages. Figure pinouts.
SRAM Operation
With BES# BEF# high, SST31LF021/021E/ 023/023E operate 128K CMOS SRAM, with fully static operation requiring external clocks timing strobes. SRAM mapped into first KByte address space device. Read Write cycle times equal.
SRAM Read
SRAM Read operation SST31LF021/021E/023/ 023E controlled BES#, both have with high, system obtain data from outputs. BES# used SRAM bank selection. When BES# BEF# high, both memory banks deselected. output control used gate data from output pins. data high impedance state when high. Figure Read cycle timing diagram.
SRAM Write
SRAM Write operation SST31LF021/021E/023/ 023E controlled BES#, both have system write SRAM. BES# used SRAM bank selection. During Byte-Write operation, addresses data referenced rising edge either BES# WE#, whichever occurs first. Write time measured from last falling edge first rising edge BES# WE#. Figure Write cycle timing diagram.
Flash Operation
With BEF# active, SST31LF021/021E/023/023E operate 256K flash memory. flash memory bank read using common address lines, data lines, OE#. Erase Program operations initiated with JEDEC standard command sequences. Address data latched during commands internally timed Erase Program operations.
Device Operation
ComboMemory uses BES# BEF# control operation either SRAM flash memory bank. contention eliminated monolithic device will recognize both bank enables being simultaneously active. both bank enables asserted (i.e., BEF# BES# both low), BEF# will dominate while BES# ignored appropriate operation will executed flash memory bank. does recommend that both bank enables simultaneously asserted. other address, data, control lines shared; which minimizes power consumption area. device goes into standby when both bank enables raised VIHC.
Flash Read
Read operation SST31LF021/021E/023/023E devices controlled BEF# OE#, both have low, with high, system obtain data from outputs. BEF# used flash memory bank selection. When BEF# BES# high, both banks deselected only standby power consumed. output control used gate data from output pins. data high impedance state when high. Figure Read cycle timing diagram.
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Flash Erase/Program Operation
commands used initiate flash memory bank Program Erase operations SST31LF021/021E/ 023/023E. commands loaded flash memory bank using standard microprocessor write sequences. command loaded asserting while keeping BEF# high. address latched falling edge BEF#, whichever occurs last. data latched rising edge BEF#, whichever occurs first.
Flash Bank-Erase Operation
SST31LF021/021E/023/023E flash memory bank provides Bank-Erase operation, which allows user erase entire flash memory bank array "1s" state. This useful when entire bank must quickly erased. Bank-Erase operation initiated executing sixbyte Software Data Protection command sequence with Bank-Erase command (10H) with address 5555H last byte sequence. internal Erase operation begins with rising edge sixth BEF# pulse, whichever occurs first. During internal Erase operation, only valid Flash Read operations Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands loaded during Bank-Erase operation will ignored.
Flash Byte-Program Operation
flash memory bank SST31LF021/021E/023/ 023E devices programmed byte-by-byte basis. Before Program operations, memory must erased first. Program operation consists three steps. first step three-byte-load sequence Software Data Protection. second step load byte address byte data. During Byte-Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed, within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid Flash Read operations Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands loaded during internal Program operation will ignored.
Flash Write Operation Status Detection
SST31LF021/021E/023/023E flash memory bank provides software means detect completion flash memory bank Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle Read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Flash Sector-Erase Operation
Sector-Erase operation allows system erase flash memory bank sector-by-sector basis. sector architecture based uniform sector size KBytes. Sector-Erase operation initiated executing sixbyte-command load sequence Software Data Protection with Sector-Erase command (30H) sector address (SA) last cycle. address lines A17-A12 will used determine sector address. sector address latched falling edge sixth pulse, while command (30H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. End-of-Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands loaded during Sector-Erase operation will ignored.
Flash Data# Polling (DQ7)
When SST31LF021/021E/023/023E flash memory bank internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. flash memory bank then ready next operation. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth BEF#) pulse Program operation. Sector BankErase, Data# Polling valid after rising edge sixth BEF#) pulse. Figure Data# Polling timing diagram Figure flowchart.
S71137-02-000 5/01
©2001 Silicon Storage Technology, Inc.
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Flash Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating i.e., toggling between When internal Program Erase operation completed, toggling will stop. flash memory bank then ready next operation. Toggle valid after rising edge fourth BE#) pulse Program operation. Sector Bank-Erase, Toggle valid after rising edge sixth BEF#) pulse. Figure Toggle timing diagram Figure flowchart.
data Flash. following table lists valid states. does recommend that both bank enables, BEF# BES#, simultaneously asserted. CONCURRENT READ/WRITE STATE TABLE
Flash Program/Erase Program/Erase SRAM Read Write
Note that Product Identification commands SDP; therefore, these commands will also ignored while Erase Program operation progress.
Flash Memory Data Protection
SST31LF021/021E/023/023E flash memory bank provides both hardware software features protect nonvolatile data from inadvertent writes.
Product Identification
product identification mode identifies devices either SST31HF021 SST31HF021E manufacturer SST. This mode accessed hardware software operations. hardware device Read operation typically used programmer identify correct algorithm SST31LF021/021E/023/023E flash memory banks. Users wish software product identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Table hardware operation Table software operation, Figure software entry read timing diagram Figure entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST31LF021 SST31LF021E SST31LF023 SST31LF023E 0001H 0001H 0001H 0001H
T1.3
Flash Hardware Data Protection
Noise/Glitch Protection: BEF# pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Flash Write operation. This prevents inadvertent writes during power-up power-down.
Flash Software Data Protection (SDP)
SST31LF021/021E/023/023E provide JEDEC approved Software Data Protection scheme flash memory bank data alteration operations, i.e., Program Erase. Program operation requires inclusion series three-byte sequence. three byte-load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte load sequence. SST31LF021/021E/023/023E devices shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode, within TRC.
Data
0000H
Product Identification Mode Exit/Reset
order return standard Read mode, Software Product Identification mode must exited. Exiting accomplished issuing Exit command sequence, which returns device Read operation. Please note that software-reset command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
Concurrent Read Write Operations
SST31LF021/021E/023/023E provide unique benefit being able read from write SRAM, while simultaneously erasing programming Flash. device will ignore commands when Erase Program operation progress. This allows data alteration code executed from SRAM, while altering
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Design Considerations
recommends high frequency ceramic capacitor placed close possible between VSS, e.g., less than away from device. Additionally, frequency electrolytic capacitor from should placed within pin.
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
SRAM
BES# BEF#
Control Logic
Buffers
Address Buffers Latches
SuperFlash Memory
B1.2
Note: Most Significant Address
SST31LF021E/023E
BES#
SST31LF021/023
BES#
SST31LF021/023
F01.2
SST31LF021E/023E
BEF#
Standard Pinout View
BEF#
FIGURE ASSIGNMENTS 32-PIN TSOP (8MM
14MM)
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Preliminary Specifications TABLE DESCRIPTION
Symbol AMS1-A0 Name Address Inputs Functions provide memory addresses. During flash Sector-Erase, A17-A12 address lines will select sector. A17-A0 provide flash address A16-A0 provide SST31LF021/021E SRAM addresses A14-A0 provide SST31LF023/023E SRAM addresses output data during Read cycles receive input data during Write cycles. Data internally latched during flash Erase/Program cycle. outputs tri-state when BES# BEF# high. activate Flash memory bank when BEF# low. gate data output buffers. control Write operations. 3.0-3.6V Power Supply
T2.2
DQ7-DQ0
Data Input/output
BES# BEF#
SRAM Memory Bank Enable activate SRAM memory bank when BES# low. Flash Memory Bank Enable Output Enable Write Enable Power Supply Ground
Most significant address
TABLE OPERATION MODES SELECTION
Mode Flash Read Program Erase SRAM Read Write Standby Flash Write Inhibit VIHC Product Identification Hardware Mode Software Mode Manufacturer's (BFH) Device Code A17-A1=VIL, A0=VIL A17-A1=VIL, A0=VIH Table
T3.3
BES#
BEF#
DOUT
Address Sector address, Bank-Erase
VIHC
DOUT High High DOUT High DOUT High DOUT
VIH, other value. Device SST31LF021, SST31LF021E, SST31LF023, SST31LF023E.
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Preliminary Specifications TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Bank-Erase Software Entry4,5 Software Exit
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H Data
Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H Data
Write Cycle Addr1 5555H 5555H Data Data
Write Cycle Addr1 2AAAH 2AAAH Data
Write Cycle Addr1 SAX3 5555H Data
T4.3
Address format A14-A0 (Hex),Address A15, A16, VIH, other value, Command sequence. Program Byte address Sector-Erase; uses A17-A12 address lines device does remain Software Product Mode powered down. With A17-A1 Manufacturer's BFH, read with SST31LF021 Device 18H, read with SST31LF021E Device 19H, read with SST31LF023 Device 63H, read with SST31LF023E Device 64H, read with
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Operating Temperature -20°C +85°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V 0.5V Transient Voltage (<20 Ground Potential -1.0V 1.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE: SST31LF021/021E/023/023E
Range Commercial Extended Ambient Temp +70°C -20°C +85°C 3.0-3.6V 3.0-3.6V
CONDITIONS
TEST
Input Rise/Fall Time Output Load Figures
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Preliminary Specifications TABLE OPERATING CHARACTERISTICS (VDD 3.0-3.6V)
Limits Symbol Parameter Power Supply Current Read Flash SRAM Concurrent Operation Write Flash (Program) SRAM VIHC
Units
Test Conditions Address input VIL/VIH, f=1/TRC Min, VDD=VDD Max, open
0.7VDD VDD-0.3 VDD-0.2 11.4 12.6
OE#=VIL, WE#=VIH BEF#=VIL, BES#=VIH BEF#=VIH, BES#=VIL BEF#=VIH, BES#=VIL OE#=VIH, WE#=VIL BEF#=VIL, BES#=VIH BEF#=VIH, BES#=VIL BEF#=BES#=VIHC, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD -100 BEF#=OE#=VIL, WE#=VIH BEF#=OE#=VIL, WE#=VIH, A9=VH
T5.3
Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage Supervoltage Supervoltage Current
Specification applies commercial temperature devices only. This parameter higher extended devices.
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T6.1
TPU-WRITE1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O1
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T7.0
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T8.1
This parameter measured only initial qualification after design process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
CHARACTERISTICS
TABLE SRAM MEMORY BANK READ CYCLE TIMING PARAMETERS (VDD 3.0-3.6V)
SST31LF021/023-70 Symbol TRCS TAAS TBES TOES TBLZS1 TOLZS1 TBHZS1 TOHZS TOHS
SST31LF021E/023E-300 Unit
T9.3
Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time BES# Active Output Output Enable Active Output BES# High-Z Output Output Disable High-Z Output Output Hold from Address Change
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS (VDD 3.0-3.6V)
SST31LF021/023-70 Symbol TWCS TBWS TAWS TASTS TWPS TWRS TDSS TDHS Parameter Write Cycle Time Bank Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write recovery Time Data Set-up Time Data Hold from Write Time SST31LF021E/023E-300 Unit
T10.3
TABLE FLASH READ CYCLE TIMING PARAMETERS (VDD 3.0-3.6V)
SST31LF021/023-70 Symbol TBLZ1 TOLZ1 TBHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Bank Enable Access Time Address Access Time Output Enable Access Time BEF# Active Output Active Output BEF# High High-Z Output High High-Z Output Output Hold from Address Change SST31LF021E/023E-300 Units
T11.2
This parameter measured only initial qualification after design process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Preliminary Specifications TABLE FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS (VDD 3.0-3.6V)
SST31LF021/023-70 Symbol TOES TOEH TWPH TBPH TIDA TSBE Parameter Byte-Program Time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time High Setup Time High Hold Time BEF# Pulse Width Pulse Width Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Bank-Erase Bank Enable Setup Time Concurrent Operation SST31LF021E/023E-300 Units
T12.2
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
TRCS ADDRESS A16-0
TAAS
BEF# TBES BES# TOES TBLZS TOHS DATA VALID TBHZS HIGH-Z DATA VALID TOLZS TOHZS
DQ7-0
HIGH-Z
F02.0
FIGURE SRAM READ CYCLE TIMING DIAGRAM
TWCS ADDRESS A16-0 ADDRESS TAWS
BEF#
TBWS BES# TWPS TASTS TDSS DQ7-0 DATA VALID
F03.0
TWRS
TDHS
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
ADDRESS A17-0
BES#
BEF#
TOLZ
TOHZ TBHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TBLZ
DATA VALID
F18.0
FIGURE FLASH READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS A17-0 5555 BEF# BES# TWPH 2AAA 5555 ADDR
DQ7-0
DATA BYTE (ADDR/DATA)
F04.0
FIGURE FLASH CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
INTERNAL PROGRAM OPERATION STARTS ADDRESS A17-0 5555 2AAA 5555 ADDR
BES# BEF# DQ7-0 DATA BYTE (ADDR/DATA)
F05.0
TCPH
FIGURE BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A17-0
BES# BEF# TOEH TOES
F06.0
FIGURE FLASH DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
ADDRESS A17-0
BES# BEF# TOEH TOES
READ CYCLES WITH SAME OUTPUTS
F07.0
FIGURE FLASH TOGGLE
TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS A17-0 5555 2AAA 5555 5555 2AAA
BES#
BEF#
DQ7-0
Note:
F08.1
device also supports BEF# controlled Sector-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table Sector Address
FIGURE CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc. S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
SIX-BYTE CODE BANK-ERASE ADDRESS A17-0 5555 2AAA 5555 5555 2AAA 5555
TSBE
BES#
BEF#
DQ7-0
Note:
F17.1
device also supports BEF# controlled Bank-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table
FIGURE CONTROLLED FLASH BANK-ERASE TIMING DIAGRAM
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
BES#
BEF#
TWPH DQ7-0
F09.4
TIDA
DEVICE
FIGURE FLASH SOFTWARE ENTRY
©2001 Silicon Storage Technology, Inc.
Device SST31LF021 SST31LF021E, SST31LF023, SST31LF023E READ
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
BES# TIDA BEF#
DQ7-0
F10.0
FIGURE FLASH SOFTWARE EXIT
RESET
ADDRESS A17-0
BEj# BEj1#
DQ7-0
F20.0
Note:
FIGURE TIMING DIAGRAM
ALTERNATING
BETWEEN
FLASH/SRAM
SRAM/FLASH
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F11.1
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
F12.1
FIGURE TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Start
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 5555H
Load Byte Address/Byte Data
Wait Program (TBP, DATA# Polling bit, Toggle operation) Program Completed
F13.1
FIGURE BYTE-PROGRAM ALGORITHM
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Internal Timer Byte Program/Erase Initiated
Toggle Byte Program/Erase Initiated
Data# Polling Byte Program/Erase Initiated
Wait TBP, TSBE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match?
Program/Erase Completed
Program/Erase Completed
F14.0
FIGURE WAIT OPTIONS
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Software Product Entry Command Sequence
Software Product Exit Reset Command Sequence
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address:
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Wait TIDA
Load data: Address: 5555H
Load data: Address: 5555H
Return normal operation
Wait TIDA
Wait TIDA
Read Software
Return normal operation
F15.1
FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Chip-Erase Command Sequence Load data: Address: 5555H
Sector-Erase Command Sequence Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H
Load data: Address:
Wait TSBE
Wait
Chip erased
Sector erased
F16.1
FIGURE ERASE COMMAND SEQUENCE
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Preliminary Specifications Device Speed Suffix1 Suffix2 Package Modifier pins Numeric modifier Package Type TSOP (8mm 14mm) Temperature Range Commercial +70°C Extended -20°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Version Blank Flash Pinout EPROM Pinout Density Mbit Flash Mbit SRAM (Flash pinout) 021E Mbit Flash Mbit SRAM (EPROM pinout) Mbit Flash Kbit SRAM (Flash pinout) 023E Mbit Flash Kbit SRAM (EPROM pinout) Voltage 3.0-3.6V Device Family Monolithic ComboMemory
SST31LF02xx
SST31LF021/023 Valid combinations SST31LF021-70-4C-WH SST31LF021-70-4E-WH SST31LF023-70-4C-WH SST31LF023-70-4E-WH
SST31LF021E/023E Valid combinations SST31LF021E-300-4C-WH SST31LF023E-300-4C-WH SST31LF021E-300-4E-WH SST31LF023E-300-4E-WH
Example: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
PACKAGING DIAGRAMS
Identifier
1.05 0.95
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
32.TSOP-WH-ILL.4
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). Coplanarity: (±.05) Maximum allowable mold flash 0.15mm package ends, 0.25mm between leads.
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
14MM
©2001 Silicon Storage Technology, Inc.
S71137-02-000 5/01
Mbit Flash Mbit Kbit SRAM ComboMemory SST31LF021 SST31LF021E SST31LF023 SST31LF023E
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com
©2001 Silicon Storage Technology, Inc. S71137-02-000 5/01
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