FIGURE RECOMMENDED HARDWARE CONFIGURATION System Level Design Con

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FIGURE RECOMMENDED HARDWARE CONFIGURATION System Level Design Con

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AN709
FIGURE RECOMMENDED HARDWARE CONFIGURATION
System Level Design Considerations When Using I2CSerial EEPROM Devices
Rick Stoneking Microchip Technology Inc.
INTRODUCTION
Developing systems that implement protocol communicating with serial EEPROM devices requires that certain factors considered during hardware software development phase system achieve maximum compatibility robustness. This application note discusses these factors, both hardware software, help insure that optimal system design achieved. This application note limited single master systems therefore does specifically address unique requirements multimaster system. However, concepts presented this application note apply equally well those systems.
EEPROM
INSURING `BUS-FREE' DURING POWER-UP
order insure that internal state machine serial EEPROM correctly initialized power crucial guarantee that device sees `bus-free' condition (defined both being high) until VDDmin been reached. ideal guarantee this through pull-up resistors both lines. addition, these pull-ups should tied same voltage source device. other words device supplied from main positive supply rail then pull-ups should connected that same supply rail opposed being connected microcontroller pin, example). Figure example recommended hardware configuration. reasoning behind doing this same both adding pull-up line utilizing same supply pull-ups. anyone experience with CMOS logic already knows, necessary ensure that inputs tied either high low, since allowing CMOS input float lead number problems. line does have pull-up, pull-ups tied supply rail, then conditions occur, however briefly, where SCL/SDA inputs floating with respect supply voltage. When possible this condition should avoided.
CONDITIONS CONSIDERED
bi-directional nature data devices operate both transmit receive modes various times. order make this bi-directional operation possible protocol must define specific times which given device transmit receive, well define specific points protocol where functions swapped (i.e. transmitter becomes receiver receiver becomes transmitter). There number events which could potentially cause this sender/receiver `synchronization' lost, which result situations where: Both master slave send mode. Both master slave receive mode. `bit count' more bits between master slave. These events, which include microcontroller being reset during communication, brown-out conditions, excessive noise clock data lines, improper input levels during power effectively neutralized through combination hardware software techniques.
trademark Philips Semiconductors
1999 Microchip Technology Inc.
DS00709B-page
AN709
When possible pullup resistor line (i.e. hardware design already been finalized) then firmware should configured either: drive line high during power float input during power these options, first recommended method, despite typical concerns regarding latch-up, because does negatively impact battery life battery powered applications. Microchip Technology's serial EEPROM devices, like CMOS devices, susceptible latch-up, however latch-up does occur until currents excess 100mA injected into pin. Typical microcontrollers capable supply currents this magnitude, therefore risk latch-up extremely low. second option also acceptable does lead brief increase current draw device during time period which floating with respect VDD. This increase significant comparison normal standby current device have detrimental affect battery life power sensitive applications. cases important that lines actively held while EEPROM device powered This have indeterminable effect internal state machine and, some cases, state machine fail correctly initialize EEPROM will power incorrect state. Another improper practice which should pointed driving line high microcontroller rather than tri-stating allowing requisite pullup resistor pull high state. While this practice would appear harmless enough, indeed long microcontroller EEPROM device never sync, there potential high current situation occur. event that microcontroller EEPROM should sync, EEPROM outputting `low' (i.e. sending driving data `0') while microcontroller driving high then impedance path between created excessive current will flow microcontroller into EEPROM pin. amount current that flows limited only specification microcontoller's pin. This high current state obviously have very detrimental effect battery life, well potentially present long term reliability problems associated with excess current flow. START Clock nine bits START STOP
first START will cause device reset from state which expecting receive data from microcontroller. this mode device monitoring data receive mode detect START which forces internal reset. nine bits used force reset those devices that could reset previous START bit. This occurs only device mode where either driving acknowledge (low), output mode driving data bus. both these cases previous START (defined going while high) could generated device holding low. sending nine bits guaranteed that device will NACK (microcontroller does drive acknowledge data sent EEPROM) which also forces internal reset. second START sent guard against rare possibility erroneous write that could occur microcontroller reset while sending write command EEPROM, and, EEPROM driving when first START sent. this special case this second START sent, instead STOP sent, device could initiate write cycle. This potential erroneous write occurs only event microcontroller being reset while sending write command EEPROM. final STOP terminates activity puts EEPROM standby mode. This sequence does effect other devices which they will simply disregard invalid command.
SUMMARY
This application note presented ideas that fundamental nature, always obvious, utilization serial EEPROM devices. Ideally hardware/software engineer(s) takes these ideas into consideration during system development design accordingly. recommended that software reset sequence detailed this application note added system initilization code system that utilizes serial EEPROM device.
FORCING INTERNAL RESET SOFTWARE
designs recommended that software reset sequence sent EEPROM part microcontrollers power sequence. This sequence guarantees that EEPROM correct known state. Assuming that EEPROM powered into incorrect state that reset occurred microcontroller during communication), following sequence (which further explained below) should sent order guarantee that serial EEPROM device properly reset:
DS00709B-page
REFERENCES
`I2C-Bus Specification', Philips Semiconductors, January 1992 `The I2C-Bus It', Philips Semiconductors, April 1995
1999 Microchip Technology Inc.
AN709
NOTES:
1999 Microchip Technology Inc.
DS00709B-page
Note following details code protection feature PICmicro® MCUs. PICmicro family meets specifications contained Microchip Data Sheet. Microchip believes that family PICmicro microcontrollers most secure products kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using PICmicro microcontroller manner outside operating specifications contained data sheet. person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable". Code protection constantly evolving. Microchip committed continuously improving code protection features product.
have further questions about this matter, please contact local sales office nearest you.
Information contained this publication regarding device applications like intended through suggestion only superseded updates. your responsibility ensure that your application meets with your specifications. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights.
Trademarks Microchip name logo, Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, MATE, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode Total Endurance trademarks Microchip Technology Incorporated U.S.A. Serialized Quick Turn Programming (SQTP) service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2002, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved.
Printed recycled paper.
Microchip received QS-9000 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona July 1999. Company's quality system processes procedures QS-9000 compliant PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs microperipheral products. addition, Microchip's quality system design manufacture development systems 9001 certified.
2002 Microchip Technology Inc.
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01/18/02
2002 Microchip Technology Inc.

FIGURE RECOMMENDED HARDWARE CONFIGURATION System Level Design Con

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