Family Specifications January 1995 File under Integrated Circuits
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Family Specifications
January 1995 File under Integrated Circuits, IC04
Philips Semiconductors
Family Specifications
INTRODUCTION These specifications cover common electrical characteristics entire HE4000B family, unless otherwise specified individual device data sheet. LOCMOS HE4000B family devices will operate over recommended power supply range referenced (usually ground). Parametric limits guaranteed Because wide operating voltage, power supply regulation less critical than with other types logic. lower limit supply voltage determined required system speed and/or noise immunity interface other logic. recommended upper limit determined power dissipation constraints interface other logic. Unused inputs must connected VDD, another input. Inputs outputs protected against electrostatic effects wide variety device-handling situations. However, totally safe, desirable take handling precautions into account. RATINGS Limiting values accordance with Absolute Maximum System (IEC 134) SYMBOL Ptot PARAMETER Supply voltage Voltage input current into input output Power dissipation package (plastic ceramic DIL) (plastic mini-pack) (ceramic DIL) Tstg Tamb Tamb Power dissipation output Storage temperature Operating ambient temperature (HEF) Operating ambient temperature (HEC) Tamb Tamb Tamb Tamb Tamb Tamb +125 derate linearly with mW/K derate linearly with mW/K derate linearly with mW/K +150 +125 CONDITIONS MIN. -0.5 -0.5 TYP. MAX. UNIT
January 1995
January 1995
Philips Semiconductors
CHARACTERISTICS devices unless otherwise specified. Tamb (°C) SYMBOL PARAMETER MIN. Quiescent device current gates buffers, flip-flops Output voltage Output voltage HIGH Input voltage (buffered stages only) Input voltage HIGH (buffered stages only) 4.95 9.95 14.95 11.0 16.0 0.05 0.05 0.05 4.95 9.95 14.95 11.0 16.0 0.05 0.05 0.05 4.95 9.95 14.95 11.0 15.0 30.0 1500 0.05 0.05 0.05 13.5 13.5 VDD; VDD; valid input combinations; VDD; MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS
Family Specifications
January 1995
Philips Semiconductors
Tamb (°C) SYMBOL PARAMETER MIN. Input voltage (unbuffered stages only) Input voltage HIGH (unbuffered stages only) Output (sink) current -IOH Output (source) current HIGH -IOH IOZH -IOZL Output (source) current HIGH Input leakage current 3-state output leakage current; HIGH 3-state output leakage current; 12.5 0.52 0.52 MAX. 12.5 0.44 0.44 MIN. MAX. 12.5 0.36 0.36 MIN. MAX. 12.0 12.0 13.5 13.5 13.5 output returned output returned UNIT CONDITIONS
Family Specifications
January 1995
Philips Semiconductors
CHARACTERISTICS devices unless otherwise specified. Tamb (°C) SYMBOL PARAMETER MIN. Quiescent device current gates buffers, flip-flops Output voltage Output voltage HIGH Input voltage (buffered stages only) Input voltage HIGH (buffered stages only) 4.95 9.95 14.95 11.0 0.25 10.0 20.0 0.05 0.05 0.05 4.95 9.95 14.95 11.0 0.25 10.0 20.0 0.05 0.05 0.05 4.95 9.95 14.95 11.0 15.0 30.0 1500 0.05 0.05 0.05 13.5 13.5 VDD; VDD; valid input combinations; VDD; MAX. MIN. MAX. +125 MIN. MAX. UNIT CONDITIONS
Family Specifications
January 1995
Philips Semiconductors
Tamb (°C) SYMBOL PARAMETER MIN. Input voltage (unbuffered stages only) Input voltage HIGH (unbuffered stages only) Output (sink) current -IOH Output (source) current HIGH -IOH IOZH -IOZL Output (source) current HIGH Input leakage current 3-state output leakage current; HIGH 3-state output leakage current; 12.5 0.64 0.64 MAX. 12.5 MIN. MAX. 12.5 0.36 0.36 +125 MIN. MAX. 12.0 12.0 13.5 13.5 13.5 output returned output returned UNIT CONDITIONS
Family Specifications
Philips Semiconductors
Family Specifications
handbook, halfpage
MGK555
handbook, halfpage
MGK556
(mA)
(mA)
Tamb
Tamb
Fig.1 P-channel drain characteristics (source).
Fig.2 N-channel drain characteristics (sink).
handbook, halfpage
MGK557
handbook, halfpage
MGK558
(mA)
(mA)
Tamb
Tamb
Fig.3 P-channel drain characteristics (source).
Fig.4 N-channel drain characteristics (sink).
January 1995
Philips Semiconductors
Family Specifications
handbook, halfpage
(mA)
MGK553
handbook, halfpage
(mA)
MGK554
Tamb
Tamb
Fig.5 P-channel drain characteristics (source).
Fig.6 N-channel drain characteristics (sink).
Note: temperature coefficient: -0.4%/°C
January 1995
Philips Semiconductors
Family Specifications
CHARACTERISTICS Clock input rise fall times (tr, upper limits vary widely from device device with supply voltage. Unless otherwise specified individual data sheets recommended that input rise fall times less than Output transition times (tTLH, tTHL) Tamb input transition times SYMBOL PARAMETER output transition times tTHL HIGH tTLH HIGH Temperature coefficient (typical values) Propagation delays Output transition times +0.35%/°C +0.35%/°C (1.0 ns/pF) (0.42 ns/pF) (0.28 ns/pF) (1.0 ns/pF) (0.42 ns/pF) (0.28 ns/pF) MIN. TYP. MAX. UNIT TYPICAL EXTRAPOLATION FORMULA
Input capacitance (digital inputs) Maximum input capacitance
January 1995
Philips Semiconductors
Family Specifications
handbook, full pagewidth
CLOCK INPUT tWCPH thold
tWCPL thold
DATA INPUT
tTHL
tTLH tPLH
OUTPUT
SET, RESET, PRESET INPUT
tPHL
MGK561
waveforms above active transition clock input going from HIGH active level forcing signals (SET, CLEAR PRESET) HIGH. actual direction active transition clock input actual active levels forcing signals specified individual device data sheet.
Fig.7 Set-up times, hold times, recovery times propagation delays sequential logic circuits.
January 1995
Philips Semiconductors
Family Specifications
handbook, full pagewidth
OUTPUT ENABLE tPLZ OUTPUT LOW-to-OFF OFF-to-LOW tPHZ OUTPUT HIGH-to-OFF OFF-to-HIGH outputs connected
tPZL
tPZH
outputs disconnected
MGK559
outputs connected
Fig.8 Propagation delays 3-state outputs.
handbook, halfpage
other inputs output disable
with 3-state outputs
tPLZ, tPZL tPHZ, tPZH
MGK560
Fig.9 Test circuit 3-state output ICs.
January 1995
Philips Semiconductors
Family Specifications
DEFINITIONS SYMBOLS TERMS USED DATA SHEETS Currents Positive current defined conventional current flow into device. Negative current defined conventional current flow device. Input current; current flowing into device specified input voltage VDD. Output current HIGH; drive current flowing device specified HIGH output voltage VDD. Output current LOW; drive current flowing into device specified output voltage VDD. Quiescent power supply current; current flowing into lead specified input conditions. Output current; leakage current flowing into output 3-state device state when output connected VSS. Input current LOW; current flowing into device specified level input voltage specified VDD. Input current HIGH; current flowing into device specified HIGH level input voltage specified VDD. Quiescent power supply current LOW; current flowing into lead with specified level input voltage inputs specified conditions. Quiescent power supply current HIGH; current flowing into lead with specified HIGH level input voltage inputs specified conditions. state leakage current; leakage current flowing into output 3-state device state specified output voltage VDD. Voltages voltages referenced VSS, which most negative potential applied device. Supply voltage; most positive potential device. Supply voltage; device with single negative power supply, most negative power supply, used reference level other voltages; typically ground. Supply voltage; (VSS VEE) negative power supplies. device with dual negative power supply, most negative power supply reference level other voltages. Input voltage HIGH; range input voltages that represents logic HIGH level system. Input voltage LOW; range input voltages that represents logic level system. Output voltage HIGH; range voltages output terminal with specified output loading supply voltage. Device inputs conditioned establish HIGH level output. Output voltage LOW; range voltages output terminal with specified output loading supply voltage. Device inputs conditioned establish level output. Trigger threshold voltage; positive-going signal. Trigger threshold voltage; negative-going signal.
IDDL
IDDH
Analogue terms resistance; effective state resistance analogue transmission gate, specified input voltage, output load VDD. resistance; difference effective resistance between transmission gates analogue device specified input voltage, output load VDD.
January 1995
Philips Semiconductors
Family Specifications
switching parameters Input frequency; combinatorial logic devices maximum number inputs outputs switching accordance with device truth table. sequential logic devices clock frequency using alternate HIGH data input using toggle mode, whichever applicable. Output frequency; each output. Clock frequency; clock input waveform should have duty cycle such cause outputs switching from 10%VDD 90%VDD accordance with device truth table. Clock input rise fall times; value. Propagation delay time; time between specified reference points, normally points input output waveforms, with output changing from defined level defined HIGH level. Propagation delay time; time between specified reference points, normally points input output waveforms, with output changing from defined HIGH level defined level. Transition time, LOW-to-HIGH; time between specified reference points waveform, normally points, that changing from HIGH. Transition time, HIGH-to-LOW; time between specified reference points waveform, normally points, that changing from HIGH LOW. Pulse width; time between amplitude points leading trailing edges pulse. Hold time; interval immediately following active transition timing pulse (usually clock pulse) following transition control input latching level, during which interval data recognized must maintained input ensure their continued recognition. negative hold time indicates that correct logic level released prior timing pulse still recognized. tPLZ Set-up time; interval immediately preceding active transition timing pulse (usually clock pulse) preceding transition control input latching level, during which interval data recognized must maintained input ensure their recognition. negative set-up time indicates that correct logic level initiated sometime after active transition timing pulse still recognized. 3-state output disable time, HIGH time between specified reference points, normally point output enable input voltage waveform point representing drop output voltage waveform 3-state device, with output changing from output HIGH level (VOH) high impedance OFF-state. 3-state output disable time, time between specified reference points, normally point output enable input voltage waveform point representing (VDD VOL) rise output voltage waveform 3-state device, with output changing from output level (VOL) high impedance OFF-state. 3-state output enable time, HIGH; time between specified reference points, normally point output enable input voltage waveform point representing rise output voltage waveform 3-state device, with output changing from high impedance OFF-state output HIGH level (VOH). 3-state output enable time, LOW; time between specified reference points, normally point output enable input voltage waveform point representing (VDD VOL) voltage drop output voltage waveform 3-state device, with output changing from high impedance OFF-state output level (VOL). Recovery time; time between overriding asynchronous input, typically clear reset input, earliest permissible beginning synchronous control input, typically clock input, normally measured points both input voltage waveforms.
fmax
tPHZ
tPLH
tPHL
tTLH
tPZH
tTHL
tPZL
thold
January 1995
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