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RAD5A4
RECONFIGURABLE ARITHMETIC DATAPATH DEVICE
DESCRIPTION SPECIFICATIONS
INFINITE TECHNOLOGY CORPORATION
RAD5A4
Reconfigurable Arithmetic Datapath
Quality Assurance
quality system focuses high quality components best possible service customers. RAD5A4 been designed optimize arithmetic performance.
1995, 1996, 1997 Infinite Technology Corporation, Inc.
Infinite Technology Corporation, Richardson, Texas, reserves right make changes products without notice order improve design performance characteristics.
Trademarks RADis trademark Infinite Technology Corporation, Richardson, Texas. RADwareis trademark Infinite Technology Corporation, Richardson, Texas. Reconfigurable Arithmetic Datapathis trademark Infinite Technology Corporation, Richardson, Texas.
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Description Specifications
RAD5A4 DATA BOOK
Contents
Product Status Part Number Description High-Speed Accelerator Algorithms Architecture Description RAD5A4 Configuration Device Specifications Revision History Terms Definitions Appendix
MacroSequencer programming information found MacroSequencer Programming Manual this book. programming configuration file generation found RADware Windows Manual. Simulation information found VHDL Simulation Guide this book. Typical applications using RAD5A4 devices described various Notes which contain Application descriptions implementations, Execution Results, Example MacroSequencer assembly programs.
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Description Specifications Reconfigurable Arithmetic Datapath
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Description Specifications
TABLE CONTENTS
PRODUCT STATUS PART NUMBER DESCRIPTION HIGH-SPEED ACCELERATOR DATA STREAM ALGORITHMS
HIGH-PERFORMANCE MULTIPLY-ACCUMULATE MULTIPLE OPERATIONS CLOCK CYCLE DATA STREAM PROCESSING RAD5A4 COMPONENTS RAD5A4 PERFORMANCE.
IMAGING APPLICATIONS ARITHMETIC ACCELERATOR APPLICATIONS.7 RAD5A4 COPROCESSOR RAD5A4 MATRIX PROCESSING RAD5A4 VIDEO FILTERING NOISE FILTERING
EASE IMPLEMENTATION
DESIGN TOOLS
IN-CIRCUIT RECONFIGURABILITY .GREAT TIME-TO-MARKET ARCHITECTURE DESCRIPTION RAD5A4 DATA RAD5A4 CONTROL INPUT CLOCKS MACROSEQUENCER DESCRIPTION MACROSEQUENCER ARITHMETIC DATAPATH
INPUT REGISTERS INPUT SELECTOR MULTIPLIER-ACCUMULATOR ADDER SHIFTER LOGIC UNIT 1-PORT MEMORY 3-PORT MEMORY Smart Indexing OUTPUT SELECTOR INTERFACE
MACROSEQUENCER DATAPATH CONTROLLER
COMPONENTS CONTROL SIGNALS
Infinite Technology Corporation Phone: 972-437-7800 March 1997
RAD5A4
Description Specifications Reconfigurable Arithmetic Datapath STATUS SIGNALS ADDER STATUS SIGNALS PROGRAM COUNTER BRANCH OPERATIONS LONG INSTRUCTION WORD REGISTER INSTRUCTION MEMORY COUNTER0 COUNTER1 STACK INDEX REGISTERS
MACROSEQUENCER CONFIGURATION BITS RAD5A4 DUAL DESCRIPTION
INPUT SELECTORS MINTERM GENERATOR ARRAYS ARRAY FUNCTION GENERATOR FIXED ARRAYS CONTROL ARRAY CTRLREG REGISTER OUTPUT ARRAY OUTPUT REGISTER PLAI/O BUFFERS
RAD5A4 CONFIGURATION
CONFIGURATION CONTROL DESCRIPTION RAD5A4 CONFIGURATION MODES
NORMAL OPERATING MODE: PGM0 PGM1 LOW.66 PASSIVE CONFIGURATION MODE: PGM0 PGM1 HIGH, OTHER LOW.66 ACTIVE CONFIGURATION MODE: PGM0 PGM1 HIGH.
CONFIGURING RAD5A4 DEVICE CONFIGURATION WITH POSITIVE HANDSHAKING SIGNALS CONFIGURATION TIMING
CONFIGURATION SUMMARY MINIMIZING CONFIGURATION TIME.78 CONFIGURATION WITHOUT HANDSHAKING
TIME CONFIGURE RAD5A4.
PLACLK PULSES MEMORY CONFIGURED Reading PLACLK Pulses Configuration Table.84 PLACLK PULSES DEVICE CONFIGURATION DEVICE CONFIGURATION TIME
MULTIPLE RAD5A4 DEVICE CONFIGURATION. CONFIGURATION DATA WORD COUNTER DEVICE SPECIFICATIONS LIST ABSOLUTE MAXIMUM RATINGS
March 1997 Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Description Specifications
TTL-LEVEL INTERFACE OPTIONS (PRELIMINARY SPECIFICATION) CMOS-LEVEL INTERFACE OPTIONS (PRELIMINARY SPECIFICATION) CMOS-LEVEL INTERFACE OPTIONS (PRELIMINARY SPECIFICATION)104 TIMING DIAGRAMS
MEASUREMENT DIAGRAM LOAD CIRCUIT OUTPUT .111
TRANSITIONING BETWEEN ACTIVE NORMAL OPERATING MODES
WAVEFORMS .113
DIAGRAM RAD5A4 DESCRIPTION.
POWER SUPPLY PINS .115 MACROSEQUENCER PINS .116 INPUT PINS .118 PINS.119 CONFIGURATION PINS .120 SCAN PINS.121
PACKAGE CHARACTERISTICS
POWER DISSIPATION VERSUS CLOCK FREQUENCY .122 THERMAL CHARACTERISTICS .124
PACKAGE MECHANICAL DETAILS
THIN QUAD FLAT PACK (TQFP), PINS .126 POWER TQFP, PINS .127
REVISION HISTORY TERMS DEFINITIONS
ACRONYMS GLOSSARY. APPENDIX TABLE SIGNAL NAMES MACROSEQUENCER LONG INSTRUCTION WORD
Multiplexers.142 Assembly Operations.145 SETTING SUMMARY.152
JTAG SCAN CIRCUITRY
BOUNDARY SCAN PATH MAP.156 Instruction Register.160 Device Identification Register Specification .161
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March 1997
RAD5A4
Description Specifications Reconfigurable Arithmetic Datapath
viii
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Description Specifications
TABLE FIGURES
Figure Number Figure Name Part Number Description Simplified RAD5A4 Operational Block Diagram Video Filter Application RAD5A4 Coprocessor Matrix Processing Reconfigurable Video Filter Noise Filter Programming RAD5A4 Simplified RAD5A4 Data Flow Block Diagram MacroSequencer MacroSequencer Datapath Block Diagram MacroSequencer Input Registers MacroSequencer Input Selector Multiplier-Accumulator Adder Shifter Logic Unit 1-port Memory 3-port Memory 3-port Memory Index Pointers Output Selector Interface MacroSequencer Datapath Controller Dual Block Diagram Input Selector Product Terms Function Generator Fixed Block Diagram Fixed Schematic Fixed Block Diagram Fixed Schematic Control Control Simplified Schematic Control Register Output Output Simplified Schematic Output Register PLAI/O Buffers Page Number
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Description Specifications Reconfigurable Arithmetic Datapath
Figure Number
Figure Name Configuration Timing Initial Portion Configuration Timing Mid-Cycle Portion Configuration Timing Continue Portion Configuration Timing Halt Portion Configuration Timing with Invalid Preamble Minimizing Configuration Timing Mid-Cycle Portion Detailed Configuration Timing Mid-Cycle Portion Synchronous Configuration Timing Initial Portion Synchronous Configuration Timing Mid-Cycle Portion Synchronous Configuration Timing Continue Portion Synchronous Configuration Timing Halt Portion Multiple RAD5A4 Configuration Configuration Data Word Counter
Page Number
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Description Specifications
RAD5A4
RECONFIGURABLE ARITHMETIC DATAPATH DEVICE
DATAPATH SOLUTIONS SMALLER, FASTER, SOONER
INFINITE TECHNOLOGY CORPORATION
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Description Specifications Reconfigurable Arithmetic Datapath
Product Status
Infinite Technology Corporation uses various product status markings designate phases documentation relates products. markings appear beginning each data sheet. following Data Sheet Classification definitions explain status specifications presented this Data Book.
Definitions
Data Sheet Classification Objective Specification Product Status Formative Design Definition This data sheet reflects target design specifications product development. Specifications change manner without notice. This data sheet reflects preliminary data based engineering samples. Characterization tests have been completed some parameters. Supplementary data will published upon availability. Specification changes made time without notice improve design supply best possible product. This data sheet reflects Final Specifications. Infinite Technology Corporation reserves right make changes products without notice order improve design performance characteristics. table
Preliminary Specification
Preproduction Product
Production Specification
Full Production
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Description Specifications
Part Number Description
Part number ordering information devices shown following diagram. information specific package, speed, operating temperature combinations, interface type, refer individual device data sheets this data book, contact Marketing (214) 437-7800.
Device Family
Reconfigurable Arithmetic Datapath
Count
pins
Device Package Type
Thin plastic quad flat pack (TQFP) Power TQFP
Operating Temperature Range
Commercial +70°C)
Interface Type
CMOS CMOS
Operating Clock Frequency Designation
-100 only) only)
Device Number
internal data buses MacroSequencers
figure
Device Type
Operating Clock Frequency (MHz) -70, -100 -40,
Interface Type
Operating Temperature Range table
Device Package Type
Number Pins
RAD5A4
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Reconfigurable Arithmetic Datapath
RAD5A4
Reconfigurable Arithmetic Datapath Device
High-Speed Accelerator Data Stream Algorithms
RAD5A4 high speed accelerator data stream algorithms. contains four independent 16-bit fixed-point programmable processors called MacroSequencers that together execute Multiple Instructions Multiple Data paths (MIMD). MacroSequencers operate independently combined even greater performance those systems requiring real-time operation.
High-Performance Multiply-Accumulate
Operating 75-100% multiplier efficiency across wide range applications, RAD5A4 MacroSequencer architecture provides:
multiply-accumulate (MAC) clock cycle Million 8-bit MACs second Million 16-bit MACs second
Multiplier efficiency enhanced with local Registers, 1-port 3-port Memories using smart Index Registers. multiplier's accumulator bits support extended filter linear transform computations.
Multiple Operations Clock Cycle
Each RAD5A4 MacroSequencer designed with Long Instruction Word (LIW) architecture enabling multiple operations clock cycle. Independent operation fields control MacroSequencer's data memories, 16-bit adder, multiplier-accumulator, logic unit, shifter, registers they used simultaneously with branch control. pipelined architecture allows seven operations execution units during each clock cycle.
Operations clock cycle MacroSequencer Million operations second MacroSequencer Billion operations second RAD5A4
RAD5A4 architecture optimizes performance allowing algorithms implemented with small number long instruction words. Each MacroSequencer holds thirty-two LIWs, each capable operations.
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath
Data Stream Processing
RAD5A4 provides cost effective, quick time-to-market solution High Speed Data Stream requirements imaging simulation applications such Video, Real-time Custom Array, Parallel Processor, Medical Photo Manipulation.
Input Data Stream
RAD5A4
Math Algorithm
Output Data Stream
RAD5A4 takes more input data streams, applies high-speed arithmetic algorithms, outputs more data streams.
RAD5A4 Components
heart RAD5A4 consists four MacroSequencers which supported five global 16-bit buses, connections pins input pins, built-in Dual with pins input pins, five independent clocks which drive four MacroSequencers Dual clock rates MHz.
Simplified RAD5A4 Operational Block Diagram
MS2I/O[15:0] MS3I/O[15:0]
Bus4IN[15:0]
MacroSequencer MacroSequencer
PLAI/O[7:0] PLAIN[7:0]
MacroSequencer MacroSequencer
Dual
Bus0 Control
MS0I/O[15:0]
MS1I/O[15:0]
figure
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Reconfigurable Arithmetic Datapath
RAD5A4 contains Dual which used initiating stream processes, output enable signal generation, glue interface. Dual often referred simply PLA.
Package
RAD5A4 available 176-pin plastic Thin Quad Flat Pack (TQFP) Power TQFP packages.
RAD5A4 Performance
RAD5A4 accelerates arithmetic algorithms such Discrete Cosine Transform (DCT) Inverse Discrete Cosine Transform (IDCT) Finite Impulse Filter (FIR) filter video speeds Fast Fourier Transform (FFT) analysis Array processing Convolution Linear transformations Signal processing formatting Process control
example, these speeds typical RAD5A4 performance: Algorithm 1024 complex 16-bit FFT* Convolution Convolution bit) IDCT bit) bit) IDCT bit) Color Space Conversion table RAD5A4s Data Stream Speed
Computation inner most loop only. Refer Note.
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath
Imaging Applications
Imaging applications require many multiply-accumulates benefit from greater performance. RAD5A4 improves these imaging applications: Video filter Multi-media image scaling image functions Medical instrumentation Photo manipulation Satellite Radar Sonar
Video Filter Application
Video Input
RAD5A4
Math Algorithm
3Channel
figure
Arithmetic Accelerator Applications
Communications (Linear transformations) Digital Compression Robotics FPGA Coprocessor Coprocessor Avionics Encryption Digital Filtering Noise Filtering
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Reconfigurable Arithmetic Datapath
RAD5A4 Coprocessor
RAD5A4 Coprocessor Micro-Computer FPGA RAD5A4
Math Algorithm Input Data Stream Output Data Stream
figure
RAD5A4 Matrix Processing
RAD5A4 devices combined into blocks number MacroSequencers larger algorithms.
Matrix Processing
Input Data Stream
Output Data Stream
RAD5A4
Memory
Control
FPGA
FPGA
Data Control Buses
figure more FPGAs, DSPs, other microprocessors used interfacing Buses.
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath
RAD5A4 Video Filtering
NTSC interlaced video protocol which requires frame buffer 2dimensional applications. less complex applications, frame buffer necessary.
Reconfigurable Video Filter
RAD5A4 Video Filter
NTSC Input
Video Decoder
FPGA Switch Matrix
Video Encoder
Enhanced NTSC Ouput
Frame Buffer
figure
Noise Filtering
Noise Removal Video Audio RAD5A4
Time domain input with frequency noise
Transform frequency domain separate frequency noise from signal
Optional Filter
RAD5A4
Filtered time domain output with noise reduction
Inverse
From frequency time domain
figure
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Reconfigurable Arithmetic Datapath
Ease Implementation
Applications development simplified with following features: Programming readily implemented using RADware design tools. Predictable timing arithmetic algorithms. Example configurations predefined RADware design tools. TTL, CMOS interface Rapid Reconfiguration less than
Each MacroSequencer programmed using RAD5A4 assembly language. hardware oriented instruction with only fourteen Datapath operations sixteen Controller operations. Each operation performs multiple low-level operations. Most operations executed during each clock cycle allowing multiple operations cycle high performance efficient processing. Dual programmed using subset VHDL language. MacroSequencer instruction code source code created text editor. These MacroSequencer source files then compiled using VHDL compiler RAD5A4 assembler combined RAD5A4 software produce configuration file. vector file produced VHDL simulation. These files used configure RAD5A4 device simulation. When programming devices, design separated into: Arithmetic Algorithms programmed into MacroSequencers Test Vectors Process initiation response, handshake, protocol logic programmed into Dual PLA.
.vec
Test Vectors
.msa
MacroSequencer Source Code
.vhd
VHDL Design File
RADware
Combines Source Files create Configuration File Simulation File
.cfg
Configuration File
.sim
Simulation File
figure
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Several standard configurations that bypass provided within software package. These options will program nothing while connecting MacroSequencers external pins.
Dual External Control Signals
MacroSequencers execute independently ways: Each MacroSequencer pair execute independently from each other with programs initiated from either Dual external control pins.
Design Tools
RAD5A4 fully supported ITC's RADwaresystem. This system contains VHDL compiler programming PLA, MacroSequencer assembler, RAD5A4 Fitter which will combine compiled files produce reports, configuration file program RAD5A4 vector file with VHDL model simulator. VHDL model test-bench provided testing debugging applications. This VHDL model used with Vantage Model Technology VHDL simulators running test vectors verifying design operation. RADwaresystem offered with Windows interface.
In-Circuit Reconfigurability .Great Time-to-Market
RAD5A4 first family Reconfigurable Arithmetic Datapath (RAD) devices designed specifically datapath applications that demand high-speed arithmetic operations data stream. RAD5A4 reconfigured time less than FPGAs CPLDs inefficient solutions arithmetic datapath applications. RAD5A4 devices specifically address these performance density issues while retaining flexibility time-to-market benefits other programmable devices. implementation cost high arithmetic performance RAD5A4 devices provide significant advantages computationally intensive applications. RAD5A4 devices offer simplicity digital filter, dynamic flexibility DSP, speed custom ASIC.
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
RAD5A4
Reconfigurable Arithmetic Datapath Device High Speed Accelerator Data Stream Algorithms
Architecture Description
RAD5A4 composed array four 16-bit fixed-point processors, called MacroSequencers, that individually initiated either using Dual PLA-based built-in periphery logic directly from control pins. Five 16-bit data buses connect MacroSequencers pins allow data shared passed according design needs. addition each pair MacroSequencers coupled directly private 16-bit buses. These private buses allow each pair MacroSequencers paired together additional data sharing. heart RAD5A4 four MacroSequencers which supported Five global 16-bit buses, (bus0 Connections pins (MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], MS3I/O[15:0]) input pins (BUS4IN[15:0]), Five independent clocks which drive MacroSequencers clock rates MHz. built-in Dual PLA.
MacroSequencers
Each RAD5A4 MacroSequencer designed with Long Instruction Word (LIW) architecture enabling multiple operations clock cycle. Independent operation fields control MacroSequencer's data memories, 16bit adder, multiplier-accumulator, logic unit, shifter, registers they used simultaneously with branch control. pipelined architecture allows seven operations execution units during each cycle. RAD5A4 architecture optimizes performance allowing algorithms implemented with small number long instruction words. Each MacroSequencer configured operate independently, paired some 32-bit arithmetic operations. MacroSequencer0, referred MacroSequencer(n) where specifies respective MacroSequencer number.
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description data flow from MacroSequencers shown here:
Simplified RAD5A4 Control Data Flow Diagram
MS2I/O[15:0] Bus0 Bus1 Bus2 Bus3 BUS4IN[15:0] PLAI/O[7:0] PLAIN[7:0]
MS3I/O[15:0]
Dual
MacroSequencer
MSPair32
MSPair23
MacroSequencer
Bus4 Control
Direct Control Status Pins
MacroSequencer
MSPair10
MSPair01
MacroSequencer
MS0I/O[15:0]
MS1I/O[15:0]
figure
Built-In Glue Logic
programmable Dual built into device initiate processes MacroSequencers provide glue logic interface capabilities. PLAI/O[7:0] pins configured individually input only output only pins. These used external interface control. Process initiation response provided externally input pins directly MacroSequencers provided programmable control bus.
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
Operation Modes
RAD5A4 operates either normal operating mode configuration mode. RAD5A4 configured during Active Configuration mode which allows each MacroSequencer's instruction memory Data Memories Dual memory programmed. Normal Operating mode, RAD5A4 MacroSequencers concurrently execute Long Instruction Words (LIWs) programmed into each MacroSequencer's instruction memory. Passive Configuration mode disables device pins disables device from being configured, that other RAD5A4s same circuit configured.
Paired MacroSequencer Operational Support
MacroSequencers used individually 16-bit operations pairs standard 32-bit addition, subtraction, logic operations. When pairing, MacroSequencers interchangeable. MacroSequencers form pair, MacroSequencers form other pair. least significant sixteen bits processed MacroSequencers summary this information listed here: Paired MacroSequencers First Pair MacroSequencer number Least significant 16-bits Most significant 16-bits Paired MacroSequencer table Second Pair
Paired MacroSequencer Names
Each pair MacroSequencers have private data buses between them labeled MSPair(nm) MSPair(mn) where first references MacroSequencer that sources data, second references recipient MacroSequencer. refers current MacroSequencer, refers other MacroSequencer pair. source data from OutRegB signal MacroSequencer(m). four data buses between paired MacroSequencers are: Name Data buses between Paired MacroSequencers MSPair01 MSPair10 MSPair23 MSPair32 From MacroSequencer table MacroSequencer
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
RAD5A4 Data
RAD5A4 Data composed five global 16-bit data buses that simultaneously accessed MacroSequencers. Four buses, bus0, bus1, bus2, bus3, associated with MacroSequencer0, respectively. fifth bus, bus4, always receives data from BUS4IN[15:0] pins. Data bus0, bus1, bus2, bus3 receive data from either MacroSequencer output registers from MacroSequencer pins. Each MacroSequencer input access from buses. However, each MacroSequencer only place data onto respective busn from output register, OutRegA onto MSnI/O pins. Busn receive inputs from either MSnI/O[15:0] pins from output register, OutRegA MacroSequencer(n). Input/Output between busn MSnI/O[15:0] pins determined configuration bits instruction memory each MacroSequencer MSnOE oepla[n].
RAD5A4 Control
Control used communicate control, status, output enable information between MacroSequencer external MacroSequencer pins.
Control Signals
control signals sent MacroSequencer described MacroSequencer Datapath Controller section. They used Initiate available sequences, Continue execution sequence, Acknowledge MacroSequencer status flags resetting send await state bits. MacroSequencer(n)'s Configuration determines whether control signals from MSnCTRL[1:0] pins from PLA0 CtrlReg[2n+1:2n] signals. Configuration bits selected using RADware design tools.
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
Status Signals
MacroSequencer always executes Register every clock cycle. Await Send status signals from MacroSequencer described MacroSequencer Datapath Controller section indicate: Program Counter sequencing. MacroSequencer send state, executed specific LIW. Program Counter continuing sequence. MacroSequencer await state, executed specific LIW. Program Counter continuing sequence, awaiting further commands before resuming. status signals, Send Await, sent from MacroSequencer(n)s output both MSnAWAIT MSnSEND outputs Dual input selectors. direct control pins shown Simplified RAD5A4 Control Data Flow diagram (figure control interface signals which connect directly between pins each MacroSequencer. These signals (MSnAwait, MSnSend, MSnCTRL[1:0], MSnOE) included table MacroSequencer Control Interface Signals (table
Output Enable
output enable circuitry MacroSequencer(n) described Output Selection description allows output enable From Dual oepla[n] outputs from MacroSequencer(n) output enable MSnOE pins. Always output Always input (the power condition) Optionally inverted.
MacroSequencer Control Interface Signals
following table lists names control, status, output enable signals that interface with MacroSequencers. MacroSequencer Status Signals Pins Dual MS0AWAIT, MS0SEND MS1AWAIT, MS1SEND MS2AWAIT, MS2SEND MS3AWAIT, MS3SEND Control Signals From Pins MS0CTRL[1:0] MS1CTRL[1:0] MS2CTRL[1:0] MS3CTRL[1:0] table From Dual PLACtrl0[1:0] PLACtrl1[3:2] PLACtrl2[5:4] PLACtrl3[7:6] Output Enable From Pins MS0OE MS1OE MS2OE MS3OE From Dual oepla[0] oepla[1] oepla[2] oepla[3]
MacroSequencer0 MacroSequencer1 MacroSequencer2 MacroSequencer3
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Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Input Clocks
Five input clocks provided allow RAD5A4 process multiple data streams different transmission speeds. There clock each MacroSequencer, separate clock PLA. Each MacroSequencer operate separate data paths different rates. clock signals connected, synchronization between four MacroSequencers Dual PLA. clock (PLACLK) used Active Configuration Mode.
System Constraints
MacroSequencers change states rising edge their respective clock signals. Signals between Dual MacroSequencers resynchronized receiving MacroSequencer Dual PLA. Techniques should employed reduce timing skew which occur printed circuit board layout. When using RAD5A4 high clock frequencies, data should loaded captured synchronously with proper set-up hold times. bandwidth MSnI/O[15:0] pins BUS4IN[15:0] one-half MacroSequencer clock frequency. Data input should asserted pins MacroSequencer clock period before data captured MacroSequencer's registers. Data output these pins should asserted MacroSequencer clock period before data captured external circuitry.
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
MacroSequencer Description
Each MacroSequencer identical composed functional blocks, Arithmetic Datapath, Datapath Controller. 3-port 1-port memories accessed arithmetic data path. instruction memory, 3port 1-port memories loaded during Active Configuration Mode.
MacroSequencer
Data
bus0, bus1, bus2, bus3, bus4, MSPairmn
3-Port Memory 1-Port Memory
Data Interface
busn MSPairnm MSnI/O[15:0]
Arithmetic Datapath
Adder Status bits: Equal, Overflow, Sign
Control bits
MSnCTRL[1:0] PLACtrln[1:0] MSnOE oepla[n]
Control Signals
Datapath Controller
Instruction Memory
Status Signals
MSnAwait MSnSend
figure control signals initiate programmed sequences instruction memory normal operating mode. Once sequence begins, will run, loop indefinitely until stopped control signals. await state programmed into sequence will stop Program Counter from continuing increment. sequences combination data steering, data processing, branching operations. Each MacroSequencer execute combination branch, memory access, logic, shift, add, subtract, multiply-accumulate, input output operations each clock cycle. instruction memory reloaded dynamically time transitioning Active Configuration Mode which will also initialize registers entire device. MacroSequencer0, referred MacroSequencer(n) where specifies respective MacroSequencer number.
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
MacroSequencer Arithmetic Datapath
MacroSequencer Arithmetic Datapath pipelined structure where data processed stages. There nine basic elements MacroSequencer Arithmetic Datapath. these data processing functions other three data steering functions. data processing elements include: Multiplier-Accumulator (MAC), Adder, Shifter, Logic Unit, 3-port Data Memory, 1-port Data Memory.
data steering functions include the: Input Register block capture inputs, Input Selector selecting three operands data processing elements, Output Register block select which data processing elements stored. processor core contains four parallel data processing units: MultiplierAccumulator (MAC), Adder, Logic Unit, Shifter. Each data processing unit runs independently others allowing execution multiple operations cycle. Inputs MacroSequencer(n) include: Direct access sixteen pins (MSnI/O[15:0]). Five 16-bit internal buses (bus0, bus1, bus2, bus3, bus4) where busn connected MSnI/O[15:0] output register, OutRegA from MacroSequencer(n). Bus4 always connected BUS4IN[15:0] shared between MacroSequencers Dual PLA. Paired MacroSequencer 16-bit MSPair(mn) from MacroSequencer(m)'s OutRegB MacroSequencer(n)'s Input Register.
Infinite Technology Corporation Phone: 972-437-7800
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
MacroSequencer Datapath Block Diagram
mem1 mem2
3-Port Memory 1-Port Memory
Register
mem0
bus0 bus1 Input Selectors Input Registers bus2 bus3 bus4 MSPairmn
InBusC InRegA InBusA InBusB
MultOutA,B
Adder Status
Output Selector
Adder
OutRegA
Interface
nI/O
InRegB
Logic Unit
OutRegB
MSPairnm
Shifter
Constant
figure Each these data processing functions MacroSequencer Datapath Block Diagram discussed individually following sections. They controlled operation fields MacroSequencer's Register. MacroSequencer discussions that follow, terms `external' `internal' refer signals external internal RAD5A4 device, only signals external internal individual MacroSequencer. Relevant Register control bits shown MacroSequencer Arithmetic Datapath data processing functions. They defined RAD5A4 Long Instruction Word Appendix.
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Input Registers
16-bit input registers named InRegA InRegB. There external inputs internal input available Input Registers.
MacroSequencer Input Registers
LIW[4:2]
bus4 Constant bus0 bus1 bus2 bus3 MSPairmn
InRegA
InRegB
Register
LIW[7:5]
figure There several possible input selections each MacroSequencer Input Register: Five 16-bit internal buses (bus0, bus1, bus2, bus3, bus4) 16-bit from partner MacroSequencer(m)'s OutRegB each pair labeled MSPair(nm), Constant (0-65535) generated from Register bits LIW[43:28].
Constant introduces 16-bit constants into calculation. constant MacroSequencer shares internal signals with MacroSequencer Controller well MAC, Shifter, Logic Unit. Since Constant field shared, care must taken insure that overlap these signals does occur. RAD5A4 Assembler detects reports overlap problems. Related Assembly Operations: Syntax <src>,<dest>
Allowed values arguments
<src>: bus0, bus1, bus2, bus3, bus4, pair, 65535 <dest>: inrega, inregb table
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath pair parameter selects MSPair(mn) which from OutRegB other member pair MacroSequencers. When operation occurs, input register holds data. Resource Conflicts: When using constant value, there conflict with MAC, Logic Unit, Shifter, some Datapath Controller instructions.
Input Selector
Input Selector generates InBusA, InBusB, InBusC signals. Data these buses independent. There controls InBusB enable number zero used invert selected result. InBusA InBusB available MAC, Adder, Logic Units. InBusC available only Shifter.
MacroSequencer Input Selector
InRegA OutRegA OutRegB mem1 mem0 InRegB
LIW[9:8] LIW[13]
InBusA
InBusB
mem2
LIW[12:10] LIW[14]
InBusC
figure Inputs Input Selector include: InRegA InRegB from Input Register, OutRegA OutRegB from Output Register, Mem1 mem2 from 3-port Memory read ports respectively, Mem0 from 1-port Memory read port, Constant which generated Input Selector does involve Register bits LIW[43:28].
Control signals from MacroSequencer Controller determine which three eight possible inputs used whether InBusB inverted not. Input Selector automatically controlled RADware assembly language operations Multiplier, Adder, Shifter, Logic Unit does require separate programming.
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
input selections controlled same assembly operations used MAC, Adder, Logic Unit Shifter.
Multiplier-Accumulator
Multiplier-Accumulator (MAC) three-stage, multiplier capable producing full 32-bit product multiply every cycles. architecture allows next multiply begin first stages before result output from last stage that once pipeline loaded, result (24-bit product) generated every clock cycle.
Multiplier Accumulator
Multiplier
Operand OutRegB InBusB
Accumulator
Operand mem0 InBusA
Adder:
MultOutA MultOutB
LIW[42:41] LIW[47,44] LIW[43,40]
Register
figure
Input Stage
input stage loads operands assures proper byte alignment multiplier. multiplier input multiplexers serve purposes: They align high bytes from operand multiplier which allows multiply operations; They allow inputs selected from three different sources each operand: Operand selected from 1-port memory, InBusA, operand from previous cycle. Operand selected from high byte OutRegB, InBusB, least significant byte previous operand
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RAD5A4
Architecture Description Related Assembly Operations: Syntax mult1 <srca>, <srcb> Allowed values arguments <srca>: inrega, outrega, outregb, mem1, mem0 <srcb>: inregb, outrega, outregb, mem2, mem0, table Resource Conflicts: Using mem0 outregb arguments makes InBusA InBusB available other assembly operations. mult1 hold operation holds operand moves byte operand Multiplier stage input. Reconfigurable Arithmetic Datapath
mult1 hold
Multiplier Stage
Multiplier produces 24-bit product from registered 16-bit operand either most significant byte (8-bits) least significant byte operand
Accumulator Stage
third stage aligns accumulates product. Controls accumulator allow product multiplied when <weight> low, when <weight> high. result then: Added result accumulator when <enable> acc, Placed accumulator replacing previous value when <enable> clr, Held accumulator lieu mult3 operation. mult3 operation must follow cycles after mult1 operation. accumulator holds data when mult3 used. accumulator output divides 48-bit output into four 16-bit parts called (bits[15:0]), (bits[31:16]), high (bits [47:32]) norm (bits[30:15]). low, mid, high bits used conversion. Select norm when only bits signed multiplication result required. Related Assembly Operations: Syntax mult3 <weight>, enable> add1 mult, <pos> Allowed values arguments <weight>: high, <enable>: clr, <pos>: low, mid, high, norm table
Cycles Multiply
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description number cycles required Multiplies MACs shown these tables. Cycles Between Multiplies Multiply Accuracy bits bits bits bits table Cycles
Cycles Between Multiply Accumulates Products Multiply Accuracy bits bits bits bits bits bits table Cycles
internal format converted standard integer format Adder. this reason, multiply multiply-accumulate outputs must through Adder. desired, operands loaded every cycle. Multiplier results 24-bit product which then accumulated third stage result. This allows least multiply-accumulate operations before overflow. only upper bits 24-bit result required, lower bits discarded. more than 16-bit word extracted, accumulated result must extracted specific order. First lower 16-bit word moved Adder, followed order middle bits then upper bits. This allows least these 16-bit multiply-accumulate operations before overflow will occur. 16-bit MAC, operands loaded every other cycle. Example software MacroSequencer Assembly Language documentation.
Adder
Adder produces 16-bit result 16-bit addition, subtraction, 16-bit data conversion two's complement every cycle. Adder also used equality, less-than greater-than comparisons. Adder twostage structure: input multiplexers with first adder stage second
Infinite Technology Corporation Phone: 972-437-7800 March 1997
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath adder stage. architecture allows next adder operation begin first stage before result output from last stage. input multiplexers select sources data operation Adder. operands selected from either InBusA InBusB, from Multiplier. Select InBusA InBusB simple addition subtraction setting Adder Status flags. Select multiplier outputs, MultOutA MultOutB, conversion.
Adder
Carry
Carry Adder (pipe
MultOutA InBusA MultOutB InBusB
Adder (pipe
Adder Status Flags: Equality, Overflow, Sign Output Selector
LIW[15] config bit[3:2] LIW[16]
Register
figure first adder stage receives operands begins operation. second adder stage completes operation specifies output registers Output Selector where result will stored. adder stages controlled separately addition subtraction operations.
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RAD5A4
Reconfigurable Arithmetic Datapath Related Assembly Operations: Syntax add1 <oper1>, <oper2> Allowed values arguments <oper1>: inrega, outrega, outregb, mem1 <oper2>: inregb, outrega, outregb, mem2, mem0, <pos>: low, mid, high, norm <dest1>, <dest2>: outrega, outregb <srca>: inrega, outrega, outregb, mem1 <srcb>: inregb, outrega, outregb, mem2, mem0, <dest1>, <dest2>: outrega, outregb table Architecture Description
add1 mult, <pos> add2 [<dest1> <dest2>]] sub1 <srca>, <srcb>
sub2 [<dest1> <dest2>]]
add1 mult operation used data conversion Accumulator allows InRegA InRegB available other operations same cycle. sub1 operation inverts InBusB selection. sub2 used, Carry logical `1'.
Adder Configuration Bits Switches
Configuration bit[3] selects 32-bit 16-bit addition subtraction. 32/16 configuration RADware design tools. successful 32-bit operation, MacroSequencer1 and/or MacroSequencer3 should have 32/16bit configuration 32-bit operation. MacroSequencer0 MacroSequencer2 32/16-bit configuration should always proper operation. When 32-bit mode, signal tells other MacroSequencer pair Operand Operand equal. signal input upper bits. When MacroSequencer1 32-bit mode, External Carry from External Carry from MacroSequencer0. When MacroSequencer3 32bit mode, External Carry from External Carry from MacroSequencer2. External Carry MacroSequencer0 MacroSequencer2 from specialized circuitry addition subtraction carries. Configuration bit[2] selects whether operands signed values unsigned values. signed/unsigned configuration with directives when programming MacroSequencer. Refer MacroSequencer Configuration bits discussion Assembler Directives discussion MacroSequencer Programming Section more detail.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
Adder Status Bits
Equal, Sign, Overflow, Carry flags cycles after addition operation (add1 sub1) occurs remain effect clock cycle: Equal flag when operands equal during addition operation. Overflow flag when result addition subtraction results 16-bit out-of-range value. When adder configured unsigned integer arithmetic, Overflow Carry. Range 65535 When adder configured signed integer arithmetic, Overflow Carry Sign. Range -32768 +32767 Sign flag when result addition subtraction negative value. Carry flag indicates whether carry value exists.
Conversion
Adder used convert data Accumulator Multiplier standard integer formats when inputs selected from output MAC. outputs shown MultOutA MultOutB diagrams. Since Accumulator bits, multiplier's accumulated result must converted specific order: lower-middle 32-bit conversion, lowermiddle-upper 48-bit conversion. Once conversion process started, must continue every cycle until completed. Signed number conversion uses bits 30:15. Conversion explained more detail MacroSequencer Assembly Language examples.
Shifter
Shift Mode (type) signals control which Shifter functions performed: Logical Shift Left bits (shift order bits high order bits). data shifted Shifter lost, logical used fill bits shifted Logical Shift Right bits (shift high order bits order bits). data shifted Shifter lost, logical used fill bits shifted Arithmetic Shift Right bits. This same logical shift right with exception that bits shifted filled with Bit[15], sign bit. This equivalent dividing number Rotate Shift Left bits. bits shifted from highest ordered shifted into lowest ordered bit. Normalized Shift Right bit. bits shifted lower order. lowest lost highest replaced Overflow Register Adder. This used scale number when 16-bit words added produce 17-bit result.
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description Logical, Arithmetic Rotate shifts shift zero fifteen bits determined Shift Length control signal.
Shifter
Adder Status Overflow InBusC
Shifter
type
Output Selector
LIW[35:32] LIW[38:36]
figure
Shift Mode (type) Shift Length controls shared Constant word; therefore, only these functions used cycle. Constant inputs MacroSequencer shown MacroSequencer Datapath Block Diagram. Related Assembly Operations: Syntax shift <src>, <type>,<length>, <dest1> <dest2>] Allowed values arguments <src>: inrega, outrega <type>: logicleft, logicright, arithmetic, rotate <length>: 0-15 0x0-0xf <dest1>, <dest2>: outrega, outregb <src>: inrega, outrega <dest1>, <dest2>: outrega, outregb table
shift <src>, normal, <dest1> [,<dest2>]
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
Logic Unit
Logic Unit able perform bit-by-bit logical function 16-bit vectors 16-bit result. positions will have same function applied. sixteen logical functions bits supported. Logic Function controls determine function performed.
Logic Unit
InBusA InBusB
Logic Unit
Output Selector
LIW[31:28]
figure Related Assembly Operations: Syntax logic <oper>, <dest1> <dest2>] logic <oper>, <srca>, <dest1> [,<dest2>] logic <oper>, <srcb>, <dest1> [,<dest2>] Allowed values arguments <oper>: <dest1>, <dest2>: outrega, outregb <oper>: nota, <srca>: inrega, outrega, outregb, mem1 <dest1>, <dest2>: outrega, outregb <oper>: notb, <src>: inregb, outrega, outregb, mem2, mem0, <dest1>, <dest2>: outrega, outregb <oper>: nor, notab, anotb, xor, nand, and, xnor, notaorb, aornotb, <srca>: inrega, outrega, outregb, mem1 <srcb>: inrega, outrega, outregb, mem2, mem0, <dest1>, <dest2>: outrega, outregb table
logic <oper>, <srca>, <srcb>, <dest1> <dest2>]
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RAD5A4
Reconfigurable Arithmetic Datapath sixteen logical functions are:
LIW[31:28] 0000 1111 0011 1100 1010 0101 0001 0010 0100 0110 0111 1000 1001 1011 1101 1110 Operation nand xnor Description logical logical inverted value inverted value notB nand xnor
Architecture Description
table Logic Function controls shared Constant word, Logic Unit, 1-port memory index register operations Function. Only these functions used cycle. output defined bits follows: Out[i] (LIW[28] A[i] B[i]) (LIW[29] A[i] B[i]) (LIW[30] A[i] B[i]) (LIW[31] A[i] B[i])
1-Port Memory
1-port memory supports single-cycle read single-cycle write operations, both same time. There addressable 16-bit memory locations 1-Port Memory. separate register provided store maintain result read operation until read executed. Read write operands control whether reading writing memory requested. operation performed when both Read Write controls inactive. Only operation, read write, occur cycle. Index register Datapath Controller provides read write address 1-port memory. index register incremented,
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath decremented, held with each operation. Both index operation read write operation controlled MacroSequencer LIW.
1-Port Memory
OutRegA 1-port Address
mem0
LIW[1]
LIW[0]
Register
figure Related Assembly Operations: Syntax oneport <oper> Allowed values arguments <oper>: write, read table
3-Port Memory
3-port memory 16-bit that supports read write operation each clock cycle. read ports used independently; however, data written same address either read address same clock cycle.
3-Port Memory
mem1
OutRegB 3-port Read1 Address 3-port Read2 Address 3-port Write Address
LIW[45]
mem2
LIW[46]
LIW[46,45,22]
Register
figure Four index registers associated with 3-port memory. separate registers provided write indexing: Write Offset (I3PWO) Write Index (I3PW). These registers loaded reset simultaneously independently. Write Offset provides mechanism offset read index
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description registers from Write Index fixed distance. Increment Decrement apply both write registers that offset maintained. Read Index registers independently reset aligned Write Offset. Related Assembly Operations: Syntax memwrite memread1 memread2 table Each index separate controls incremented, decremented, held after each read write operation. Syntax setindex <value> setindex <valuew>, <value1>, <value2> Allowed values arguments <value>: 0-31 0x0-0x1f <valuew>: 0-15 0x0-0xf <value1>: 0-15 0x0-0xf <value2>: 0-15 0x0-0xf <m0>: none, reset <mw>: none, resetoffset, resetall <m1>: none, reset, align <m2>: none reset, align <d0>: none, inc, <dw>: none, inc, dec, <d1>: none, inc, dec, <d2>: none, inc, dec, <index>: readwrite0, write, read1, read2, all3port Allowed values arguments arguments arguments arguments
indexmode <m0>, <mw>, <m1>, <m2>
indexdirect <d0>, <dw>, <d1>, <d2> <index>
table setindex operation sets index specified value. indexmode operation resets aligns index values. indexdirect operation controls whether index values incremented, decremented, held after access.
Smart Indexing
Smart indexing operates multiple memory addresses accessed. This particularly useful when data symmetrical. Refer symmetric filter Notes detailed examples. Symmetrical coefficients accessed providing Write Offset from center data aligning both Read Indices Write Offset. Read Indices separated dummy read. Additional simultaneous reads with index incrementing other decrementing allows addition subtraction data that uses same inverted coefficients.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
Each index separate direction controls. Each index increment decrement, and/or change direction. change each index register's address takes place after read write operation associated port.
3-port Memory Index Pointers
offset write offset write index
read1
read2
figure Smart indexing ideal Filter, applications where pieces data taken from equal distance away from center symmetrical data. smart index method used 3-port Memory allows symmetrical data multiplied half number cycles that would have normally been required. Data from both sides added together then multiplied with common coefficient. example, 6-tap filter which would normally take multiplies cycles, implemented with single MacroSequencer only requires cycles complete calculation. 8-point which normally requires multiplies cycles implemented with single MacroSequencer only requires clock cycles complete calculation.
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Output Selector
Output Selector controls state output registers OutRegA OutRegB controls state MSnI/O[15:0] pins.
Output Selector
Input Selector Logic Unit Shifter Adder Input Selector MSnI/O[15:0] InRegB
LIW[18:17]
OutRegA
OutRegB
LIW[21:19]
Register
figure Output Selector multiplexes five 16-bit buses places results 16-bit output registers which drive on-chip buses MacroSequencer pins. Output registers held multiple cycles.
Inputs
output selector receives inputs from the: Adder, Logic Unit, Shifter, InRegB, MacroSequencer MSnI/O[15:0] pins.
Outputs
output selector places outputs OutRegA OutRegB. Output Register OutRegA, available the: Input Selector, Write port 1-port memory, MSnI/O pins, Busn input from MacroSequencer(n) OutRegA. Data placed busn available other three MacroSequencers.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath Output Register OutRegB, available the: Write port 3-port memory, Input Selector, MAC, Paired MacroSequencer MSPair(nm) where: OutRegB from MacroSequencer0 source MSPair01. OutRegB from MacroSequencer1 source MSPair10. OutRegB from MacroSequencer2 source MSPair23. OutRegB from MacroSequencer3 source MSPair32. Related Assembly Operations: Syntax move pins, outregb Allowed values arguments arguments; moves value InRegB OutRegB arguments; moves value MSnI/O pins OutRegB table
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Interface
Interface selection each MacroSequencer determines: Input source data busn output enable configuration.
MacroSequencer Interface
MSnI/O[15:0]
Output Selector
config bit[4]
busn MSnI/O[15:0] Port
(Input) OutRegA MSnOE oepla[n]
config bit[7:6] config bit[8]
(Output)
figure Interface diagram output enable circuitry represents equivalent output enable selection configuration bits normal operating mode. These MacroSequencer configuration selections made RADware design tools.
Busn Selection
input data busn selected from MSnI/O[15:0] pins OutRegA output MacroSequencer(n) configuration When MacroSequencer(n)'s associated busn connected OutRegA signal, MacroSequencer still input access MSnI/O pins Output Selector.
Output Enable Control
Output Enable MSnI/O pins controlled configuration selections. Inputs output enable control circuitry include MSnOE MacroSequencer(n) oepla[n] signal.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
MacroSequencer Datapath Controller
MacroSequencer Datapath Controller contains executes sequences Long Instruction Words (LIWs) that configured into instruction memory. Datapath Controller generates bits which control MacroSequencer Arithmetic Datapath. also generates values 1-port 3-port index registers. controller accepts control signals from PLACtrl(n)[1:0] signals external MSnCTRL pins which initiates possible sequences. outputs Send Await status signals external MSnSEND MSnAWAIT pins. Datapath Controller operation determined MacroSequencer contents register control signals.
Components
Each MacroSequencer Controller contains following elements: Program Counter (PC), Register which holds currently executing LIW, 48-bit reprogrammable Instruction Memory, loop counters: Counter0 Counter1, Return Stack `calls' which holds return addresses, Index Registers 1-port 3-port memories.
Inputs include: Controln signals setting sequences, issuing Continue commands Adder status bits: Equal, Overflow, Sign. Outputs include: instruction bits, 1-port 3-port memory addresses, single-bit Send Await Status signals
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description Datapath Controller shown following diagram.
MacroSequencern Datapath Controller
Register Memory
Control Bits
Adder Status Control Signals MSnCTRL PLACtrln
1-Port Address 3-Port Read1 Address 3-Port Read2 Address
Sequence Controller
Control
I3pR1
Stack
Configuration
I3pR2
Counter
Counter
I3pWO
I3pW
3-Port Write Address Status Signals
Register
figure Datapath Controller synchronous pipelined structure. 48-bit instruction fetched from instruction memory address generated program counter registered into register clock cycle. actions occurring during next clock cycle determined contents register from previous clock cycle. Meanwhile, next instruction being read from memory contents register changed next clock cycle that instructions executed every clock cycle. Because synchronous pipelined structure, Datapath Controller will always execute next instruction before branch operations executed. program counter initiated control signals. increments branches address executed next.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath Adder status signals, Stack Counter elements Datapath Controller support program counter. Their support roles are: Adder status bits report value Equal, Overflow, Sign, branch operations. Stack contains return addresses. Counter0 Counter1 hold down loop-counter values branch operations. five index registers hold write, read, write offset addresses 1port 3-port memories. write offset register (I3PWO) used alignment read index registers, holds value offset distance from 3-port memory write index read indices. Each Datapath Controller Block Diagram elements described detail.
Control Signals
Direct Control Status pins shown Simplified RAD5A4 Control Data Flow diagram (figure control status interface signals which connect directly between pins each MacroSequencer. direct control signals MSnCTRL[1:0], MSnOE, direct status signals MSnAWAIT MSnSEND. These listed table MacroSequencer Control Interface Signals (table Alternatively, MacroSequencers control signals from Dual PLA. Dual also receives MacroSequencer status signals. Control signals each MacroSequencer specify four control commands. They selected from either MSnCTRL[1:0] pins from PLACtrln signals. control state MacroSequencer next clock cycle determined state above components state these PLACtrln[1:0] signals. four control states include:
SetSequence0
SetSequence0 sets holds Program Counter resets Send Await state registers without initializing other registers MacroSequencer. clock cycles after SetSequence0 received, Datapath Controller will execute every clock cycle. Program Counter does change until Continue command received.
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
SetSequence2
SetSequence2 sets holds Program Counter resets Send Await state registers without initializing other registers MacroSequencer. clock cycles after SetSequence2 received, Datapath Controller will execute every clock cycle. Program Counter does change until Continue command received.
permits normal operation Datapath Controller. command should asserted every cycle during normal operation except when resetting Send and/or Await flags, initiating sequence with SetSequence0 SetSequence2.
Continue
Continue resets both Send Await status signals permits normal operation. Await State asserted, Program Counter will resume normal operation next cycle. await operation encountered while Continue command effect, Continue command will apply, await operation will halt Program Counter, will Await status register `1'. Therefore, Continue command should changed command after clock cycles. send operation encountered while Continue command effect, Continue command will apply, Send status register will `1'.
About Commands
following table summarizes four command options Controln[1:0] which from PLACtrln from MSnCTRL pins: Controln [1:0] Command Continue SetSequence0 Description Normal Operating Condition Reset Send Await registers. Program Counter `0'. Resets Send Await registers. This must asserted least cycles. Program Counter `2'. Resets Send Await registers. This must asserted least cycles. table
SetSequence2
allowing sequence starting points, each MacroSequencer programmed perform algorithms without reloading. PLACtrln signals synchronized within MacroSequencer. MSnCTRL signals synchronized within MacroSequencer; therefore, consideration timing requirements necessary.
Infinite Technology Corporation Phone: 972-437-7800 March 1997
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
Status Signals
There single-bit registered status signals that notify external pins when MacroSequencer reached predetermined point sequence operations. They Await Send status signals. Both Status signals their registers reset these conditions: During Power Reset, Active configuration part RAD5A4, During Control States: SetSequence0, SetSequence2, Continue. Related Assembly Operations: Syntax await send Allowed values arguments arguments arguments table
When await operation asserted from register, MacroSequencer executes next instruction, repeats execution that next instruction until Continue SetSequence command received. await instruction stops Program Counter from continuing change sets Await status signal register `1'. Continue command resets Await status signal register allowing Program Counter resume. send operation only sets Send status signal register `1'. Execution sequence continues. Program Counter stopped. Continue command will reset Send status signal register `0'. Status signals resynchronized Dual with PLACLK.
Adder Status Signals
Adder status bits, Equal, Overflow, Sign provided conditional jumps.
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Program Counter
Program Counter 5-bit register which changes state based upon number conditions. program counter incremented, loaded directly, `2'. three kinds operations which affect MacroSequencer Program Counter explicitly are: Branch operations, SetSequence0 SetSequence2 commands, Await operation. Program Counter zero `0': During power-on Reset, During Active configuration part RAD5A4, During SetSequence0 command, When Program Counter reaches value `31', previous contain branch another address, Upon execution branch operation address `0'.
Control Signal Effects:
Controln[1:0] signals used reset program counter either time with either SetSequence0 SetSequence2 respectively. command begins maintains execution program counter according LIW. Continue command resumes program counter operation after Await state resets Send Await registers next rising clock edge. Continue command after Send operation resets Send register next rising clock edge.
Status Signal Effects:
Await status register Program Counter stops next clock cycle after await operation encountered. Continue command resets Send Await registers permits Program Counter resume. Send status register next clock cycle after send operation. Continue command required reset Send register. Send operation does effect Program Counter.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
Branch Operations
register contain Branch operation time. Conditional Branches should performed during SetSequence commands insure predictable conditions. Branch Operation Assembly Instruction Result Program Counter Program Counter <address>. Program Counter <address> respective loop counter non-zero value. respective loop counter will then decremented next clock cycle. Program Counter <address> Adder status bits agree with branch condition.
Unconditional branch jump <address> Branch loop Counter0 jumpcounter0 <address> jumpcounter1 <address> loop Counter1 equal Branch Adder status condition: Equal, Overflow, Sign Call subroutine jumpequal <address> jumpoverflow <address> jumpsign <address> call <address>
Return from subroutine operation
return
current address plus Program Counter pushed onto Stack. contents Program Counter next clock cycle will address LIW. address from Stack popped into Program Counter. table
Long Instruction Word Register
purpose 48-bit Register hold contents current executed. bits directly connected elements datapath. register loaded with contents instruction memory pointed Program Counter before Program Counter updated. effect that instruction calculated during next clock cycle.
Instruction Memory
Instruction memory consists thirty-two words 48-bit configured according MacroSequencer assembly language program. Instruction memory initialized during Power Reset. reliability, must configured before MacroSequencer execution begins. fields Registers control datapath operations program flow. They described detail Appendix.
Counter0 Counter1
There 5-bit loop counters labeled Counter0 Counter1. Both loop counters filled with `0's during Power Reset active configuration component RAD5A4.
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Counter0 Counter1 loaded setcounter0 setcounter1 operations respectively. jumpcounter0 jumpcounter1 operations will decrement respective counter next clock cycle until Counter value reaches `0'. SetSequence0 SetSequence2 control signals alter reset loop counters. Therefore, counters should initialized with setcounter0 setcounter1 operations before they referenced program. Related Assembly Operations: Syntax jumpcounter0 <address> jumpcounter1 <address> setcounter0 <value> setcounter1 <value> Allowed values arguments <address>: 0-31 0x0-0x1f label <address>: 0-31 0x0-0x1f label <value>: 0-31 0x0-0x1f <value>: 0-31 0x0-0x1f table
Stack
Stack holds return addresses. contains four 5-bit registers 2-bit stack pointer. After Power Reset active configuration component RAD5A4, stack pointer 5-bit registers initialized `0's. call performs unconditional jump after executing next instruction, pushes return address second instruction following call into Stack. return operation pops return address from Stack into Program Counter. call return operations will repeat corrupt Stack these operations next after await operation because program counter held that address, MacroSequencer repeats execution that address.
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RAD5A4
Architecture Description Related Assembly Operations: Syntax call <address> return Allowed values arguments <address>: 0-31 0x0-0x1f label arguments table Reconfigurable Arithmetic Datapath
Index Registers
Register controls five index registers which used data memory address generation. index register holds 1-port memory address. other four index registers hold 3-port memory address information. During Power Reset active configuration component RAD5A4, index register bits reset `0's. control states, Run, Continue, SetSequence0 SetSequence2 affect index registers. During each clock cycle that memory access performed, that memory address loaded, incremented, decremented held depending upon control settings each index register. Related Assembly Operations: Syntax Allowed values arguments
setindex <value> <value>: 0-31 0x0-0x1f setindex <valuew>, <value1>, <value2> <valuew>: 0-15 0x0-0xf <value1>: 0-15 0x0-0xf <value2>: 0-15 0x0-0xf indexmode <m0>, <mw>, <m1>, <m2> <m0>: none, reset <mw>: none, resetoffset, resetall <m1>: none, reset, align <m2>: none reset, align indexdirect <d0>, <dw>, <d1>, <d2> <d0>: none, inc, <index> <dw>: none, inc, dec, <d1>: none, inc, dec, <d2>: none, inc, dec, <index>: readwrite0, write, read1, read2, all3port table
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Index Register Components
Each index register contains address register control register that provide: Index Control bits which include: index direction bits load enable Index memory address bits where: 1-port Index address five bits. 3-port Read1 Index address four bits. 3-port Read2 Index address four bits. 3-port Write Offset address four bits. 3-port Write Index address four bits. 3-port read index control registers also contain load-write-offset (ldwo) bit, which enables loading from write offset register. index direction assembly language increment (count_up=1 count_down=0), decrement (count_up=0 count_down=1), hold value (count_up=0 count_down=0). effects control bits address bits software listed this table: Index Control Bits Count_ Count_ down Load Enable (lden) Load Write Offset (ldwo)
Effect
1-port Index allows value loaded into address[4:0] value address[4:0] held post-decrements address[4:0] post-increments address[4:0]
3-port Read1 Read2 Index, 3-port Write Offset, 3-port Write Index allows value loaded into address[3:0] value address[3:0] held post-decrements address[3:0] post-increments address[3:0] Address value Write Index address less Write Offset address
table
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath Index Register bits shown this table: Index Register Description 1-port Index 3-port Read1 Index 3-port Read2 Index 3-port Write Offset 3-port Write Index Name I3pR1 I3pR2 I3pWO I3pW count_ Control Register Bits count_ down Load Enable (lden) Load Write Offset (ldwo) Address Register Bits adr[4:0] adr[3:0] adr[3:0] adr[3:0] adr[3:0]
table
MacroSequencer Configuration Bits
each MacroSequencer there nine programmable configuration bits. They listed table below. three signed/unsigned bits with directives when programming MacroSequencer. other selections made RADware design tools. MacroSequencer Configuration Bits Functional Block Multiplier Multiplier Adder Adder Data Connections Function Mult operand sign Mult operand sign Signed Unsigned 32/16 Select OutRegA MSnI/O pins MacroSequencer busn inputs Control[1:0] source select Output Enable Select unsigned. unsigned. Unsigned Datapath mode Busn inputs from OutRegA MacroSequencer(n) Control[1:0] from MSnCTRL[1:0] pins signed. signed. Signed Datapath mode Busn inputs from MSnI/O pins
Datapath Controller Interface
Control[1:0] from PLA0 CtrlPLAn[1:0]
[00]: from MSnOE [01]: from [1x]:
Interface
Polarity Select
logical one, logical zero
table configuration bits configured with instruction memory, where bits through 16-bit program data word nine configuration bits listed above. They placed automatically RADware design tools.
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
RAD5A4 Dual Description
RAD5A4 Dual contains in-circuit programmable, input product term PLAs. PLA0 serve state machine coordinate MacroSequencer array operation with external devices. PLA1 used random interface logic. Dual perform peripheral logic control functions based upon state BUS4IN, PLAIN PLAI/O states Control bus.
Dual Block Diagram
PLA0
Input Selector
Array
Control Registers
Minterm Generater
Fixed
Control
BUS4IN[15:0] Send Status Await Status PLAIN[7:0] PLAI/O[7:0]
(Inputs)
oepla[1] oepla[3] PLACtrl0[1:0] PLACtrl1[1:0] PLACtrl2[1:0] PLACtrl3[1:0]
CtrlReg OutReg
Output Registers
Minterm Generater
PLAI/O Buffers
Fixed
Output
Input Selector
Array
OutCom
PLAI/O[7:0]
(Outputs)
oepla[0] oepla[2]
Register
PLA1
figure
Dual control functions which used MacroSequencers include: Registered control outputs, CtrlReg[7:0], for: Initiation sequences Control response Send Await status signals. Combinatorial outputs, oepla[3:0], used generate Output Enable signals MacroSequencers. oepla[3:0] signals generated from individual product terms.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath CtrlReg[7:0] signals used pairs each MacroSequencers where: CtrlReg[1:0] available Control0[1:0] MacroSequencer0. CtrlReg[3:2] available Control1[1:0] MacroSequencer1. CtrlReg[5:4] available Control2[1:0] MacroSequencer2. CtrlReg[7:6] available Control3[1:0] MacroSequencer3.
RAD5A4 Dual MacroSequencers should programmed power dynamically reconfigured time during operation. Active Configuration RAD5A4 forces registers every component RAD5A4, including Dual output control registers initialized.
Outputs
PLA0 produces eight CtrlReg outputs that used MacroSequencer control signals where signals available each MacroSequencer Control signals. They also available feedbacks both PLA0 PLA1. CtrlReg[7:0] signals useful multi-chip array processor applications where system control signals transmitted each RAD5A4. PLA1 produces combinatorial registered outputs PLAI/O[7:0] pins. fourteen Fixed outputs(FO1) from PLA1 also available Control array PLA0. PLA1 registers available feedback both Input Selectors. PLAI/O signals useful single chip applications requiring interface/handshake signals, they useful multi-chip array processor applications where system control signals transmitted each device.
Components
PLA0 consists Input Selector Minterm Generator Array0 product terms inputs Array0 Fixed array (Fixed OR0) Programmable array (Control registers (Control Register)
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RAD5A4
Reconfigurable Arithmetic Datapath PLA1 consists Input Selectors Minterm Generator Array1 product terms inputs Array1 Fixed nodes with product terms node (Fixed OR1) Programmable array (Output registers (Output Registers) Choice registers combinatorial outputs (PLAI/O Buffers) Architecture Description
Each element RAD5A4 Dual described detail.
Input Selectors
Input Selectors PLA0 PLA1 identical accept inputs from: Send Await status signals from each MacroSequencer which synchronized registered Input Selector circuits. BUS4IN[15:0] input pins, PLAI/O[7:0] pins, PLAIN[7:0] pins, CtrlReg[7:0] registered signals from PLA0, OutReg[7:0] registered signals from PLA1.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath There groups generated signals A[15:0] B[15:0] which output Input Selector circuit.
Input Selector
CtrlReg[6,4,2,0] OutReg[6,4,2,0]
A[3:0]
CtrlReg[7,5,3,1] OutReg[7,5,3,1]
Configuration (CtrlReg OutReg)
B[3:0]
PLAI/O[6,4,2,0] Await[3:0] PLACLK
A[7:4]
PLAI/O[7,5,3,1] Send[3:0]
Configuration (PLAI/O Await Send)
B[7:4]
BUS4IN[6,4,2,0] BUS4IN[7,5,3,1] PLAIN[6,4,2,0] PLAIN[7,5,3,1]
A[11:8] B[11:8] A[15:12] B[15:12]
Register
figure Configuration bits within RADware design tools when Dual programmed.
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Minterm Generator
Minterm generator provides sets four minterms adjacent numbered inputs (A[i] B[i]) from Input Selectors planes. There 16-bit parallel inputs Minterm Generator known A[15:0] B[15:0]. Adjacent inputs, A[i] B[i], paired generate four possible minterms array. Instead routing conventional inverted non-inverted input signals array, four minterms inputs routed. number lines through array number memory signals array four inputs each product term which same conventional array. From each input pair, A[i] B[i], minterms generated inputs array. A[i] B[i] A[i] B[i] A[i] B[i] A[i] B[i]
Each pair inputs Minterm generator, A[i] B[i], generate following minterm signals i=0, mt[4*i] A[i] B[i] mt[4*i+1] A[i] B[i] mt[4*i+2] A[i] B[i] mt[4*i+3] A[i] B[i]
minterm results, mt[63:0] available planes.
Arrays
Each generates product terms inputs arranged pairs (A[i], B[i]) signals. array inputs from Minterm Generator. Minterm Generator translates pairs A[i] B[i] signals into groups four minterms labeled mt[4i+3:4i]. These minterm signals then transmitted each product terms within array.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath Each product term consists function generators which four minterm signals generate function A[i] B[i] signals. function generator outputs, f(0) f(15) inputs 16-input gate. Each 16-input gate outputs product term signals.
Product Terms
mt[3:0] Function Generator f(0) mt[7:4] Function Generator f(1) mt[63:60] Function Generator f(15)
16-input Gate
figure
Array Function Generator
Configuration four configuration bits, within each function generator determines functions each A[i], B[i] input pair product terms. relation between configuration bits, input pairs AND-gate inputs shown this diagram:
Function Generator
Array Inputs
figure
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description Memory selections sixteen possible input functions shown this truth table: constant function xnor constant function table Resulting Function
Bolded functions normally available structures. function generators allow these extra functions. logic formula product term PT[i] PT[i] f[i,0] f[i,1] f[i,2] f[i,3] f[i,4] f[i,5] f[i,6] f[i,7] f[i,8] f[i,9] f[i,10] f[i,11] f[i,12] f[i,13] f[i,14] f[i,15] where f[i,j] represents generated function signal PT[i] input pair A[j], B[j].
Example
RAD5A4 minterm generator enhanced product term allow single product cover same Boolean function that several conventional product terms would require. Consider comparison: A[7:0] B[7:0] between 8-bit vectors This equation requires conventional product terms; with RAD5A4 will exactly one. This accomplished implementing !(A0 !(A7 directly.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
Fixed Arrays
Fixed
Array outputs summed sets four successive signals form eight 4-product term signals FO0[7:0] shown here:
Fixed
Fixed
figure where eight Fixed outputs shown here:
Fixed
Fixed Outputs
figure
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Fixed
Array outputs summed sets one, four successive signals form fourteen, fixed term signals FO1[13:0]. Array outputs summed follows: sets four array sets array outputs sets single array outputs
Fixed
Fixed
figure detailed product terms shown this diagram.
Fixed
PT10 PT11 PT12 Array PT13 Outputs PT14 PT16 PT17 PT18 PT19 PT20 PT21 PT22 PT23 PT24 PT25 PT26 PT27 PT28 PT29 PT30 PT31
Fixed Outputs
figure
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
Control Array
Control array programmable array with inputs that produce eight registered Control Register form MacroSequencer Control signals which available inputs Input Selector. inputs Control array include FO0[7:0] FO1[13:0].
Control
ARRAY
FO0[7]
ARRAY
FO1[13] [12] [11] [10] C0[0]
figure vertical lines above diagram represent programmable gate, horizontal lines represent fixed gates. boxes intersections show which fixed terms ORed together.
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description Each gate input determined configuration bits shown this schematic:
Control Simplified Schematic
s0,j
s1,j
C0[i] 16-input Gate
s16,j
figure formula each Control output, C0[i] C0[i] FO1[0] s[0,i] FO1[1] s[1,i] FO1[2] s[2,i] FO1[3] s[3,i] FO1[4] s[4,i] FO1[5] s[5,i] FO1[6] s[6,i] FO1[7] s[7,i] FO1[8] s[8,i] FO1[9] s[9,i] FO1[10] s[10,i] FO1[11] s[11,i] FO1[12] s[12,i] FO1[13] s[13,i] FO0[j+2] s[14,j+2] FO0[j] s[15,j]
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
CtrlReg Register
CtrlReg Registers hold MacroSequencer Control signals produced Control array.
CtrlReg Register
CtrlReg
CtrlReg
Register
PLACLK
figure
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Output Array
Output array programmable array with fourteen inputs from Fixed array producing eight combinatorial OutCom[7:0] signals which registered. Output Registers available inputs Input Selector. Both combinatorial outputs registered Outputs available PLAI/O Buffers. inputs Output array Fixed signals which labeled FO1. PLA1 fixed terms available every programmable term.
Output FO1[13] [12] [11] [10] C1[0]
figure vertical lines above diagram represent programmable gate, horizontal lines represent fixed gates. boxes intersections show which fixed terms ORed together.
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RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath Each gate input determined configuration bits shown this schematic:
Output Simplified Schematic
s0,j
s1,j
C1[i] 14-input Gate
s16,j
figure formula each Output output, C1[i] C1[i] FO1[0] s[0,i] FO1[1] s[1,i] FO1[2] s[2,i] FO1[3] s[3,i] FO1[4] s[4,i] FO1[5] s[5,i] FO1[6] s[6,i] FO1[7] s[7,i] FO1[8] s[8,i] FO1[9] s[9,i] FO1[10] s[10,i] FO1[11] s[11,i] FO1[12] s[12,i] FO1[13] s[13,i]
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RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Output Register
eight Output Registers used holding signals produced Output array. registered signals, OutReg[7:0], available Input Selectors both PLA0 PLA1.
OutReg Register
OutReg
OutReg
PLACLK
Register
figure
PLAI/O Buffers
eight buffers select either combinatorial outputs registered outputs from Output array PLAI/O pins. simple schematic buffer shown here:
PLAI/O Buffers
Registered OutReg Combinatorial OutCom
PLAI/O Output
Config. Bits
figure Exactly configuration controls whether combinatorial registered outputs selected eight PLAI/O pins. configuration each determines whether each PLAI/O always output always input.
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RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
RAD5A4 Configuration
This chapter offers directions RAD5A4 device configuration thirteen memories RAD5A4 that programmed. RAD5A4 configured loading configuration file into device.
RAD5A4 Configurable Memories
There three memories each four MacroSequencers Dual configuration memory. Within each MacroSequencers, there MacroSequencer configuration memory, 1-port data memory, 3-port data memory. MacroSequencer memory nine programmable configuration bits supplied together MacroSequencer configuration memory data packet. MacroSequencer configuration memory Dual configuration memory only written during Active Configuration Mode. 1-port 3-port data memories each MacroSequencer loaded during Active Configuration accessed during Normal Operating Mode directed each MacroSequencer's Register.
RAD5A4 Operating Modes
configuration file loaded into RAD5A4 during Active Configuration Mode. RAD5A4 three operating modes depending logic states PGM0 PGM1: Normal Operation Mode, RAD5A4 MacroSequencers concurrently execute LIWs, Dual operational. Active Configuration Mode allows each MacroSequencer's configuration memory data memories Dual configuration memory configured. Passive Configuration Mode disables device outputs. This allows other RAD5A4s sharing same circuitry configured individually. Four configuration pins, named PGM0, PGM1, PRDY, PACK, used control operating mode configuration process. PGM0 PGM1 control device operating mode. PRDY PACK provide positive handshake interface between internal RAD5A4 circuitry external circuitry configuring device. BUS4IN[15:0] pins used input configuration data words.
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RAD5A4
Reconfigurable Arithmetic Datapath This chapter includes following: Configuration control descriptions Description Configuration Modes Configuration with positive handshaking signals Minimizing Configuration Time Configuration without handshaking Time Configure RAD5A4 Multiple RAD5A4 Configuration RAD5A4 Configuration
Throughout this chapter term used logic level `0'. term HIGH used indicate logic level `1'. indicates `don't care' which should either logical `1'. symbol indicates rising edge signal, symbol indicates falling edge signal.
Configuration Control Description
Symbol: Pins Number Type Function: PGM0 Input Configuration Mode0 PGM1 Input Configuration Mode1 table PRDY Input Configuration Ready PACK Output Configuration Acknowledge
PGM0 PGM1: Configuration Mode Pins
PGM0 PGM1 pins used inputs determine operating mode RAD5A4. They functionally identical. When both pins HIGH, RAD5A4 Active Configuration Mode. this mode, outputs high-impedance state, most internal registers flip-flops MacroSequencers Dual held initialized state. PACK enabled output indicate when device configured. When they both LOW, device Normal Operating Mode, pins under control MacroSequencers Dual PLA, PACK high-impedance state. configuration device occur. When HIGH (either one), device Passive Configuration Mode, outputs PACK output highimpedance state. configuration device occur.
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RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
PRDY: Configuration Ready
During Active Configuration Mode, external circuitry uses PRDY input communicate device load configuration data word present BUS4IN[15:0] into device. PRDY used query RAD5A4 ready next configuration data word.
PACK: Configuration Acknowledge
During Active Configuration Mode, PACK used RAD5A4 indicate when configuration data word been accepted PACK used indicate when data word will accepted.
PLACLK: Configuration Clock Signal
During Active Configuration Mode, PLACLK should connected freerunning clock signal defined Electrical Specifications. RAD5A4 configuration circuitry rising edge triggered this clock pulse.
RAD5A4 Configuration Modes
Normal Operating Mode: PGM0 PGM1
Normal Operating Mode occurs when PGM0 PGM1 maintained LOW. This prevents configuration from occurring, device pins will remain active under control MacroSequencers Dual PLA. PACK will remain high-impedance state. PGM0 PGM1 asynchronous inputs must maintained their logic states prevent undesired device operation. PRDY should known state minimize power dissipation.
Passive Configuration Mode: PGM0 PGM1 HIGH, other
Passive Configuration Mode occurs when PGM0 PGM1 HIGH other LOW. When least PGM0 PGM1 HIGH, outputs high-impedence state. Configuration will occur Passive Configuration Mode Normal Operating Mode. Passive Configuration Mode allows RAD5A4 devices common configured time without affecting I/Os other RAD5A4 devices system.
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RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
Active Configuration Mode: PGM0 PGM1 HIGH.
Only during Active Configuration Mode configuration file loaded into RAD5A4 device. Active Configuration, PLACLK, PGM0, PGM1, PRDY, PACK, BUS4IN[15:0] used follows: PLACLK should connected free running clock signal. PGM0 PGM1 must held HIGH active RAD5A4 Configuration. BUS4IN[15:0] used configuration data word input. PRDY input PACK output work together provide positive handshaking signals.
When both PGM0 PGM1 HIGH, MacroSequencer Dual registers flip-flops held initialized state. Once PGM0 PGM1 HIGH, device Active Configuration Mode, they must remain HIGH until Configuration Halt state. them goes LOW, device will transition Active Configuration Mode resulting configuration circuitry internal registers, counters, flipflops resetting initialized state.
Configuring RAD5A4 Device
RAD5A4 configured loading configuration file which generated RADware design tools. configuration file divided into 16-bit configuration data words labeled `DWn' where represents data word being loaded. preamble represented DWP. represents first configuration data word, DWmax represents last configuration data word. Each memory type requires different number configuration data words. example, data words required load MacroSequencer configuration memory. instruction memory requires configuration data words (DW0 DW95). MacroSequencer configuration bits loaded using additional data word (DW96). more data words (DW97 DW98) contain reserved bits that complete MacroSequencer configuration memory data packet.
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RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath When loading configuration data words into memory, necessary load data words fill that memory. Configurable RAD5A4 Memories MacroSequencer configuration memory MacroSequencer 1-port memory MacroSequencer 3-port memory Dual configuration memory table Number Data Words Load into Memory DWmax DW98 DW31 DW15 DW299
About Configuration File
information needed configure RAD5A4 prepared configuration file software tools. Some information about configuration file also been included reference purposes: configuration file consists configuration data packets each RAD5A4 memory programmed. Each configuration data packet consists 16-bit preamble data word that indicates which memory programmed followed data loaded into memory. configuration file loaded onto RAD5A4 using 16-bit configuration data words (DWn).
Configuration with Positive Handshaking Signals
RAD5A4 been designed configuration occur with positive handshaking signals using PRDY input PACK output. This pattern between PRDY PACK repeated from Configuration Initialization Configuration Halt: PRDY input query RAD5A4 will accept data. PACK output advise that device ready receive data. PRDY input indicate when data present pins BUS4IN[15:0] ready loaded. PACK output used advise when data accepted device. PRDY should changed until PACK changed same state PRDY. RAD5A4 supports synchronous asynchronous protocols. Changes state PRDY, PGM0 PGM1 will detected RAD5A4. When configuration complete, PACK will remain HIGH indefinitely indicating that device will accept more configuration data. device taken Active Configuration Mode taking PGM0 and/or PGM1 LOW.
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RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
Configuration Timing
When loading configuration data words, PACK output will second PLACLK after PRDY goes LOW, PACK will HIGH second PLACLK pulse after PRDY goes HIGH. shortest time load configuration data word four PLACLK cycles unless these four conditions occur that require additional PLACLK cycles: Configuration Initialization. Additional PLACLK pulses required. Configuration Continue. Additional PLACLK pulses required. Configuration Halt. PACK will LOW. Invalid preamble. PACK will LOW.
following diagrams depict relationship between PRDY PACK Active Configuration Mode. PGM0 PGM1 pins referenced PGM_a PGM_b because either changed first, they changed same time. PLACLK pulse timing with respect rising edge clock pulse (l). Active Configuration begins when PGM0 PGM1 HIGH (tB).
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RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath timing diagrams that follow depict typical configuration cycle timing separated into four areas operation: Initial portion, Mid-Cycle portion, Continue portion, Halt portion.
Configuration Cycle Timing RAD5A4 Initial Portion
BUS4IN[15:0] Inputs
PLACLK Input PRDY Input PACK Output PGM_b Input PGM_a Input Outputs
Hi-Z
Hi-Z
figure
Configuration Cycle Timing RAD5A4 Mid-Cycle Portion
BUS4IN[15:0] Inputs
DWn+1
PLACLK Input PRDY Input PACK Output
figure
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RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
Configuration Cycle Timing RAD5A4 Continue Portion
BUS4IN[15:0] Inputs
DWmax-1 DWmax
PLACLK Input PRDY Input PACK Output
figure
Configuration Cycle Timing RAD5A4 Halt Portion
BUS4IN[15:0] Inputs
DWmax-1 DWmax
PLACLK Input PRDY Input PACK Output PGM_b Input PGM_a Input Outputs
Hi-Z Hi-Z
figure Between time Initial portion time Halt portion, states PGM_a, PGM_b, outputs remain constant, shown Mid-Cycle portion Continue portion. These four timing figures (figures illustrate RAD5A4 configuration timing operation using example PRDY response time after PACK transitions. this example, positive handshake exists between PRDY signal from external circuitry PACK acknowledge signal from RAD5A4. PRDY asynchronous input signal that changed between first second PLACLK rising edge after PACK transitions.
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RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
Configuration Initialization
Configuration initialization begins upon entry into Active Configuration Mode when second PGM0 PGM1 HIGH (tB) ends when PACK goes first time (tD). PACK goes from high-impedence state HIGH beginning Configuration Initialization (tB) remains HIGH during Configuration Initialization. Configuration Initialization represented time between timing diagrams configuration summary table, represented time Time Configure RAD5A4 discussions. During Configuration Initialization, PACK output remains HIGH minimum four PLACLK rising edges after second PGM0 PGM1 asserted HIGH time PRDY asserted during before Configuration Initialization. time when PACK goes dependent when PRDY LOW. PRDY before third PLACLK pulse after PACK goes HIGH (l), then PACK will fourth PLACLK after PACK goes HIGH (l). This quickest method. PRDY after second PLACLK pulse after PACK goes HIGH (l), then PACK will second PLACLK pulse after PRDY (h). When PACK goes (tD) Configuration Initialization, device will ready accept data input BUS4IN[15:0]. preamble, DWP, should present BUS4IN[15:0] before PRDY HIGH time
Configuration Continue
Either Configuration Continue Configuration Halt occurs each data packet. from each preamble (DWP:b7) specifies whether accompanying data packet last another data packet follows continue configuration. When Configuration Continue occurs, PACK output remains HIGH minimum PLACLK periods after receiving last data word, DWmax, time time when PACK goes dependent when PRDY LOW. PRDY before fifth PLACLK pulse after PACK goes HIGH (l), then PACK will sixth PLACLK after PACK goes HIGH (l). This quickest method. PRDY after fourth PLACLK pulse after PACK goes HIGH (l), then PACK will second PLACLK pulse after PRDY (h). preamble, DWP, next data packet placed BUS4IN[15:0] preparation configuration next memory after PACK goes accept DWmax.
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RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration When PACK goes (tX), configuration continue. PACK remains HIGH time then Configuration Halt indicated.
Configuration Halt
Configuration Halt occurs when data packets configuration file have been loaded. halted state, PACK remains HIGH after time regardless when PRDY until Active Configuration Mode been terminated setting PGM0 and/or PGM1 LOW. only time device should enter Configuration Halt state when configuration file completely loaded. Timing Configuration Halt same timing Configuration Continue. Configuration Halt differentiated from Configuration Continue logic state PACK after time device should always Configuration Halt before transitioning PGM0 PGM1 LOW. During Active Configuration termination, when first pins PGM0 PGM1 (tY), PACK output will highimpedance state. When second pins PGM0 PGM1 LOW(tZ), outputs will become active under control MacroSequencers Dual PLA. PGM0 PGM1 referenced PGM_a PGM_b because either first, they same time.
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RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
Invalid Preamble (DWP)
bits through zero preamble (DWP b6:b0) allowed option, preamble considered valid, additional data words loaded. preamble valid, PACK will PLACLK pulses after PRDY (tI) shown figure Otherwise, preamble invalid, PACK will remain HIGH until Active Configuration terminated shown time figure PACK will remain HIGH until Active Configuration Mode terminated.
Configuration Cycle Timing RAD5A4 with Invalid Preamble
BUS4IN[15:0] Inputs
PLACLK Input PRDY Input PACK Output PGM_b Input PGM_a Input Outputs
Hi-Z
Hi-Z
figure RADware software automatically generates correct preamble each memory configured configuration file; therefore, device should enter invalid preamble state unless caused other factors.
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RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
Configuration Summary
following configuration table summary detailed configuration steps described this chapter. number PLACLK pulses between signal changes indicated. time (t_) refers times shown Configuration timing diagrams, figures Configuration Pins Inputs Step PGM_a PGM_b Normal Operation Mode Hi-Z Active pins operational under control Dual MacroSequencers. PRDY BUS4IN Outputs PACK I/Os Operation Description
Time
Passive Configuration Mode Hi-Z Hi-Z Passive Configuration
Active Configuration Mode Initialization Hi-Z both PGM0 PGM1 High begin Active Configuration. PRDY LOW, already LOW. Configuration Initialization complete
Hi-Z Hi-Z
Load Preamble Hi-Z Place preamble pins BUS4IN[15:0] already loaded. PRDY HIGH tell device that ready. PACK acknowledges that preamble received. Take PRDY query RAD5A4 will accept data. When Preamble valid, PACK will LOW. step
Hi-Z Hi-Z Hi-Z
Hi-Z
table
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RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
Configuration Pins Inputs Step PGM_a PGM_b PRDY BUS4IN Outputs PACK I/Os Operation Description
Time
Load 0,1,2, max-1) Hi-Z Hi-Z Hi-Z Hi-Z Place next data BUS4IN[15:0]. PRDY HIGH advise that next data present. PACK acknowledges data received. Take PRDY query RAD5A4 will accept data. PACK goes acknowledge that next data will accepted. Repeat steps until DWmax.
Hi-Z
Load DWmax DWmax Hi-Z Place DWmax configuration data word BUS4IN[15:0] PRDY HIGH advise that DWmax present. PACK acknowledges DWmax data received. Take PRDY query RAD5A4 will accept data.
DWmax DWmax
Hi-Z Hi-Z Hi-Z
Continue Active Configuration Hi-Z PACK goes LOW, next data will accepted. Continue configuration another memory with step
table
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RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
Configuration Pins Inputs Step PGM_a PGM_b PRDY BUS4IN Outputs PACK I/Os Operation Description
Time
Halt Active Configuration Hi-Z Hi-Z Hi-Z PACK remains HIGH, configuration halted. terminate active Configuration, take PGM0 PGM1 LOW.
Passive Configuration Mode Hi-Z Hi-Z Passive Configuration
Normal Operation Mode Hi-Z table Active Normal operation.
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March 1997
RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
Minimizing Configuration Time
shortest configuration cycle four PLACLK pulses data word Mid-Cycle portion Active Configuration. number PLACLK pulses required load each data word dependent upon soon PRDY input changes state after PACK output changes state. timing examples shown earlier this chapter illustrate changes PRDY between rising edges first second PLACLK pulses after PACK output transitions. This results PLACLK pulses each data word Mid-Cycle portion Active Configuration. achieve fastest configuration operations with without handshaking, PRDY must transition before first PLACLK rising edge after PACK output transitions. PRDY taken before next PLACLK pulse after PACK goes HIGH, PRDY taken HIGH before next PLACLK pulse after PACK goes LOW. timing diagram showing minimum four clock cycles configuration data word shown here. This diagram illustrates asynchronous configuration with handshaking. BUS4IN[15:0] data valid whenever PRDY HIGH.
Configuration Cycle Timing RAD5A4 Mid-Cycle Portion
BUS4IN[15:0] Inputs
DWn+1
DWn+2
PLACLK Input PRDY Input PACK Output
figure
Setup Hold Timing
setup hold timing requirements PRDY BUS4IN[15:0] inputs with respect PLACLK input signal correctly load configuration data shown figure During Active Configuration Mode, PRDY transition received RAD5A4 first PLACLK after PRDY transition satisfies actual setup time. asynchronous PRDY signals, PRDY transition that does meet actual setup time first PLACLK will received next PLACLK (l). Synchronous PRDY inputs must satisfy
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration minimum setup time (tSU) specified Electrical Specifications received RAD5A4 desired PLACLK rising edge. configuration circuitry been designed that data BUS4IN[15:0] received RAD5A4 PLACLK after PRDY input received device. This allows BUS4IN[15:0] data change same time with PRDY provides defined maximum allowed skew (tSKEW(max)) between PRDY input input data BUS4IN[15:0]. parameter tSKEW(max) calculated follows: tSKEW(max) PLACLK period (PRDY) (BUS4IN[15:0]) where: PLACLK period (PRDY)
period PLACLK signal minimum setup time PRDY specified Electrical Specifications, Active Configuration (BUS4IN[15:0]) minimum setup time BUS4IN[15:0] specified Electrical Specifications, Active Configuration When using asynchronous configuration, BUS4IN[15:0] transitions should occur later than PRDY assure correct configuration. Asynchronous configuration should positive handshaking. When using synchronous configuration, PRDY BUS4IN[15:0] transitions must satisfy setup hold time requirements Electrical Specifications appropriate PLACLK shown figure Synchronous configuration used with without handshaking provided proper timing implemented.
Detailed Configuration Cycle Timing RAD5A4 Mid-Cycle Portion
BUS4IN[15:0] Inputs
PRDY Input
PLACLK Input
PACK Output
figure
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
Configuration without Handshaking
possible configure RAD5A4 without using PACK output signals. This requires understanding number PLACLK signals required receive load data into memory. speed configuration, PRDY input from external circuitry change state synchronously same PLACLK PACK changes anticipation PACK transitioning. PRDY signal must change state until after minimum specified hold time (tH) following PLACLK been satisfied. This procedure used minimize configuration time when executing high PLACLK frequency eliminating effects PACK output delay time, system response time, PRDY setup time when using handshaking protocol. timing diagrams figures illustrate example synchronous system where PRDY BUS4IN[15:0] inputs from external registers that clocked appropriate PLACLK edge. minimum number PLACLK pulses synchronous configuration illustrated these figures between time time This example uses PLACLK pulse between transitions PGM_a PGM_b inputs both Initial portion (figure Halt portion (figure configuration cycle.
Synchronous Configuration Cycle Timing RAD5A4 Initial Portion
BUS4IN[15:0] Inputs
PLACLK Input PRDY Input PACK Output PGM_b Input PGM_a Input Outputs
Hi-Z
Hi-Z
figure
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
Synchronous Configuration Cycle Timing RAD5A4 Mid-Cycle Portion
BUS4IN[15:0] Inputs
DWn+1 DWn+2
PLACLK Input
PRDY Input PACK Output
figure
Synchronous Configuration Cycle Timing RAD5A4 Continue Portion
BUS4IN[15:0] Inputs
DWmax
PLACLK Input PRDY Input PACK Output
figure
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
Synchronous Configuration Cycle Timing RAD5A4 Halt Portion
BUS4IN[15:0] Inputs
DWmax
PLACLK Input
PRDY Input PACK Output PGM_b Input
Hi-Z
PGM_a Input Outputs
Hi-Z
figure
PRDY initially HIGH (tC) same time PGM_b HIGH (tB) start Active Configuration shown figure PGM_b (tY) same time that occurs Active Configuration shown figure PACK output transition occurs second PLACLK after PRDY changes state except figure time figures where additional PLACLK pulses required.
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
Time Configure RAD5A4
RAD5A4 devices completely reconfigured less than 150µs. exact time required configure RAD5A4 device dependent upon: Number PLACLK pulses configuration memory which determined size memory PRDY response time after PACK changes, many memories programmed, PLACLK rate. discussion each these factors follows with tables example choices.
PLACLK Pulses Memory Configured
number PLACLK Pulses each configuration memory dependent upon PRDY response time after PACK changes. minimize configuration time, PRDY changed before rising edge first PLACLK pulse following change PACK shown figure However, some systems require more time before PRDY changed. example used figures shows PRDY changing asynchronously between rising edges first second PLACLK pulses following change PACK. This table shows number complete PLACLK pulses required configure each type RAD5A4 memory using several different PLACLK delays (tDPR). time required Configuration Initialization Configuration Continue Halt shown separately because they independent type memory being configured. PLACLK Pulses Configuration Type Memory MacroSequencer Memories
During PLACLK pulse after PACK changes PRDY Delay Config. Memory (TDW=100) 1-port Memory (TDW=33) 3-port Memory (TDW=17) Dual Config. (TDW=301) Initialization Config. Memory Config. Continue Halt
tDPR first second third fourth fifth sixth seventh eighth
1194 1393 1592 1791
table
1202 1803 2404 3005 3606 4207 4808 5409
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
Reading PLACLK Pulses Configuration Table
total number data words each type memory includes preamble data word.
During PLACLK pulse PRDY Delay (tDPR)
tDPR number PLACLK rising edges between change PACK PRDY response. example, when PRDY changes before rising edge first PLACLK pulse following change PACK, PRDY Delay (tDPR PRDY changes between rising edges first second PLACLK following change PACK, then PRDY delay (tDPR example illustrated figures uses tDPR example illustrated figures uses tDPR
number PLACLK pulses load memory including extra clock pulses required Configuration Continue Configuration Halt. example timing diagrams shown this chapter, time from tDPR)*(2
Configuration Initialization Time
number PLACLK periods Configuration Initialization including full PLACLK period which second pins taken HIGH. example timing diagrams shown this chapter, time from tDPR) tDPR tDPR (minimum time) timing diagrams shown this chapter, time tDPR.
Configuration Continue Halt Time
number PLACLK pulses Configuration Continue Halt. example timing diagrams shown this chapter, time from tDPR) tDPR tDPR (minimum time)
March 1997
Infinite Technology Corporation Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
PLACLK Pulses Device Configuration
PLACLK Pulses Configuration Single Memory Configuration Dual MacroSequencer Memories
Config. During Memory PLACLK pulse PRDY Delay after PACK (TDW=100) changes 1-port Memory (TDW=33) 3-port Memory (TDW=17) Config. Memory (TDW=301)
Multiple Memories
MacroSequencer memories) RAD5A4 memories)
first second third fourth fifth sixth seventh eighth
tDPR
1006 1206 1407 1608 1809
table
1213 1814 2415 3016 3618 4221 4824 5427
1121 1508 1806 2107 2408 2709
3661 5450 7239 9028 10818 12621 14424 16227
Time from Configuration Initialization Halt
number PLACLK pulses device configuration. includes number PLACLK pulses for: Configuration Initialization, Each configured memory, Applicable Configuration Continues, Configuration Halt
example timing diagrams shown this chapter, time from Configuration Halt. (for each memory) (tVX configured memories)
Infinite Technology Corporation Phone: 972-437-7800
March 1997
RAD5A4
RAD5A4 Configuration Reconfigurable Arithmetic Datapath
Device Configuration Time
Device configuration time function number PLACLK pulses PLACLK rate.
RAD5A4 Configuration Time memories)
During PLACLK pulse after PACK changes PRDY Delay
PLACLK Input Frequency (MHz)
first second third fourth fifth sixth seventh eighth
tDPR
(µs) 1091 1449 1807 2165 2526 2886 3247
(µs) 1082 1263 1443 1624 table
(µs)
(µs)
(µs)
Time Device Configuration
includes number PLACLK pulses for: Configuratio
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