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Chip Errata 68306 Integrated EC000 Processor January 1999
Contents this document intended only internal Motorola customers designing with this product. mask each part encoded into device topside markings example, following markings would indicate device from 2E94M mask, manufactured 12th week 1993: XC68306FC16 2E94M QEAQ9312 This errata list applies following 68306 mask sets: Rev. Mask 1E94M 2E94M 3E94M 4E94M 0G71K 1G71K 2G71K 3G71K 0J88R Processing Geometry 0.8u 0.8u 0.8u 0.8u 0.65u 0.65u 0.65u 0.65u 0.65u Part Number Suffix (none) (none) (none) (none)
DUART Never-Ending Break
Start Break command written DUART Command Register (either channel), followed Stop Break command same register (same channel), followed some other command same register, then transmit data will (Start Break) then high (Stop Break) then again break issued erroneously when last command written will away.) Workaround: Whenever Start Break Stop Break command issued, follow immediately with Command command (00.) Other commands issued time, even between Start Command/No Command Stop Command/No Command pair. Masks: 1E94M 2E94M 3E94M 4E94M 7/22/93
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
DUART Receive Buffer Data Corrupt
DUART receiver (either channel) operate five bits-per-character mode receiver FIFO full, data read from receiver corrupt. This condition exaggerated temperatures extreme VCC. Workaround: more bits character don't allow receiver FIFO become full. Masks: 1E94M 2E94M 3E94M 4E94M DUART Baud Clock
7/22/94
programmed "RxCB "TxCB (Bits three OPCR respectively), channel baud clock source Timer (RCSx bits 1101 DUCSRx register), then clock signal actually baud rate, Workaround: Compensate device receiving clock, possible. Masks: 1E94M 2E94M 3E94M 4E94M DUART Baud Clock
10/18/93
programmed "RxCB "TxCB (Bits three OPCR respectively), channel baud clock source built-in Baud Rate Generator, then clock signal correct frequency, only 6.25% (1/16) duty cycle, instead 50%. Workaround: Compensate device receiving clock, possible. Masks: 1E94M 2E94M 3E94M 4E94M DUART Transmitter Auto-RTS
10/18/93
transmitter ready-to-send signal (RTS) either channel does function auto-negate mode (Bit five DUMR2 register one.) Workaround: Control manually. Wait Transmitter Empty status before negating (Bit three DUSR register one.) Masks: 1E94M 2E94M 3E94M 4E94M 10/18/93
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
DUART Receiver Auto-RTS
receiver ready-to-send signal (RTS) either channel does function auto-negate mode (Bit seven DUMR1 register one.) Workaround: None. sure check overrun status receivers (Bit four DUSR one.) Masks: 1E94M 2E94M 3E94M 4E94M 10/18/93 DUART Change-Of-State-Detect
IP0, IP1, IP2, high unchanging during after DUART reset, shows change-detect IPCR; they low, there change-detect. Workaround: Clear change-detects reading DUIPCR before enabling change-detect interrupts. Also service existing state appropriate before enabling change-detect interrupts. Masks: 1E94M 2E94M 3E94M 4E94M 10/18/93 DUART Interrupt Acknowledge
next DUART access following read (stop_counter) write (OPCLR) access UART address $FFFFF7FF IACK cycle, stop_counter operation will occur parallel with IACK. Similarly, next DUART access following read (start_counter) write (OPSET) DUART address $FFFFF7FD IACK cycle, start_counter operation will also occur. When timer used periodic interrupt, failure symptom typically spurious interrupt exception following IACK timer interrupt, less frequently incorrect interrupt vector returned IACK. Workaround: Following read start_counter stop_counter, write OPSET OPCLR, immediately read DUISR register. DUART interrupts should masked during this sequence prevent intervening IACK access DUART. Disabling DUART interrupts within serial module sufficient. processor interrupt priority mask must programmed higher than DUART interrupt priority level (DUIPL2-0) selected System Register ($FFFFFFFE.) Masks: 1E94M 2E94M 3E94M 4E94M 10/26/94
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
DUART Receiver Duplicates Characters
DUART receiver FIFO used, data read from receiver duplicated with indication error. Because this problem result asynchronous race condition FIFO, exaggerated temperatures extreme VCC. Workaround: Don't FIFO used. RxRDY instead FFULL indication that DUART requires data read from buffer. Ensure that polling interrupt latency short enough prevent FIFO from being used. Masks: 1E94M 1/22/96 Internal Register Accesses
During accesses internal registers, control signals operate normally. Additionally, data driven read cycles. This could result external data contention with external data buffers Workaround: Avoid external data buffers. external data buffers must used, IACKx signals which used application should ANDed together used data buffer enable signal. Masks: 1E94M 2E94M 3E94M 4E94M 0G71K 1G71K 2G71K 3G71K 0J88R 10/26/94 Electrical Specifications
following electrical specifications have been changed: Clock Input High Voltage (EXTAL,X1) changed from 0.7*VDD 0.8*VDD. Clock Input Leakage Current changed from +/-2.5µA +/-10µA. Output High Voltage (IOH Rated Maximum) changed from VCC-0.75V VCC-0.8V. Workaround: None. Masks: 1E94M 2E94M 3E94M 4E94M 0G71K 1G71K 2G71K 3G71K 0J88R Electrical Specifications
9/7/95
following electrical specifications have been changed: Spec Data-In Valid CLKOUT (Setup Time Read) changed from Spec Asynchronous Input Setup Time changed from Workaround: None. Masks: 1E94M 2E94M 3E94M 4E94M
9/7/95
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
Electrical Specifications
following electrical specifications have been changed 16MHz part: Spec CLKOUT High RASx Asserted (0-Wait-State Operation) changed from Spec CLKOUT High RASx Asserted (1-Wait-State Operation) changed from Spec Column Address Valid CASx Asserted changed from Workaround: None. Masks: 1E94M 2E94M 3E94M 4E94M 0G71K 1G71K 2G71K 3G71K 0J88R IEEE Non-Compliancy JTAG Boundary Scan Register
7/15/96
JTAG boundary scan register cells BERR, DTACK, RESET, HALT conform IEEE 1149.1-1990 specification. accurate BSDL file available, generate errors when processed many BSDL tools. Workaround: None. Masks: 1E94M 2E94M 3E94M 4E94M 0G71K 1G71K 2G71K
3/21/96
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
Mask Adjust Oscillator Capacitor Values
G71K J88R mask sets, on-chip capacitors oscillator have been eliminated, requiring external capacitors proper operation oscillator circuit. diagram below shows oscillator circuit with required external capacitors. chip capacitance values: Mask E94M G71K J88R 17pF
Note: Includes estimated stray capacitance cases.
EXTAL,
XTAL,
MC68306
Workaround: Optimum performance likely achieved with values CEXT CEXT range depending rated load capacitance (CL) particular crystal. necessary experiment with values CEXT CEXT optimize performance. following equation used determine starting value: CEXT CEXT Masks: 0G71K 1G71K 2G71K 3G71K 0J88R 9/26/96
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
Reset Break Change Interrupt Command
There window periods receiver baud clock (16x clock asynchronous mode, clock synchronous mode) after Reset Break Change Interrupt command, during which another RBCI command effect. Therefore, receiver detects start/end break, user issues RBCI, another start/end break occurs within baud clock periods, user issues another RBCI, second change-of-break status cleared. Change-ofBreak Interrupts enabled, this second Change-of-Break could cause reinterrupted many times until baud clock window, when RBCI will finally clear interrupt. Masks: 0G71K 1G71K 2G71K Input High Voltage, Limit Specification 12/30/97
input high-voltage specification, VIH, this mask marginal some operating conditions. electrical specification (min) 2.2V (max) Workaround: Insure that logic devices driving 68306 inputs capable driving inputs required levels that adequate noise margin maintained. Masks: 0G71K 1G71K 2G71K 3G71K 0J88R 12/30/97 Timer/Counter Lockup with clock input DUART timer.
306A sensitivity slow rise fall times input. Noise generated chip sufficient cause false pre-loads counter timer causing either inconsistent time-outs timer lockup. Workaround: rise fall time greater than 10ns should used input. Masks: 0G71K 1G71K 2G71K 3G71K
12/30/97
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
Timer/Counter
Lockup with successive Start commands.
There counter/timer start/stop signal synchronization circuit within DUART counter that potentially lock counter. Once this state, reset (hardware software) required clear locked state. problem occurs when start issued read START COUNTER COMMAND register $FFFFF7FD), followed single DUART clock, then second start issued before next DUART clock. With this sequence events, counter loaded with preload value counter will start without reset reinitialization DUART. Workaround: Ensure that least cycles DUART counter clock between issuing consecutive starts commands. This true with stop commands well. Note that start-then-stop stop-then-start sequence does have this restriction. Masks: 0G71K 1G71K 2G71K 3G71K Reading DUART Mode Register (DUMR2A,DUMR2B). 12/30/97
value written Mode channel (MR2A, MR2B) bits cannot read back. These bits always read back "00". Also, note permanent changes available stop-bit lengths. Masks: 0G71K 1G71K 2G71K DRAM Access Timing Specification Changes 12/30/97
following electrical specifications have been changed 16MHz part: Spec CLKOUT High RASx Asserted (1-Wait-State Operation) changed maximum from 27ns Spec CLKOUT High RASx Asserted (Refresh Cycle, 1-Wait-State Operation) changed maximum from 27ns Note Masks: 0G71K 1G71K 2G71K 3G71K 0J88R 12/30/97
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
Counter/Timer Preload Timing
either Counter/Timer Preload registers (DUCTUR, DUCTLR) written after DUART Counter/Timer Start command, before Counter/Timer clock rising edge, Counter/Timer will count from preload value instead value effect time start command. Workaround: Counter mode: Counter does automatically reload Preload value when preload registers written, another Start command will have issued eventually. Either ensure that least Counter clock rising edge occurs after Start command before modifying Preload register, delay writing Preload register until ready issue another Start command. Timer mode: intent that timer should preload value, another start command will issued, then this likely cause problems. (See there possibility issuing multiple start commands rapid succession.) preload value intended used until timer already counted down first preload value, then ensure that least timer clock rising edge occurs after issuing start command, before modifying preload registers. faster clock source timer, less likely that this timing problem will encountered: timer clock source clock", then premature preload cannot happen. With very slow unpredictable clocks, only know sure that sufficient clocks have occurred wait timer interrupt poll CTRDY Interrupt Status reg, DUISR[3]). course, this means timer already counted down re-loaded first preload value, preload value will used until timer counted down first Preload value second time. short-cut load false value 0000 into preload register, start timer, wait interrupt. interrupt will occur after timer clocks. When interrupt signaled, change Preload register "First_Desired_Timer_Load_Value timer will count more clocks, load modified preload value, issue another interrupt. second subsequent interrupts, load preload register with correct value counted down after current count down complete. Masks: 0G71K 1G71K 2G71K 3G71K 0J88R 2/16/97
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
Notes: DUART Timer Period timer period 68681 (timer_load_value) timer_clock_period. timer period 68306 DUART (timer_load_value timer_clock_period. This chip errata, considered user's manual errata. Workaround: Compensate timer_load_value. DUART timer capable generating frequencies that standalone 68681 timer generate. minimum timer_load_value 68681 two; minimum timer_load_value E94M 68306 DUART one, which creates same frequency. G71K follows DUART timing equation above minimum value (i.e. values from $0000 $FFFF valid with $0000 producing timer period timer_clock_period). Masks: 1E94M 2E94M 3E94M 4E94M 0G71K 1G71K 2G71K 3G71K 0J88R DUART Stop Length Change 10/18/93
68306A G71K mask sets longer support stop lengths 1/16 increments. This will true future masks sets 68306A well Only stop lengths supported: 1.5, When Stop Length code programmed Mode channel (DUMR2A, DUMR2B), select these Stop lengths, bits ignored. MR2A/B encoding follows: Stop Length Async Sync Masks: 0G71K 1G71K 2G71K 3G71K 0J88R DRAM Access Timing Specification Changes 12/30/97
following specifications have been permanently changed follows. Errata errata these specifications. User's manual specification Spec CLKOUT High RASx Asserted (1-Wait-State Operation) maximum Spec CLKOUT High RASx Asserted (Refresh Cycle, 1-Wait-State Operation) maximum Masks: 1E94M 2E94M 3E94M 4E94M 0G71K 1G71K 2G71K 3G71K 0J88R DUART Counter/Timer Start Time Change 12/30/97
DUART counter/timer Start Command timing 68306B 0J88R mask differs from timing E94M mask sets G71K mask sets. When timer start command issued read START COUNTER COMMAND register $FFFFF7FD) DUART counter/timer mask sets E94M G71K will skip clock cycle before counter timing begins. However, DUART counter/timer mask 0J88R will begin timing first clock cycle after timer start command issued. This difference important note customers moving from E94M G71K masks 0J88R mask DUART counter/timer being used counter. this
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:
case, user might want increase their preload value consistent with previous mask functionality. When timer/counter used baud rate generator, this difference will only noticed very first clock cycle timer. Masks: 0J88R 1/15/99
MC68306 MC68306A Errata 12/30/97Copyright 1997 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, Imaging Storage Division, Applications, M.S. OE34, 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 895-7523 Fax: (512) 891-2943 WWW:

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