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Division ADSP-21160N Anomaly List Revision 0.0, December 2003
These anomalies represent currently known differences between revision ADSP-21160N, revision ADSP-21160N, functionality specified ADSP-21160N data sheet ADSP-21160 Hardware Reference Manual (Second Edition). revision number with form x.x" branded parts. Bits 31-25 ADSP-21160N's MODE2_SHDW register used identify specific revisions shown table below: Revision MODE2_SHDW[31-25] 0100100 0101100
Changes from last version this document (August 22nd, 2003): Added statement anomaly four Added Anomaly "Single instruction loops terminate early". Added Anomaly "Bit reversal fails with indirect jump". Added Anomaly "VIPD gets cleared when branching ISR".
Additional Notes: Documentation notes have been removed from anomaly list. Documentation information will located errata appropriate manuals. Tools notes have been removed from anomaly list. Tools information available tools anomaly list.
TABLE CONTENTS
ANOMALY SUMMARY TABLE ANOMALY DESCRIPTIONS
Anomaly Summary RFRAME instruction does function correctly IMASKP bits left shifted writes bits Inactive EPBx channel parameter registers (EIx, EMx, ECx) read incorrectly Direct writes IMASKP LIRPTL cause highest priority interrupt serviced twice
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Key: Asynchronous Host Reads fail tSADRDL less than external clock cycle 32-bit wide link port transfers limited throughput with LCLK-toCCLK ratio Internal memory operation will possible while /TRST active (low) Conditional type instruction fail SIMD SIMD broadcast loads fail type instructions Rn=MANT results will rounded RND32 enabled Illegal stalls occur under certain circumstances Serial Port Multichannel mode, external cycle early causes data corruption Execution instructions that modify interrupt latch registers cause incoming interrupts ignored breakpoint following JUMP, CALL, trigger early/improper emulator break register write followed directly register read fails during context switch System registers written with access have cycle effect latency Conditional fails SIMD mode Single instruction loops terminate early reversal fails with indirect jump VIPD gets cleared when branching anomaly exists revision, anomaly does exist revision, F.I. anomaly implemented tested/verified, Tested revision
ANOMALIES
RFRAME instruction does function correctly RFRAME instruction generated compiler facilitate restoring stack frame pointers when returning from subroutine (function, isr, etc.). special opcode which same functionality "I7=I6, I6=dm(0,I6);". During execution RFRAME, portion instruction executed. will retain previous value contents dm(0,I6) portion opcode executed properly hence previous value lost. RFRAME appear work correctly I7=I6 executed before RFRAME. Work around: RFRAME instruction. This instruction should never used assembly programming general. ADSP-21160 Compiler forced generate RFRAME instruction. Compiler (revision 4.1.2 later) supports switch (21160rev0) which will force compiler generate RFRAME instruction. This Compiler available 4.1.2 upgrade further updates tools.
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RFRAME anomaly correctly addressed VDSP 4.1.2. subsequent defect VisualDSP++ release correctly pass option compiler. first VisualDSP++ Service Pack corrects this. relevant 5976, which notes patch. -21160rev0 switch fails work correctly driver fails pass correct options through VisualDSP++ release. Work around (VisualDSP++ only): When using compiler switch `-21160rev0' with VisualDSP++ 1.0, specify -21160 well command line. example, user should both options together command line: cc21k -21160 -21160rev0
IMASKP bits left shifted writes bits Direct writes core IMASKP[30:14] will result value being stored IMASKP that shifted left bit. When IMASKP updated normal operation (i.e., during interrupt service), correct value will stored read from IMASKP. problem occurs during direct write IMASKP. Setting IMASKP[13:0] will result left shift these bits affected this anomaly. following example illustrates anomalous behavior: IMASKP 0x04000000; write IMASKP register IMASKP; read from IMASKP register will value 0x08000000 Note that LPISUM (bit read only cannot modified, however attempting will result being modified. When executing link port interrupt, correctly indicate that link port interrupt being serviced. IMASKP reserved cannot modified. Work around: order store intended value IMASKP correctly, users must first shift value written IMASKP[31:14] position toward LSB, then this value with lower bits before writing 32-bit value IMASKP. This will result appropriate interrupt bits being set.
Inactive EPBx channel parameter registers (EIx, EMx, ECx) read incorrectly. Active channel parameter registers always read reliably. Reading inactive External Port Buffer channel parameter registers (associated with external address generation circuitry EIx, EMx, ECx) will reveal correct results when there pipeline stall. contents inactive EPBx external channel registers corrupted; read values simply reflect actual contents. EPBx functionality works properly affected this reporting error. pipeline stall occurs when controller unable write peripheral buffer. Typical situations where controller stalls occur when core external accesses
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configured have higher priority than held allow core access compete, when peripheral transmitting data sends data slower rate than controller writes peripheral buffers. active EPBx channel that enabled currently performing internal<-> external memory access, while inactive EPBx channel enabled currently performing access. Workaround: DMASTAT register should used check status external port channel activity channels Code should test status based EPBx channel parameter registers. This reporting error inactive EIx, EMx, channel parameter registers should considered when viewing addressing window debugger interface.
Direct writes IMASKP LIRPTL cause highest priority interrupt serviced twice problem observed when LIRPTL IMASKP register being written simultaneously interrupt servicing starts, irrespective source interrupt generation (Interrupt could caused writing IRPTL, LIRPTL could normal interrupt). beginning interrupt servicing overlaps with execute phase LIRPTL/IMASKP load, problem occurs. This will problem will occur only following conditions met: User performs direct write LIRPTL IMASKP register. interrupt just started servicing. This interrupt could caused direct write IRPTL could normally occurring interrupt.
example, have following instructions condition shown above true: IRPTL 0x7FFFFDFF; LIRPTL 0x003F003F; //user direct write register //user direct write register
Then highest priority interrupt (IICD this example) executed twice, once beginning interrupt servicing once after interrupts serviced. multiple interrupts, which unmasked, latched, processor starts servicing highest priority interrupt then services other interrupts order their priorities. When interrupts serviced, jumps highest priority latched unmasked interrupt services again. Also during this interrupt service IMASKP corresponding this highest priority interrupt set. This behavior does occur when multiple interrupts latched IRPTL without latching interrupt LIRPTL. Also when multiple interrupts latched LIRPTL without latching interrupt IRPTL this behavior will occur. Thus, anomalous behavior will occur with sequence instructions form shown below interrupt just started servicing upon completion instructions (note instruction order) IRPTL
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LIRPTL Furthermore, this anomalous behavior does occur have following instructions interrupt just started servicing upon completion instructions (note change instruction order) LIRPTL IRPTL `bit set' instructions necessary reproduce problem. example, instruction, "bit IRPTL .;", replaced normally occurring interrupt. Note that software breakpoint restricted immediately after manipulation instructions LIRPTL/IMASKP software breakpoint triggers emulator interrupt. Workaround: artificial latching interrupts required direct user writes LIRPTL/IMASKP, first mask interrupts before writing LIRPTL/IMASKP then unmask them upon completion write. This will preclude overlap between LIRPTL loading beginning interrupt service.
Asynchronous Host Reads fail tSADRDL less than external clock cycle meeting tSADRDL specification result address host read latch properly causing data from previous address read driven bus. consecutive reads occurring from same address, example when reading subsequent times from external port buffer, first host reads will performed correctly. Workaround: Guarantee that address valid external clock cycle previous where asserted will resolve this problem. tSADRDL should minimum external clock cycle.
32-bit wide link port transfers limited throughput with LCLK-to-CCLK ratio There latency internal update link port transmit buffer status delaying request. This occurs when link port running core link clock ratio transmitting byte wide link port data with DMA. This latency results stall link clock cycles every other word transmitted link port. This anomaly does create data loss corruption, only reduction overall transfer speed. following link port transfers work properly affected this anomaly: wide transfers Nibble wide link port transfers Transfers where link ports running 1:2, link clock core ratios Workaround: Maximum throughput achieved sending 32-bit data buffer 48-bit data. Because
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memory organized DSP, data 32-bit column) memory accessed 48-bit column) memory. (Memory organization discussed further hardware reference manual.) Data buffers column memory transferred 48-bit data using following steps: Program index register point column address properly corresponding beginning column data buffer. order first address column data buffer translated properly into three column address buffer must located address whose value multiple 32-bit addressing. other words, buffer would need start address 0x50000, 0x50003, 0x50006, 0x50009, 0x5000C etc. block 48-bit address translation obtained multiplying decimal address 2/3. example: location 0x5000C 32-bit space would translate 0x50008 48-bit space 0x5000C 0x50000 decimal Program count register that will send number words that corresponds length data buffer. Each 48-bit word that transferred will consist words. Configure link port send 48-bit data with LxEXT LCTL register. receiving will also have configured receive bit-words will place words memory such that they will accessible 32-bit data from buffer declared column memory.
Internal memory operation will possible while /TRST active (low). This prevents from booting properly well hangs functionality applied that been successfully booted. Normally, /TRST signal JTAG port recommended tied hold Test Access Port (TAP) reset, when emulator connected. boards designed with JTAG header, this accomplished placing jumper across /TRST /BTRST, under assumption that /BTRST tied target board. Workaround: board designed used with emulator JTAG header), /TRST /RESET. This will allow JTAG circuitry initialize properly prevent /TRST from going after reset. When JTAG header present board, /BTRST should tied /RESET instead GND, under assumption that there JTAG boundary scan controller board. this case: When emulator connected JTAG header, VisualDSP emulator session will control /TRST signal. order debug booting, user (F5) VisualDSP debugger window, reset then halt emulator result boot. advised that emulator pull down /TRST. emulator connected while VisualDSP emulator session active, internal memory will operate properly.
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When emulator connected JTAG header, jumper /TRST /BTRST. Conditional type instruction fail SIMD Given that type conditional instruction follows (see page 4-14 ADSP-21160 SHARC Instruction Reference more details instruction type): COND Jump |(Md, Else compute, |DM(Ia, Mb)=dreg;| |dreg=DM(Ia, Mb);|
|(PC, <reladdr6>)|
SIMD mode, condition TRUE both jump occurs condition FALSE, then else block this instruction executed. both conditions FALSE register post modifies intended. register erroniously fails post modifiy only conditions FALSE. This instruction does work intended only one, both, conditions FALSE. Workaround: When SIMD mode, substitute type instruction type replace type instruction. example: JUMP ELSE DM(I1, could separated into: JUMP DM(I1, Broadcast load fails type instruction Broadcast loads described page 4-17 ADSP-21160 SHARC Instruction Reference fail. example SIMD instruction, JUMP(M8, I8), else R6=dm(I1,M1);, both should loaded with value address pointed DSP, when instruction executed loaded properly, erroneously loaded with value address pointed I1+1. Workaround: same workaround anomaly
Rn=MANT results will rounded RND32 enabled
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instruction Rn=MANT designed work independently rounding mode, does not. example, consider following instructions: R2=0x45678901; F1=float R0=mant rounding enabled (RND32) result would R0=8ACF120000, rounding enabled result would R0=8ACF120200. Workaround: desired result MANT instruction unrounded, rounding enabled code, user must disable rounding manually before executing MANT instruction then reenable instruction after MANT instruction been executed. Keep mind that writes MODE1 have cycle effect latency. workaround implemented example presented above would follows: MODE1 RND32; R2=0x45678901; F1=float R0=mant MODE1 RND32; NOP;
Illegal stalls occur under certain circumstances When register load followed read same register automatically inserts cycle stall between those instructions. erroneously identifies certain instruction patterns register reads when they not. This results unintended additional stall. There functional failures beyond stall. Workaround: Typically register loads part initialization code possibility additional stall problem. such cases workaround necessary. cases where cycle accuracy code using affected register loads critical (ex. registers directly written critical loop) instruction must inserted after register load ensure cycle count predictability. addition instruction that doesn't involve data addressing, modify/bit-reverse instructions indirect jumps used. there series loads registers, then there need NOPs between each loads, only last load needs followed NOP. example: 0x50000; 0x1; 0xFF;
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0x55000; 0x1; 0xFF; NOP; This needs added predicting number cycles execution accurately. Serial Port Multichannel mode, external cycle early causes data corruption Multichannel mode should ignore external frame sync that occurs when SPORT still process receiving frame data. erroneously samples cycle before frame data externally generated sent cycle early would properly ignored. This will cause corruption current frame data. Once failure mode occurred will longer recognize valid signals. This failure will only occur signal comes cycle early, externally generated signals received time before last cycle frame will ignored intended. This failure occurs independently mulitchannel frame delay configuration well.
Workaround: avoid problems with multichannel mode this configuration, ensure that device transmitting signal does send cycle before existing frame data. Once this failure occurred, SPORT must disabled, reconfigured reenabled resume normal operation.
Execution instructions that modify interrupt latch registers cause incoming interrupts ignored When execute phase manipulation instruction that modifies interrupt latch register extended core being held off, some interrupts that latched during this period interrupt latch register lost. core held when fetching next instruction from external memory, accessing data from external memory, reading from empty buffer, writing full buffer register reads that take more than core clock cycle. specific Group system register manipulation instructions that affected follows: IRPTL <data32>; IRPTL <data32>; IRPTL <data32>; LIRPTL <data32>; LIRPTL <data32>; LIRPTL <data32>; IMASKP <data32>; IMASKP <data32>; IMASKP <data32>;
interrupts that missed IRQx, EMUI, TMZHI, TMZLI, VIRPT, LPxI, EPxI. LpxI interrupts affected only driven transfer mode. This failure will occur under following conditions: When manipulation instruction that modifies interrupt latch register executed from external memory.
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When manipulation instruction executed from internal memory delayed branch JUMP CALL external memory. example:
JUMP/CALL ext_mem_location (db); IRPTL <data32>; NOP; JUMP/CALL ext_mem_location (db); NOP; IRPTL <data32>;
When manipulation instruction executed from internal memory immediately followed external memory data access. example:
IRPTL <data32>; dm(ext_mem) IRPTL <data32>; pm(ext_mem) IRPTL <data32>; dm(ext_mem); IRPTL <data32>; pm(ext_mem);
When manipulation instruction executed from emulator (running stepping.) When manipulation instruction executed from internal memory immediately followed access from core breakpoint register. core breakpoint registers proprietary only used emulator. These will cause error user's application.
Workaround: workaround condition place manipulation operation internal memory. workaround condition avoid manipulation instruction from being within delayed branch JUMP CALL external memory placing before JUMP CALL external memory. workaround conditions place NOP; instruction directly following manipulation instruction.
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Compiler fixes will implented service pack scheduled June 2003. These fixes will cause compiler avoid failure modes workarounds described above. breakpoint following JUMP, CALL, trigger early/improper emulator break Because hardware's failure detect when EMUIDLE instruction aborted, placing breakpoint memory location directly after JUMP, CALL, cause emulator break falsely with error: "Emulator halted software breakpoint, breakpoint found" Workaround: software breakpoint directly after jump, call, rts.
register write followed directly register read fails during context switch Switching context registers from primary secondary sets cycle affect latency, enabling following code structure: MODE1 SRD1L; 0x52; enable context switch DAG1 from primary secondary write DAG1 primary register read DAG1 secondary register
secondary register previously 0xAA, then instruction example above should 0xAA, however erroneously forwards primary load secondary register read that example above will actually equal 0x52. This anomaly only affects write followed read that takes advantage latency context switch. (07-09-0004) Workaround: Placing instruction that does write register between read write example will yield correctly expected results follows: MODE1 SRD1L; 0x52; Nop; enable context switch DAG1 from primary secondary write DAG1 primary register read DAG1 secondary register
take advantage fact that affect latency context switch should allow instruction cycle where your instructions will still pertain initial context. example below, code rearranged that primary load occurs before context switch initiated. secondary registers will correctly accessed after requisite cycle effect latency. 0x52; MODE1 SRD1L; Nop; write DAG1 primary register enable context switch DAG1 from primary secondary read DAG1 secondary register
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System registers written with access have cycle effect latency cycle effect latency when accessing system registers does occur when accesses bus. example, following instruction, MODE1 setting will come into affect cycle just after MODE1 write: MODE1=PM(I9,M9); NOP; //MODE1 setting effect this instruction NOP; //without anomaly, setting would effect starting this location following system registers affected: MODE1, MODE2, IRPTL, IMASK, IMASKP, MMASK, FLAGS, LIRPTL, ASTATX, ASTATY, STKYX, STKYY, USTAT1, USTAT2, USTAT3, USTAT4 accesses manipulation instructions correctly insert cycle effect latency when writing system registers. Workaround: access such MODE1=DM(I4, instead accesses when writing system registers. manipulations instructions such MODE1 0x5; instead accesses when writing system registers
Conditional fails SIMD mode conditional SIMD mode will execute expected. Consider example: COND (DB); above instruction SIMD mode should executed when COND both processing elements true. DSP's behavior executing instruction follows: Branches address stored stack. Pops status stack ASTATx/y MODE1 status registers have been pushed interrupt IRQ2-0 timer interrupt. Clears appropriate interrupt mask pointer (IMASKP) register. behavior seen with respect conditions follows: When condition both false then this instruction executed. This expected.
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When false true, then action does take place actions take place. This anomalous. this case none above actions should taken. When true, false then same case When true, true then three actions take place. This expected. Workaround: include conditional statement SIMD will enabled. Seperating conditional into separate instructions. following acceptable alternative: cond jump (pc,2); RTI;
Single instruction loops terminate early single instruction loop, termination condition checked every cycle. When condition becomes true, loop supposed execute three more times before exiting loop. Loops with instruction only execute more times after termination condition true instruction loop contains data move. Workaround: data move inside single instruction loop. Increase length loop, possibly adding nop; instructions.
reversal fails with indirect jump reverse mode program tries indirect jump, bit-reverse setting considered. example code given below executed, tries jump location pointed instead jumping bit-reversed value i.e. 0x250000. 0x0000A400; 0x0; MODE1 BR8; NOP; JUMP(M8,I8); Workaround: reverse mode with indirect jump.
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VIPD gets cleared when branching supposed clear VIPD return from VIRPT interrupt service routine. VIPD gets cleared right when branching VIRPT interrupt service routine. Workarounds: FLAGS indicate that vector interrupt processed. host should poll FLAG instead VIPD bit. Also, should toggle flag before writing address into VIRPT register. registers (like MSGRx, unused peripheral registers etc) indicate vector interrupt status. host should read this register before writing address into VIRPT register.
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These anomalies represent currently known differences between revision

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