BOOT BLOCK FLASH MEMORY FLASH MEMORY FEATURES Eleven er
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BOOT BLOCK FLASH MEMORY
FLASH MEMORY
FEATURES
Eleven erase blocks: 16KB boot block (protected) parameter blocks Eight main memory blocks SmartVoltage Technology (SVT): 3.3V ±0.3V ±10% ±10% Address access times: 80ns 110ns 3.3V Industry-standard pinouts Inputs outputs fully TTL-compatible Automated write erase algorithm Two-cycle WRITE/ERASE sequence
MT28F008B1
SMARTVOLTAGE
ASSIGNMENT (Top View) 40-Pin TSOP Type (C-2)
OPTIONS
Timing VCC/3.3V VCC) 80ns/110ns access Boot Block Starting Address (FFFFFH) Bottom (00000H)
MARKING
Package Plastic 40-pin TSOP Type (10mm 20mm) Part Number Example: MT28F008B1VG-8
GENERAL DESCRIPTION
MT28F008B1 nonvolatile, electrically blockerasable (flash), programmable read-only memory containing 8,388,608 bits organized 1,048,576 words bits. SmartVoltage Technology (SVT) provides industrystandard, multi- single-voltage, dual-supply operation. Writing erasing device done with either voltage, while operations performed with 3.3V VCC. fabricated with Micron's advanced CMOS floating-gate process. MT28F008B1 organized into eleven separately erasable blocks. ensure that critical firmware protected from accidental erasure overwrite, MT28F008B1 features hardware-protected boot block. Writing erasing
Boot Block Flash Memory F19.p65 Rev. 2/99
boot block requires either applying super-voltage driving HIGH addition executing normal WRITE ERASE sequences. This block used store code implemented low-level system recovery. remaining blocks vary density written erased with additional security measures. byte address issued read memory array with HIGH. Valid data output until next address issued, goes HIGH. Please refer Micron's site (www.micron.com/ flash/htmls/datasheets.html) latest full-length data sheet.
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Boot Block Flash Memory F19.p65 Rev. 2/99
FUNCTIONAL BLOCK DIAGRAM
Input Buffer
Control
Logic Addr. Buffer/ Latch 96KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block Command Execution Logic Machine YDecoder State Select Gates Sense Amplifiers Write/Erase-Bit Compare Verify Input Data Latch Parameter Block Parameter Block 16KB Boot Block
A0-A19
Addr. Power (Current) Control Counter
Decoder/Block Erase Control
Switch/ Pump Status Register Identification Register
DQ0-DQ7
Output Buffer
BOOT BLOCK FLASH MEMORY
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BOOT BLOCK FLASH MEMORY
DESCRIPTIONS
TSOP NUMBERS SYMBOL TYPE Input DESCRIPTION Write Enable: Determines given cycle WRITE cycle. LOW, cycle either WRITE command execution logic (CEL) memory array. Chip Enable: Activates device when LOW. When HIGH, device disabled goes into standby power mode. Write Protect: Unlocks boot block when HIGH VPPH1 (5V) VPPH2 (12V) during WRITE ERASE. Does affect WRITE ERASE operation other blocks. Reset/Power-Down: When LOW, clears status register, sets internal state machine (ISM) array read mode places device deep power-down mode. inputs, including CE#, "Don't Care," outputs High-Z. unlocks boot block overrides condition when (12V), must held during other modes operation. Output Enable: Enables data output buffers when LOW. When HIGH, output buffers disabled. Address Inputs: Select unique byte 1,048,576 available.
Input Input
Input
A0-A19
Input Input
DQ0-DQ7
Input/ Output Supply
Data I/Os: Data output pins during READ operation data input pins during WRITE. These pins used input commands CEL. Connect: These pins driven left unconnected. Write/Erase Supply Voltage: From WRITE ERASE CONFIRM until completion WRITE ERASE, must VPPH1 (5V) VPPH2 (12V). "Don't Care" during other operations. Power Supply: ±10% +3.3V ±0.3V. Ground.
Supply Supply
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BOOT BLOCK FLASH MEMORY
TRUTH TABLE1
FUNCTION Standby RESET READ READ Output Disable WRITE/ERASE (EXCEPT BOOT ERASE SETUP ERASE CONFIRM3 WRITE SETUP WRITE4 READ ARRAY5 BLOCK)2, IDENTIFICATION8, VPPH VPPH VPPH VPPH 10H/40H Data-In Data-In WRITE/ERASE (BOOT ERASE SETUP ERASE ERASE WRITE4 WRITE4, READ ARRAY5 DEVICE CONFIRM3 CONFIRM3, BLOCK)2 VPPH VPPH 10H/40H Data-In Data-Out High-Z DQ0-DQ7 High-Z High-Z
WRITE SETUP
Manufacturer Compatibility Device (top boot) Device (bottom boot) NOTE:
VIL, VIH, VIH. VPPH VPPH1 VPPH2 12V. Operation must preceded ERASE SETUP command. Operation must preceded WRITE SETUP command. READ ARRAY command must issued before reading array after writing erasing. When VIH, VHH. 12V. 12V; also read issuing IDENTIFY DEVICE command. A1-A8, A10-A19 VIL.
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BOOT BLOCK FLASH MEMORY
FUNCTIONAL DESCRIPTION
MT28F008B1 flash memory incorporates number features make ideally suited system firmware. memory array segmented into individual erase blocks. Each block erased without affecting data stored other blocks. These memory blocks read, written erased with commands command execution logic (CEL). controls operation internal state machine (ISM), which completely controls WRITE, BLOCK ERASE VERIFY operations. protects each memory location from over-erasure optimizes each memory location maximum data retention. addition, greatly simplifies control necessary writing device in-system external programmer. Functional Description provides detailed information operation MT28F008B1 organized into these sections: Overview Memory Architecture Output (READ) Operations Input Operations Command Status Register Command Execution Error Handling WRITE/ERASE Cycle Endurance Power Usage Power-Up blocks require only voltage present before writing erasing. HARDWARE-PROTECTED BOOT BLOCK This block memory array erased written only when taken when brought HIGH. This provides additional security core firmware during in-system firmware updates should unintentional power fluctuation system reset occur. MT28F008B1 available versions: MT28F008B1T addresses boot block starting from FFFFFH, MT28F008B1B addresses boot block starting from 00000H. INTERNAL STATE MACHINE (ISM) BLOCK ERASE WRITE timing simplified with that controls erase write algorithms memory array. ensures protection against overerasure optimizes write margin each cell. During WRITE operations, automatically increments monitors WRITE attempts, verifies write margin each memory cell updates status register. When BLOCK ERASE performed, automatically overwrites entire addressed block (eliminates overerasure), increments monitors ERASE attempts, sets bits status register. STATUS REGISTER status register allows external processor monitor status during WRITE ERASE operations. bits 8-bit status register cleared entirely ISM. These bits indicate whether busy with ERASE WRITE task when ERASE been suspended. Additional error information three other bits: status, write status erase status. COMMAND EXECUTION LOGIC (CEL) receives interprets commands device. These commands control operation READ path (i.e., memory array, register status register). Commands issued while active. However, there restrictions what commands allowed this condition. Command Execution section more detail. DEEP POWER-DOWN MODE allow maximum power conservation, MT28F008B1 features very current, deep powerdown mode. enter this mode, taken ±0.2V. this mode, current draw maximum 20µA
OVERVIEW
SMARTVOLTAGE TECHNOLOGY (SVT) SmartVoltage Technology allows maximum flexibility in-system READ, WRITE ERASE operations. 5V-only systems, WRITE ERASE operations executed with voltage available system, highest WRITE ERASE performance achieved with voltage 12V. operation, 3.3V ELEVEN INDEPENDENTLY ERASABLE MEMORY BLOCKS MT28F008B1 organized into eleven independently erasable memory blocks that allow portions memory erased without affecting rest memory data. special boot block hardware-protected against inadvertent erasure writing requiring either supervoltage driving HIGH. these conditions must exist along with voltage 12V) before WRITE ERASE will performed boot block. remaining
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BOOT BLOCK FLASH MEMORY
3.3V VCC. Entering deep power-down also clears status register sets read array mode. BOOT BLOCK hardware-protected boot block provides extra security most sensitive portions firmware. This 16KB block only erased written when specified boot block unlock voltage VHH) when HIGH. During WRITE ERASE boot block, must held held HIGH until WRITE ERASE completed. must VPPH 12V) when boot block written erased. MT28F008B1 available configurations, bottom boot block. MT28F008B1T boot block version supports processors variety. MT28F008B1B bottom boot block version intended 680X0 RISC applications. Figure illustrates memory address maps associated with these versions. PARAMETER BLOCKS parameter blocks store less sensitive more frequently changing system parameters also store configuration diagnostic coding. These blocks enabled erasure when VPPH. supervoltage unlock control required.
MEMORY ARCHITECTURE
MT28F008B1 memory array architecture designed allow sections erased without disturbing rest array. array divided into eleven addressable blocks that vary size independently erasable. When blocks rather than entire array erased, total device endurance enhanced, system flexibility. Only ERASE function block-oriented. READ WRITE operations done random-access basis. boot block protected from unintentional ERASE WRITE with hardware protection circuit that requires super-voltage applied that driven HIGH before erasure commenced. boot block intended core firmware required basic system functionality. remaining blocks require either these conditions before WRITE ERASE operations.
BYTE ADDRESS FFFFFH
BYTE ADDRESS FFFFFH
128KB Main Block
E0000H DFFFFH FC000H FBFFFH FA000H F9FFFH F8000H F7FFFH E0000H DFFFFH
16KB Boot Block Parameter Block Parameter Block 96KB Main Block
128KB Main Block
C0000H BFFFFH
128KB Main Block
A0000H 9FFFFH
128KB Main Block
80000H 7FFFFH C0000H BFFFFH
128KB Main Block
128KB Main Block
60000H 5FFFFH A0000H 9FFFFH
128KB Main Block
128KB Main Block
40000H 3FFFFH 80000H 7FFFFH
128KB Main Block
128KB Main Block
20000H 1FFFFH 60000H 5FFFFH
128KB Main Block
96KB Main Block
08000H 07FFFH 06000H 05FFFH 04000H 03FFFH 00000H
128KB Main Block
40000H 3FFFFH
Parameter Block Parameter Block 16KB Boot Block
128KB Main Block
20000H 1FFFFH
128KB Main Block
00000H
Bottom Boot MT28F008B1xx-xxB
Boot MT28F008B1xx-xxT
Figure MEMORY ADDRESS MAPS
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BOOT BLOCK FLASH MEMORY
MAIN MEMORY BLOCKS eight remaining blocks general-purpose memory blocks require super-voltage control erased written. These blocks intended code storage, ROM-resident applications operating systems that require in-system update capability.
OUTPUT (READ) OPERATIONS
MT28F008B1 features three different types READs. Depending current mode device, READ operation will produce data from memory array, status register device identification register. each these three cases, WE#, inputs controlled similar manner. Moving between modes perform specific READ will covered Command Execution section. MEMORY ARRAY read memory array, must HIGH, must LOW. Valid data will output pins once these conditions have been valid address given. Valid data will remain pins until address changes, goes HIGH, whichever occurs first. pins will continue output data after each address transition long remain LOW. After power-up RESET, device will automatically array read mode. commands their operations covered Command Command Execution sections. STATUS REGISTER Performing READ status register requires same input sequencing READ array except that address inputs "Don't Care." Data from status register latched falling edge CE#, whichever occurs last. contents status register change during READ status register, either toggled while other held update output. Following WRITE ERASE, device automatically enters status register read mode. addition, READ during WRITE ERASE will produce status register
contents DQ0-DQ7. When device erase suspend mode, READ operation will produce status register contents until another command issued, while certain other modes, READ STATUS REGISTER given return status register read mode. commands their operations covered Command Command Execution sections. IDENTIFICATION REGISTER READ 8-bit device identification registers requires same input sequencing READ array. must HIGH, must LOW. used decode between bytes device register; other address inputs "Don't Care." When LOW, manufacturer compatibility output, when HIGH, device output. identification register read mode, READ IDENTIFICATION issued while device certain other modes. addition, identification register read mode reached applying super-voltage (VID) pin. Using this method, register read while device mode. Once returned VIH, device will return previous mode.
INPUT OPERATIONS
pins used either input data array input command CEL. command input issues 8-bit command control mode operation device. WRITE used input data memory array. following section describes both types inputs. More information describing types inputs write erase device provided Command Execution section. COMMANDS perform command input, must HIGH, must LOW. Addresses "Don't Care" must held stable, except during ERASE CONFIRM (described later section). 8-bit command input DQ0-DQ7 latched rising edge (CE#-controlled) (WE#-controlled), whichever occurs first.
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BOOT BLOCK FLASH MEMORY
MEMORY ARRAY WRITE memory array sets desired bits logic cannot change given logic from logic Setting bits logic requires that entire block erased. perform WRITE, must HIGH, must LOW, must VPPH1 VPPH2. Writing boot block also requires that HIGH. A0-A19 provide address written, while data written array input pins. data addresses latched rising edge (CE#-controlled) (WE#controlled), whichever occurs first. WRITE must pre-
ceded WRITE SETUP command. Details input data array will covered Write Sequence section.
COMMAND
simplify writing memory blocks, MT28F008B1 incorporates that controls internal algorithms WRITE ERASE cycles. 8-bit command used control device. Details sequence commands provided Command Execution section. Table lists valid commands.
Table COMMAND
COMMAND RESERVED CODE DESCRIPTION This command unlisted commands invalid should called. These commands reserved allow future feature enhancements. Must issued after other command cycle before array read. necessary issue this command after power-up RESET. Allows device manufacturer compatibility read. used decode between manufacturer compatibility LOW) device HIGH). Allows status register read. Please refer Table more information status register bits. Clears status register bits through which cannot cleared ISM. first command given two-cycle ERASE sequence. ERASE will completed unless followed ERASE CONFIRM. second command given two-cycle ERASE sequence. Must follow ERASE SETUP command valid. Also used during ERASE SUSPEND resume ERASE. first command given two-cycle WRITE sequence. write data address given following cycle complete WRITE. Requests halt ERASE puts device into erase suspend mode. When device this mode, only READ STATUS REGISTER, READ ARRAY ERASE RESUME commands executed.
READ ARRAY IDENTIFY DEVICE
READ STATUS REGISTER CLEAR STATUS REGISTER ERASE SETUP ERASE CONFIRM/RESUME
WRITE SETUP ERASE SUSPEND
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BOOT BLOCK FLASH MEMORY
STATUS REGISTER
8-bit status register (see Table polled check WRITE ERASE completion related errors. During following WRITE, ERASE ERASE SUSPEND, READ operation will output status register contents DQ0-DQ7 without prior command. While status register contents read, outputs will updated there change status unless toggled. device write, erase, erase suspend status register read mode, READ STATUS REGISTER (70H) issued view status register contents. defined bits ISM, only erase suspend status bits reset ISM. erase, write status bits must cleared using CLEAR STATUS REGISTER. status (SR3) set, will allow further WRITE ERASE operations until status register cleared. This allows user choose when poll clear status register. example, host system perform multiple BYTE WRITE operations before checking status register instead checking after each individual WRITE. Asserting signal powering down device will also clear status register.
Table STATUS REGISTER
STATUS STATUS REGISTER STATUS Ready Busy ERASE SUSPEND STATUS ERASE suspended ERASE progress/completed ERASE STATUS BLOCK ERASE error Successful BLOCK ERASE WRITE STATUS WRITE error Successful WRITE STATUS voltage detected present RESERVED DESCRIPTION ISMS displays active status state machine during WRITE BLOCK ERASE operations. controlling logic polls this determine when erase write status bits valid. Issuing ERASE SUSPEND places suspend mode sets this ISMS "1." will remain until ERASE RESUME issued. after maximum number ERASE cycles executed without successful verify. only cleared CLEAR STATUS REGISTER command after RESET. after maximum number WRITE cycles executed without successful verify. only cleared CLEAR STATUS REGISTER command after RESET. VPPS detects presence voltage. does monitor continuously, does indicate valid voltage. sampled after WRITE ERASE CONFIRM given. VPPS must cleared CLEAR STATUS REGISTER RESET. Reserved future use.
SR0-2
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BOOT BLOCK FLASH MEMORY
COMMAND EXECUTION
Commands issued bring device into different operational modes. Each mode allows specific operations performed. Several modes require sequence commands written before they reached. following section describes properties each mode, Table lists command sequences required perform desired operation. READ ARRAY array read mode initial state device upon power-up after RESET. device other mode, READ ARRAY (FFH) must given return array read mode. Unlike WRITE SETUP command (40H), READ ARRAY does need given before each individual READ access. IDENTIFY DEVICE IDENTIFY DEVICE (90H) written enter identify device mode. While device this mode, READ will produce device identification when HIGH manufacturer compatibility identification when LOW. device will remain this mode until another command given. WRITE SEQUENCE consecutive cycles needed input data array. WRITE SETUP (40H 10H) given first cycle. next cycle WRITE, during which write address data issued brought VPPH. Writing boot block also requires that brought brought HIGH same time brought VPPH. will begin write byte. must held VPPH until WRITE completed (SR7 While executes WRITE, status (SR7) will device will respond commands. READ operation will produce status register contents DQ0-DQ7. When status (SR7) logic WRITE been completed, device will into status register read mode until another command given. After initiated WRITE, cannot aborted except RESET powering down part. Doing either during WRITE will corrupt data being written. only WRITE SETUP command been given, WRITE nullified performing null WRITE. execute null WRITE, must written.
Table COMMAND SEQUENCES
CYCLES CYCLE REQ'D OPERATION ADDRESS WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE CYCLE OPERATION ADDRESS READ READ WRITE WRITE WRITE WRITE
COMMANDS READ ARRAY IDENTIFY DEVICE READ STATUS REGISTER CLEAR STATUS REGISTER ERASE SETUP/CONFIRM ERASE SUSPEND/RESUME WRITE SETUP/WRITE ALTERNATE WRITE NOTE:
DATA
DATA
NOTES
Must follow WRITE ERASE CONFIRM commands order enable flash array READ cycles. Identify Address: manufacturer compatibility device Identify Data. Status Register Data. Block Address (A12-A19). Addresses "Don't Care" first cycle must held stable. Address written; Data written
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BOOT BLOCK FLASH MEMORY
Once status (SR7) been set, device will status register read mode until another command issued. ERASE SEQUENCE Executing ERASE sequence will bits within block logic command sequence necessary execute ERASE similar that WRITE. provide added security against accidental block erasure, consecutive command cycles required initiate ERASE block. first cycle, addresses "Don't Care," ERASE SETUP (20H) given. second cycle, must brought VPPH, address within block erased must issued, ERASE CONFIRM (D0H) must given. command other than ERASE CONFIRM given, write erase status bits (SR4 SR5) will set, device will status register read mode. After ERASE CONFIRM (D0H) issued, will start ERASE addressed block. READ operation will output status register contents DQ0-DQ7. must held VPPH until ERASE completed (SR7 Once ERASE completed, device will status register read mode until another command issued. Erasing boot block also requires that either held HIGH same time VPPH. ERASE SUSPENSION only command that issued while ERASE progress ERASE SUSPEND. This command allows other commands executed while pausing ERASE progress. Once device reached erase suspend mode, erase suspend status (SR6) status (SR7) will set. device given READ ARRAY, ERASE RESUME READ STATUS REGISTER command. After READ ARRAY been issued, location within block being erased read. ERASE RESUME issued before been set, device will immediately proceed with ERASE progress.
ERROR HANDLING
After status (SR7) been set, (SR3), write (SR4) erase (SR5) status bits checked. combination these three bits been set, error occurred. cannot reset these three bits. clear these bits, CLEAR STATUS REGISTER (50H) must given. status (SR3) set, further WRITE ERASE operations cannot resume until status register cleared. Table lists combination errors.
Table STATUS REGISTER ERROR DECODE1
NOTE: STATUS BITS ERROR DESCRIPTION errors voltage error WRITE error WRITE error, voltage valid time WRITE ERASE error ERASE error, voltage valid time ERASE CONFIRM Command sequencing error WRITE/ERASE error Command sequencing error, voltage error, with WRITE ERASE errors
SR3-SR5 must cleared using CLEAR STATUS REGISTER.
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BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE ENDURANCE
MT28F008B1 designed fabricated meet advanced firmware storage requirements. ensure this level reliability, must ±10% during WRITE ERASE cycles. Operation outside these limits reduce number WRITE ERASE cycles that performed device. device will enter standby mode. this mode, maximum current 130µA 110µA 3.3V. brought HIGH during WRITE ERASE, will continue operate, device will consume respective active power until WRITE ERASE completed.
POWER USAGE
MT28F008B1 offers several power-saving features that utilized array read mode conserve power. Deep power-down mode enabled bringing LOW. Current draw this mode maximum 20µA 3.3V VCC. With LOW, device will enter idle current mode when being accessed. this mode, maximum current 3.3V VCC. When HIGH,
POWER-UP
During power-up, necessary sequence VPP. likelihood unwanted WRITE ERASE operations minimized since consecutive cycles required execute either operation. However, held HIGH held during powerup additional protection while ramping above VLKO active. After power-up RESET, status register reset, device will enter array read mode.
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BOOT BLOCK FLASH MEMORY
SELF-TIMED WRITE SEQUENCE1 COMPLETE WRITE STATUS-CHECK SEQUENCE
Start (WRITE completed)
Start
WRITE
Error
BYTE WRITE Error
WRITE Byte Address/Data
WRITE Successful
STATUS REGISTER READ
Complete Status Check (optional)
WRITE Complete
NOTE:
Sequence repeated additional WRITEs. Complete status check required. However, further WRITEs inhibited until status register cleared. Device will status register read mode. return array read mode, command must issued. during WRITE BLOCK ERASE attempt, CLEAR STATUS REGISTER must issued before further WRITE ERASE operations allowed CEL. Status register bits must cleared using CLEAR STATUS REGISTER.
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BOOT BLOCK FLASH MEMORY
SELF-TIMED BLOCK ERASE SEQUENCE1
Start
COMPLETE BLOCK ERASE STATUS-CHECK SEQUENCE
Start (ERASE completed)
WRITE
Error
SR4,
Command Sequence Error
WRITE D0H, Block Address
BLOCK ERASE Error
ERASE Busy
STATUS REGISTER READ
ERASE Successful
Complete Status Check (optional) Suspend ERASE? Suspend Sequence
ERASE Resumed
ERASE Complete
NOTE:
Sequence repeated erase additional blocks. Complete status check required. However, further ERASEs inhibited until status register cleared. return array read mode, command must issued. Refer ERASE SUSPEND flowchart more information. during WRITE BLOCK ERASE attempt, CLEAR STATUS REGISTER must issued before further WRITE ERASE operations allowed CEL. Status register bits must cleared using CLEAR STATUS REGISTER.
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BOOT BLOCK FLASH MEMORY
ERASE SUSPEND/RESUME SEQUENCE
Start (ERASE progress)
WRITE (ERASE SUSPEND)
STATUS REGISTER READ
WRITE (READ ARRAY)
ERASE Completed
Done Reading? WRITE (ERASE RESUME)
Resume ERASE
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BOOT BLOCK FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS*
Voltage Supply Relative -0.5V +6V** Input Voltage Relative -0.5V +6V** Voltage Relative -0.5V +12.6V Voltage Relative -0.5V +12.6V Temperature under Bias -10°C +80°C Storage Temperature (plastic) -55°C +125°C Power Dissipation *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. **VCC, input pins transition <20ns <20ns. Voltage pulse <20ns <20ns.
ELECTRICAL CHARACTERISTICS RECOMMENDED READ OPERATING CONDITIONS
(0°C +70°C) PARAMETER/CONDITION Supply Voltage 3.3V Supply Voltage Input High (Logic Voltage, inputs Input (Logic Voltage, inputs Device Identification Voltage, Supply Voltage SYMBOL -0.5 11.4 -0.5 12.6 12.6 UNITS NOTES
OPERATING CHARACTERISTICS
(0°C +70°C) 3.3V PARAMETER/CONDITION OUTPUT VOLTAGE LEVELS (TTL) Output High Voltage (IOH -2mA [3.3V], -2.5mA [5V]) Output Voltage (IOL [3.3V], 5.8mA [5V]) OUTPUT VOLTAGE LEVELS (CMOS) Output High Voltage (IOH -100µA) INPUT LEAKAGE CURRENT input VCC); other pins under test INPUT LEAKAGE CURRENT: INPUT (11.4V 12.6 VID) INPUT LEAKAGE CURRENT: INPUT (11.4V 12.6 VHH) OUTPUT LEAKAGE CURRENT (Outputs disabled; VOUT VCC) NOTE: voltages referenced VSS. VOH1 0.45 0.45
UNITS
NOTES
VOH2
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BOOT BLOCK FLASH MEMORY
CAPACITANCE
25°C; MHz) PARAMETER/CONDITION Input Capacitance Output Capacitance SYMBOL UNITS NOTES
READ STANDBY CURRENT DRAIN
(0°C +70°C) 3.3V PARAMETER/CONDITION READ CURRENT: INPUT LEVELS (CE# VIL; VIH; MHz; Other inputs VIH; VIH) READ CURRENT: CMOS INPUT LEVELS (CE# 0.2V; 0.2V; MHz; Other inputs 0.2V 0.2V; 0.2V) STANDBY CURRENT: INPUT LEVELS power supply standby current (CE# VIH; Other inputs VIH) STANDBY CURRENT: CMOS INPUT LEVELS power supply standby current (CE# 0.2V) IDLE CURRENT (CE# 0.2V; 0Hz; Other inputs 0.2V 0.2V; 0.2V; Array read mode) DEEP POWER-DOWN CURRENT: SUPPLY (RP# ±0.2V) STANDBY READ CURRENT: SUPPLY (VPP 5.5V) STANDBY READ CURRENT: SUPPLY (VPP 5.5V) DEEP POWER-DOWN CURRENT: SUPPLY (RP# ±0.2V) NOTE: SYMBOL ICC1 UNITS NOTES
ICC2
ICC3
ICC4
ICC5 ICC6 IPP1 IPP2 IPP3
dependent cycle rates. dependent output loading. Specified values obtained with outputs open.
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BOOT BLOCK FLASH MEMORY
READ TIMING PARAMETERS ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS TEST CONDITION (5V)
(0°C +70°C; ±10%)
CHARACTERISTICS PARAMETER READ cycle time Access time from Access time from Access time from address HIGH output valid delay HIGH output High-Z Output hold time from OE#, address change pulse width SYMBOL tACE tAOE tRWH UNITS NOTES
TEST CONDITION (3.3V)
(0°C +70°C; +3.3V ±0.3V)
CHARACTERISTICS PARAMETER READ cycle time Access time from Access time from Access time from address HIGH output valid delay HIGH output High-Z Output hold time from OE#, address change pulse width NOTE: SYMBOL tACE tAOE tRWH 1,000 UNITS NOTES
Measurements tested under Test Condition delayed tACE minus tAOE after falls before tACE affected. Measurements tested under Test Condition
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BOOT BLOCK FLASH MEMORY
TEST CONDITION
Input pulse levels 0.4V 2.4V Input rise fall times <10ns Input timing reference level 0.8V Output timing reference level 0.8V Output load gate 100pF
TEST CONDITION
Input pulse levels Input rise fall times <10ns Input timing reference level 1.5V Output timing reference level 1.5V Output load gate 50pF
A0-A19
READ CYCLE
VALID ADDRESS
DQ0-DQ7
VALID DATA
3.3V TIMING PARAMETERS
SYMBOL (5V)1
DON'T CARE UNDEFINED
1,000 UNITS
UNITS
SYMBOL (3.3V)2 (5V)1 (3.3V)2 (5V)1
tRWH tRWH
(3.3V)2 (5V)1 tACE (3.3V)2
tACE tAOE tAOE
(5V)1 (3.3V)2
(3.3V)2 (5V)1 (3.3V)2
(5V)1
NOTE: Measurements tested under Test Condition ±10%. Measurements tested under Test Condition 3.3V ±0.3V.
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BOOT BLOCK FLASH MEMORY
RECOMMENDED WRITE/ERASE CONDITIONS1
(0°C +70°C; ±10% +3.3V ±0.3V)
PARAMETER/CONDITION WRITE/ERASE lockout voltage voltage during WRITE/ERASE operation voltage during WRITE/ERASE operation Boot block unlock voltage WRITE/ERASE lockout voltage SYMBOL VPPLK VPPH1 VPPH2 VLKO 11.4 11.4 12.6 12.6 UNITS NOTES
WRITE/ERASE CURRENT DRAIN VCC)
(0°C +70°C; ±10%) PARAMETER/CONDITION WRITE CURRENT: SUPPLY WRITE CURRENT: SUPPLY ERASE CURRENT: SUPPLY ERASE CURRENT: SUPPLY ERASE SUSPEND CURRENT: SUPPLY (ERASE suspended) ERASE SUSPEND CURRENT: SUPPLY (ERASE suspended) SYMBOL ICC7 IPP4 ICC8 IPP5 ICC9 IPP6 UNITS NOTES
WRITE/ERASE CURRENT DRAIN (3.3V VCC)
(0°C +70°C; +3.3V ±0.3V) PARAMETER/CONDITION WRITE CURRENT: SUPPLY WRITE CURRENT: SUPPLY ERASE CURRENT: SUPPLY ERASE CURRENT: SUPPLY ERASE SUSPEND CURRENT: SUPPLY (ERASE suspended) ERASE SUSPEND CURRENT: SUPPLY (ERASE suspended) NOTE: SYMBOL ICC10 IPP7 ICC11 IPP8 ICC12 IPP9 UNITS NOTES
WRITE operations tested VCC/VPP voltages equal less than previous ERASE, READ operations tested voltages equal less than previous WRITE operation. Absolute WRITE/ERASE protection when VPPLK. When used, cannot exceed more than 500mV during WRITE ERASE operations. Parameter specified when device accessed. Actual current draw will ICC9 VCC) ICC12 (3.3V VCC) plus READ current READ executed while device erase suspend mode.
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
Boot Block Flash Memory F19.p65 Rev. 2/99
BOOT BLOCK FLASH MEMORY
SPEED-DEPENDENT WRITE/ERASE TIMING CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS TEST CONDITION (5V)
(0°C +70°C; ±10%)
CHARACTERISTICS PARAMETER WRITE cycle time HIGH pulse width HIGH pulse width pulse width pulse width SYMBOL tWPH tCPH UNITS NOTES
TEST CONDITION (3.3V)
(0°C +70°C; +3.3V ±0.3V)
CHARACTERISTICS PARAMETER WRITE cycle time HIGH pulse width HIGH pulse width Address setup time HIGH Data setup time HIGH pulse width pulse width NOTE: Measurements tested under Test Condition Measurements tested under Test Condition SYMBOL tWPH tCPH UNITS NOTES
Boot Block Flash Memory F19.p65 Rev. 2/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
BOOT BLOCK FLASH MEMORY
WRITE/ERASE TIMING CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS: WE#-CONTROLLED WRITES
(0°C +70°C; ±10%)
CHARACTERISTICS PARAMETER Address setup time HIGH Address hold time from HIGH Data setup time HIGH Data hold time from HIGH setup time hold time from HIGH setup time HIGH setup time HIGH HIGH delay HIGH setup time HIGH WRITE duration Boot BLOCK ERASE duration Parameter BLOCK ERASE duration Main BLOCK ERASE duration HIGH busy status (SR7 hold time from status data valid HIGH hold time from status data valid Boot block relock delay time NOTE: SYMBOL tVPS1 tVPS2 tRHS tWED1 tWED2 tWED3 tWED4 tVPH tRHH tREL UNITS NOTES
Measured with VPPH1 Measured with VPPH2 12V. should held held HIGH until boot block WRITE ERASE complete. WRITE/ERASE times measured valid status register data (SR7 Polling status register before falsely indicate WRITE ERASE completion. tREL required relock boot block after WRITE ERASE boot block.
Boot Block Flash Memory F19.p65 Rev. 2/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
BOOT BLOCK FLASH MEMORY
WRITE/ERASE TIMING CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS: CE#-CONTROLLED WRITES
(0°C +70°C; ±10%)
CHARACTERISTICS PARAMETER Address setup time HIGH Address hold time from HIGH Data setup time HIGH Data hold time from HIGH setup time hold time from HIGH setup time HIGH setup time HIGH HIGH delay HIGH setup time HIGH WRITE duration Boot BLOCK ERASE duration Parameter BLOCK ERASE duration Main BLOCK ERASE duration HIGH busy status (SR7 hold time from status data valid HIGH hold time from status data valid Boot block relock delay time NOTE: SYMBOL tVPS1 tVPS2 tRHS tWED1 tWED2 tWED3 tWED4 tVPH tRHH tREL UNITS NOTES
Measured with VPPH1 Measured with VPPH2 12V. should held held HIGH until boot block WRITE ERASE complete. WRITE/ERASE times measured valid status register data (SR7 Polling status register before falsely indicate WRITE ERASE completion. tREL required relock boot block after WRITE ERASE boot block.
Boot Block Flash Memory F19.p65 Rev. 2/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
BOOT BLOCK FLASH MEMORY
WRITE/ERASE TIMING CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS: WE#-CONTROLLED WRITES
(0°C +70°C; +3.3V ±0.3V)
CHARACTERISTICS PARAMETER Address hold time from HIGH Data hold time from HIGH setup time hold time from HIGH setup time HIGH setup time HIGH HIGH delay HIGH setup time HIGH WRITE duration Boot BLOCK ERASE duration Parameter BLOCK ERASE duration Main BLOCK ERASE duration HIGH busy status (SR7 hold time from status data valid HIGH hold time from status data valid Boot block relock delay time SYMBOL tVPS1 tVPS2 tRHS tWED1 tWED2 tWED3 tWED4 tVPH tRHH tREL 1,000 UNITS NOTES
WRITE/ERASE TIMING CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS: CE#-CONTROLLED WRITES
(0°C +70°C; +3.3V ±0.3V)
CHARACTERISTICS PARAMETER Address hold time from HIGH Data hold time from HIGH setup time hold time from HIGH setup time HIGH setup time delay HIGH delay HIGH setup time HIGH WRITE duration Boot BLOCK ERASE duration Parameter BLOCK ERASE duration Main BLOCK ERASE duration HIGH busy status (SR7 hold time from status data valid HIGH hold time from status data valid Boot block relock delay time NOTE: SYMBOL tVPS1 tVPS2 tRHS tWED1 tWED2 tWED3 tWED4 tVPH tRHH tREL 1,000 UNITS NOTES
Measured with VPPH1 Measured with VPPH2 12V. should held held HIGH until boot block WRITE ERASE complete. WRITE/ERASE times measured valid status register data (SR7 Polling status register before falsely indicate WRITE ERASE completion. tREL required relock boot block after WRITE ERASE boot block.
Boot Block Flash Memory F19.p65 Rev. 2/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
BOOT BLOCK FLASH MEMORY
WRITE ERASE DURATION CHARACTERISTICS
3.3V PARAMETER Boot/parameter BLOCK ERASE time Main BLOCK ERASE time Main BLOCK WRITE time NOTE: 3.3V UNITS NOTES
Typical values measured +25°C. Assumes system overhead. Typical WRITE times checkerboard data pattern.
Boot Block Flash Memory F19.p65 Rev. 2/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
A0-A19
WRITE/ERASE CYCLE WE#-CONTROLLED WRITE/ERASE
Note
,,,,,,,,,,
WED1/2/3/4 Status (SR7=0) Status (SR7=1) [Unlock boot block] [Unlock boot block] [12V VPP] VPP]
BOOT BLOCK FLASH MEMORY
CMD/ Data-in
DQ0-DQ7
3.3V TIMING PARAMETERS
,,,,, ,,,,,,,
VPS1 VPS2 VPPH2 VPPH1 VPPLK WRITE SETUP ERASE SETUP input WRITE ERASE (block) address asserted, WRITE data ERASE CONFIRM issued WRITE ERASE executed, status register checked completion Command next operation issued
DON'T CARE
SYMBOL (5V)3 (3.3V)4 tWPH (5V)3
tWPH
UNITS SYMBOL
tVPS1 tVPS2
1,000
UNITS
(5V)
(3.3V)4
(5V)3
(3.3V)4 (5V) (3.3V)4
(3.3V) tRHS (5V) tRHS (3.3V)
tWED1 tWED2 tWED3 tWED4 tVPH tRHH
(5V) (3.3V)4
NOTE:
Address inputs "Don't Care" must held stable. Either HIGH unlocks boot block. Measurements tested under Test Condition ±10%. Measurements tested under Test Condition 3.3V ±0.3V.
Boot Block Flash Memory F19.p65 Rev. 2/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
A0-A19
WRITE/ERASE CYCLE CE#-CONTROLLED WRITE/ERASE
Note
,,,,,,,
WED1/2/3/4 Status (SR7=0) Status (SR7=1) [Unlock boot block] [Unlock boot block] [12V VPP] VPP]
BOOT BLOCK FLASH MEMORY
CMD/ Data-in
DQ0-DQ7
3.3V TIMING PARAMETERS
,,,,,,,
VPS1 VPS2 VPPH2 VPPH1 VPPLK WRITE SETUP ERASE SETUP input WRITE ERASE (block) address asserted, WRITE data ERASE CONFIRM issued WRITE ERASE executed, status register checked completion Command next operation issued
DON'T CARE
SYMBOL (5V)3 (3.3V)4 tCPH (5V)3
tCPH
UNITS SYMBOL
tVPS1 tVPS2
1,000
UNITS
(5V)
(3.3V)4
(5V)3
(3.3V)4 (5V) (3.3V)4
(3.3V) tRHS (5V) tRHS (3.3V)
tWED1 tWED2 tWED3 tWED4 tVPH tRHH
(5V) (3.3V)4
NOTE:
Address inputs "Don't Care" must held stable. Either HIGH unlocks boot block. Measurements tested under Test Condition ±10%. Measurements tested under Test Condition 3.3V ±0.3V.
Boot Block Flash Memory F19.p65 Rev. 2/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
BOOT BLOCK FLASH MEMORY
40-PIN PLASTIC TSOP (10mm 20mm)
.795 (20.19) .780 (19.81) .0197 (0.50) .727 (18.47) .721 (18.31) .010 (0.25)
INDEX .397 (10.08) .010 (0.25) .006 (0.15) .391 (9.93)
.010 (0.25)
.007 (0.18) .005 (0.13) DETAIL .047 (1.20)
.004 (0.10) GAGE PLANE .008 (0.20) .002 (0.05)
.024 (0.60) .016 (0.40) DETAIL .0315 (0.80)
NOTE:
dimensions inches (millimeters) typical where noted. Package width length include mold protrusion; allowable mold protrusion .01" side.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron registered trademark Micron Technology, Inc.
Boot Block Flash Memory F19.p65 Rev. 2/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
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