Improved UART Clocking Techniques Generation HPCs generation HPCs

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Improved UART Clocking Techniques Generation HPCs generation HPCs

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Improved UART Clocking Techniques Generation HPCs
Improved UART Clocking Techniques Generation HPCs
generation HPCs have on-chip UARTs with much better baud rate generation techniques better status reporting capabilities This article explains detail accurate baud rate generation HPC46400E UARTs with appropriate examples
National Semiconductor Application Note Ravi Kumar April 1993
UART implemented HPC46400E upward compatible enhancement UART present HPC46083 Unlike UART HPC46083 operating mode selected either Asynchronous Synchronous Here also select baud rate through software conjunction with both prescalar baud select registers
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FIGURE
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C1995 National Semiconductor Corporation
DD11292
RRD-B30M75 Printed
COMMON FEATURES SUPPORTED HPC46083 UART NEWER VERSION UART HPC46400E
Fully programmable serial interface characteristics including Accurate baud rate generation without penalty using expensive crystal 625k baud 7-bit characters possible stop lengths Even Mark Space parity generation detection
Fully programmable serial interface characteristics including 9-bit characters stop bits
interrupt sources (Receiver buffer full Transmit buffer empty)
Selectable Asynchronous Synchronous mode operation
Independent clock inputs (either on-chip off-chip)
transmitter receiver
Loopback Diagnostic test capability
lets various methods BAUD Rate generation First shall discuss DIVBY used generate required baud-rate UART CLOCK SOURCE FROM DIVBY REGISTER Clock DIVBY register generated using precise value crystals underflow Referring Figure that baud rate from internal source DIVBY register
Error reporting capabilities (Data overrun error framing
error)
Attention wake mode receiver enhance networking capability ADDITIONAL UART FEATURES AVAILABLE HPC46400E
Upwardly compatible from earlier UARTs such
HPC16083
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FIGURE Simplified UART Clock Routing
following sample assembly language routine illustrating BAUD Rate generation using DIVBY register through precise value crystal This program will test HPC16400E UART 9600 baud using crystal DIVBY (baud clock from internal source) power-up default setup Baud clock from internal source DIVBY Frame format start stop clock should crystal sect uart begin sbit sibit rbit rbit 0x122 0x122 018e DIRB outward direction BFUNL turns xtclk xrclk Load DIVBY from table generate 9600 baud (CKI rom16
baud clock baud rate 9600 baud bclk 9600 153600 With clock 156250 (within xmit ifbit 0126 0120 xmit load char Load TBUF transmit continue xmit
endsect begin Hence percentage error Baud Rate produced error (156250 153600) 15360
which within error limits
Baud Rate Calculation Using DIVBY Register through Precise Value Crystal Table gives values loaded into UART section DIVBY register This table defines baud rates different crystals 6608
that more care selecting crystal frequency necessary generate exact baud rates Obviously baud rate generation restricted crystal frequency
TABLE Baud Clock (x16 Clock) Baud Rate 8304 Crystal Baud Rate 6603 Crystal
Allowed Defined Timer Underflow
1024 2048 4096 8192 16384 32768 65536 131072 38400 19200 9600 4800 2400 1200 65536 32768 16384 8192 4096 2048 1024
Baud Rate Calculation Using DIVBY Register Timer Underflow Suppose want generate 9600 baud DIVBY register load UART bits with value 0001 which means Baud Clock defined underflow (refer Table Once again referring Figure BAUD clock from internal source Let's calculate Pre-Scale value loaded into register (0X018C) register (0X018A) Baud Clock Required baud rate Crystal Freq Clock Input Pre-Scale Value Baud Clock specific case required BAUD Rate 9600 crystal freq Clock Input
Baud Clock 9600 15360
Clock Input Pre-Scale Value 153600 Pre-Scale Value Actual value loaded into register (Prescale value this case Percentage error Baud Rate produced Pre-Scale Value Baud Rate Baud Clock Baud Clock Clock Input Pre-Scale Value Clock Input Baud Clock 156250 Therefore Baud Rate 156250 9765 Hence error (9765 9600) 9600 Which within error limits
following sample assembly language routine illustrating BAUD Rate generation through DIVBY underflow ******** Generation BAUD clock through timer3 without triggering timer intrpt ******** sect uart rom16 tmmode 0xcccc divby 0x2010 t3reg r3reg 0x8ccc stop timers thru DIVBY with reload Toff Reload Reload Toff BAUD rate 9600 uart internal xmit uart internal config BFUN config DIRB outward Start timer stop Ack'em
rbit 0x122 rbit 0x122 sbit 0x0f2 sbit 0x0f4 tmmode
Loop continuously xmit char specified baud rate xmit 0126 ifbit xmit load char load TBUF transmit
endsect
BAUD RATE CALCULATION USING (PRECISION UART TIMER) Precision UART Timer (PUT) obsolete kept only compatibility with software developed those earlier components registers BAUDR with 15-bit divisor field BAUDC 15-bit free-running down counter These programmed divide (CKI clock factor from 32767 units thus yielding time base UART higher resolution than that available through DIVBY register Referring Figure that BAUD clock source external Suppose Clock input required baud rate 9600 then value loaded into BAUDR register will Required Baud Rate Where Given Hence (BAUDR Required Baud Rate (9600) (CK2 (BAUDR
BAUDR
decimal
here value loaded into BAUDR register will select timer external clock source BAUDR register must 1000 0000 0011 0011 Binary
Note BAUDC must also loaded with same value (Reload Value)
Percentage error Baud Rate produced BAUDR Therefore Baud Rate 9615 Required Baud Rate 9600 Hence Error (9615 9600) 9600 Which well within error limits
(BAUDR
following sample assembly language routine illustrating BAUD Rate generation through This program will test HPC16400E UART 9600 baud Using generating 9600 baud sect code This
Using generating 9600 baud sect code main 0x017e 0x017c sbit sbit char xmission xmit 0126 xmit endsect main Load TBUF transmit Continue xmit Load char 0x0000 0x8033 9600 baud UDIV xtclk xrclk (baud count) baud value generate 9600 baud UDIVR (baud div) register xtclk xrclk DIRB outward direction BFUNL turns
0x122 0x122 0x05 0x05
BAUD RATE CALCULATIONS USING (BAUD RATE GENERATOR) most flexible accurate on-chip clocking provided BAUD Rate generator (BRG) BAUD Rate generator controlled register pair BAUD shown below Prescale factor selected upper bits register (the PRESCALE field) units clock from step increments lower
bits register conjunction with bits baud register form 11-bit BAUDRATE field which defines baud rate divisor ranging from 2048 units prescaled clock selected PRESCALE field Asynchrnous Mode resulting baud rate clocking rate selected through circuit maximum baud rate generated using kbaud
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Formula Required Baud Rate
From formula stated earlier required baud rate have 9600 N*Pe 9600
where Input Clock Baud Rate Divisor Prescaler Division Factor
Note This calculation Asynchronous mode UART operation
with given Clock
Suppose need 9600 Baud then Required Baud Rate 9600
which prescaler factor should selected from Table such that ``N'' should close integer Therefore substituting values table calculating have following table
TABLE Prescaler
UART Prescaler Factors Prescale Field (Binary) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 Value Closest Integer Prescaler Factor (Compatibility Mode)
10101 10110 10111 11000 11010 11010 11011
choose such that it's closest integer Obviously closest being integer therefore value when
11100 11101 11110 11111
from table ``UART Prescaler Factors'' select binary ``Prescale field'' using value derived above Percentage error Baud Rate produced from above table Baud Rate
9600 (9600 9600) 9600 error 0002% Which obviously negligible
Binary format 11001 Therefore Prescaler field 11001 baud rate divisor baud rate field Referring register format page combine bits bits baud rate field load Prescaler bits (PSR) Baud Rate generate bits (BRG) respectively 11001 Baud Rate field Combined value binary format 1100 1000 0000 0100 which therefore load register with C804 following sample assemble language routine illustrating BAUD Rate generation through Baud rate generation using register BAUD RATE where prescalar value baud rate filed 9600 baud crystal (CKI) BAUD crystal (CKI) BAUD sect code rom16 main First exit compatibility mode writing register 012a load prescalar 012c load baudrate field BAUD 0120 data space parity register 0122 ENUI register stop bits DIRB register outward direction BFUNL register turns Loop continuously xmit chars specified baud rate xmit load char 0126 Load TBUF transmit xmit Continue xmit endsect main
Improved UART Clocking Techniques Generation HPCs
Performance Comparison Regarding Higher Baud Rate Generation Let's take case where required Baud rate 625k baud Required Baud Rate Therefore BAUDR BAUDR BAUDR Therefore that used generate 625k baud limit baud BAUDR
Baud Rate Required 625k
NcPe1 Prescale field 00001 00000000000 0000 1000 0000 0000 0800 Therefore load register with 0800 generate 625k baud Conclusion Thus that clocking techniques generation HPCs more accurate very flexible Generation higher rates done with relative ease also observe that using newer UART clocking techniques percentage error difference between required baud rate actual baud rate produced goes down significantly
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