M5M5V208AKV/KR PRELIMINARY Notice: This final specification.
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29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This final specification. Some parametric limits subject change
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
DESCRIPTION
M5M5V208A family voltage 2-Mbit static RAMs organized 262,144-words 8-bit, fabricated Mitsubishi's highperformance 0.25µm CMOS technology. M5M5V208A suitable memory applications where simple interfacing battery operating battery backup important design objectives. M5M5V208A packaged 32-pin 13.4mm STSOP packages. types STSOPs available, M5M5V208AKV (normal-lead-bend STSOP) M5M5V208AKR (reverse-lead-bend STSOP). These types STSOPs suitable surface mounting double-sided printed circuit boards. From point operating temperature, family divided into three versions; "Standard", "W-version", "I-version". Those summarized part name table below.
FEATURES
Single 3.6V power supply clocks, refresh inputs outputs compatible. Easy memory expansion power down Data retention supply voltage=2.0V Three-state outputs: OR-tie capability prevents data contention Common Data Battery backup capability Small stand-by current 0.3µA(typ.)
PACKAGE
M5M5V208AKV,KR 32pin 13.4 TSOP Stand-by current Icc(PD), Vcc=3.0V typical Ratings (max.) 25°C 40°C 25°C 40°C 70°C -85°C -Active current Icc1 (3.0V, typ.)
PART NAME TABLE
Version, Operating temperature Part name stands for"KV"or"KR")
Power Supply
Access time
max.
Standard +70°C
W-version +85°C
I-version +85°C
M5M5V208A## -55L M5M5V208A## -70L M5M5V208A## -55H M5M5V208A## -70H M5M5V208A## -55LW M5M5V208A## -70LW M5M5V208A## -55HW M5M5V208A## -70HW M5M5V208A## -55LI M5M5V208A## -70LI M5M5V208A## -55HI M5M5V208A## -70HI
55ns 3.6V 70ns 3.6V 55ns 0.3µA 70ns 55ns 3.6V 70ns 55ns 3.6V 70ns 0.3µA 55ns 3.6V 70ns 55ns 3.6V 70ns 0.3µA
20µA
20mA
(f=10MHz)
20µA 50µA
(f=1MHz)
24µA
20µA 50µA
24µA
"typical" parameter sampled, 100% tested.
CONFIGURATION (TOP VIEW)
M5M5V208AKV
M5M5V208AKR
Outline 32P3K-B(KV)
Outline 32P3K-C(KR)
MITSUBISHI ELECTRIC
29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This final specification. Some parametric limits subject change
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
FUNCTION
operation mode M5M5V208A determined combination device control inputs Each mode summarized function table. write cycle executed whenever level overlaps with level high level address must before write cycle must stable during entire cycle. data latched into cell trailing edge whichever occurs first, requiring set-up hold time relative these edge maintained. output enable directly controls output stage. Setting high level,the output stage high-impedance state, data contention problem write cycle eliminated. read cycle executed setting high level level while active state When setting high level level, chips non-selectable mode which both reading writing disabled. this mode, output stage high-impedance state, allowing OR-tie with other chips memory expansion power supply current reduced stand-by current which specified Icc3 Icc4, memory data held power supply, enabling battery back-up operation during power failure power-down operation nonselected mode.
FUNCTION TABLE
Mode selection selection Write Read High-impedance High-impedance High-impedance Standby Standby Active Active Active
BLOCK DIAGRAM
262144 WORDS BITS ROWS COLUMNS BLOCKS
CLOCK GENERATOR
(3V)
(0V)
*Pin numbers inside dotted line show reverse-lead-bend sTSOP.
MITSUBISHI ELECTRIC
29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This final specification. Some parametric limits subject change
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Topr Tstr
Input voltage Output voltage Power dissipation Operating temperature Storage temperature
Conditions
With respect Ta=25°C
Ratings 0.5*~4.6 0.5*
(Max 4.6)
Unit
Standard Version Version
3.0V case Pulse width 30ns
~150
ELECTRICAL CHARACTERISTICS
Symbol VOH1 VOH2 Icc1 Parameter High-level input voltage Low-level input voltage High-level output voltage High-level output voltage Low-level output voltage Input current Output current off-state Active supply current
(CMOS-level Input)
(Vcc= 3.6V, unless otherwise noted)
Limits Test conditions IOH= 0.5mA IOH= 0.05mA IOL=2mA VI=0
S1=VIH S2=VIL OE=VIH VI/O=0
0.3* -0.5V
+0.3V
Unit
10MHz 5MHz 1MHz 10MHz 5MHz 1MHz
0.2V, Vcc-0.2V, other inputs 0.2V Vcc-0.2V,output-open S1=VIL,S2=VIH, other inputs=VIH output-open 0.2V,
Icc2
Active supply current
(TTL-level Input)
Icc3
Stand-by current
other inputs=0 Vcc-0.2V, Vcc-0.2V other inputs=0
~+25°C ~+40°C ~+70°C ~+85°C
Icc4
Stand-by current
S1=VIH S2=VIL,other inputs=0
0.33
3.0V case Pulse width 30ns
CAPACITANCE
Symbol Parameter
Input capacitance Output capacitance
(Vcc= 3.6V, unless otherwise noted)
Test conditions
VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
Limits
Unit
Note Direction current flowing into positive mark). Typical value 25°C
MITSUBISHI ELECTRIC
29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This final specification. Some parametric limits subject change
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
ELECTRICAL CHARACTERISTICS MEASUREMENT CONDITIONS
Input pulse level Input rise fall time Reference level Output loads
Vcc= 3.6V, unless otherwise noted) 1TTL including scope Fig.1 Output load
3.6V VIH=2.2V,VIL=0.4V VOH=VOL=1.5V Fig.1,CL=30pF CL=5pF (for ten,tdis) Transition measured ±500mV from steady state voltage. (for ten,tdis)
READ CYCLE
Limits Symbol ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select access time Chip select access time Output enable access time Output disable time after high Output disable time after Output disable time after high Output enable time after Output enable time after high Output enable time after Data valid time after address
-55L,H
-70L,H
Unit
WRITE CYCLE
Limits Symbol tw(W) tsu(A) tsu(A-WH) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Parameter Write cycle time Write pulse width Address setup time Address setup time with respect Chip select setup time Chip select setup time Data setup time Data hold time Write recovery time Output disable time from Output disable time from high Output enable time from high Output enable time from
-55L,H
-55L,H
Unit
MITSUBISHI ELECTRIC
29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This final specification. Some parametric limits subject change
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
TIMING DIAGRAMS Read cycle
A0~17 ta(A) (S1)
(Note
tdis (S1)
(Note
(Note
(S2) (OE) (OE) tdis (S2)
(Note
(Note
tdis (OE) (S1) (S2)
(Note
DQ1~8
level
DATA VALID
Write cycle control mode)
A0~17
(S1)
(Note (Note
(Note
(S2)
(Note
(A-WH) tdis tdis (OE) DQ1~8 ten(OE) trec
DATA STABLE
MITSUBISHI ELECTRIC
29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This final specification. Some parametric limits subject change
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
Write cycle control mode)
A0~17 (S1) trec
(Note (Note (Note
(Note
(Note
(Note
DQ1~8
DATA STABLE
Write cycle control mode)
A0~17
(Note (Note
(S2)
trec
(Note
(Note
(Note
(Note
DQ1~8
DATA STABLE Note Hatching indicates state "don't care". Writing executed while high overlaps low. When falling edge simultaneously prior falling edge rising edge outputs maintained high impedance state. Don't apply inverted phase signal externally when output mode.
MITSUBISHI ELECTRIC
29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This final specification. Some parametric limits subject change
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
POWER DOWN CHARACTERISTICS ELECTRICAL CHARACTERISTICS
Symbol
(PD) (S1) (S2)
Parameter
Power down supply voltage Chip select input Chip select input
Test conditions
Limits
Unit
(PD)
Vcc=3.0V 0.2V,other inputs=0 Power down supply current Vcc-0.2V,S2 Vcc-0.2V other inputs=0
~+25°C ~+40°C ~+70°C ~+85°C
TIMING REQUIREMENTS
Symbol Parameter Power down time (PD) Power down recovery time trec (PD) Test conditions
Limits
Unit
POWER DOWN CHARACTERISTICS control mode
(PD)
2.2V 2.7V
2.7V
(PD)
2.2V
0.2V
control mode
0.2V 0.2V
(PD)
2.7V
2.7V
(PD)
0.2V
MITSUBISHI ELECTRIC
29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This final specification. Some parametric limits subject change
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
Revision History Revision A0.1E A0.2E
History first edition second edition
Date 09.Nov.'98 29.Nov.'99 Preliminary Preliminary
MITSUBISHI ELECTRIC
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