CMOS DRAM (EDO) Features Organization: 262,144 words bits High sp

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CMOS DRAM (EDO) Features Organization: 262,144 words bits High sp

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AS4C256K16E0
CMOS DRAM (EDO) Features
Organization: 262,144 words bits High speed 30/35/50 access time 16/18/25 column address access time 7/10/10/10 access time power consumption Active: (AS4C256K16E0-25) Standby: max, CMOS (AS4C256K16E0-25) page mode Refresh refresh cycles, refresh interval RAS-only CAS-before-RAS refresh self-refresh Self-refresh option available generation device only. Contact Alliance more information. Read-modify-write TTL-compatible, three-state JEDEC standard packages mil, 40-pin mil, 40/44-pin TSOP power supply Latch-up current
arrangement
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 LCAS UCAS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
designation
TSOP
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8
Pin(s)
Description Address inputs address strobe Input/output Output enable Column address strobe, upper byte Column address strobe, lower byte Read/write control Power 0.5V) Ground
I/O0 I/O15
UCAS LCAS
AS4C256K16E0
AS4C256K16E0
LCAS UCAS
Selection guide
Symbol Maximum access time Maximum column address access time Maximum access time Maximum output enable (OE) access time Minimum read write cycle time Minimum page mode cycle time Maximum operating current Maximum CMOS standby current
Shaded areas contain advance information.
AS4C256K16E0-30
AS4C256K16E0-35
AS4C256K16E0-50
Unit
tRAC tCAA tCAC tOEA ICC1 ICC2
4/11/01; v.1.1
Alliance Semiconductor
Copyright Alliance Semiconductor. rights reserved.
AS4C256K16E0
Functional description
AS4C256K16E0 high performance megabit CMOS Dynamic Random Access Memory (DRAM) organized 262,144 words bits. AS4C256K16E0 fabricated with advanced CMOS technology designed with innovative design techniques resulting high speed, extremely power wide operating margins component system levels. AS4C256K16E0 features high speed page mode operation which high speed read, write read-write performed bits defined column address. asynchronous column address uses extremely short address capture time ease system level timing constraints associated with multiplexed addressing. Very fast output access time eases system design. Refresh address combinations during period accomplished performing following:
RAS-only refresh cycles Hidden refresh cycles CAS-before-RAS refresh cycles Normal read write cycles Self-refresh cycles*
AS4C256K16E0 available standard 40-pin plastic 40/44-pin TSOP packages compatible with widely available automated testing insertion equipment. System level features include single power supply 0.5V tolerance direct interface with logic families.
Logic block diagram
REFRESH CONTROLLER
COLUMN DECODER SENSE
DATA BUFFER
I/O0 I/O15
CLOCK GENERATOR
UCAS LCAS
CLOCK GENERATOR
ADDRESS BUFFERS
DECODER ARRAY (4,194,304)
SUBSTRATE BIAS GENERATOR
CLOCK GENERATOR
Recommended operating conditions
Parameter Supply voltage Input voltage Symbol -1.0
+70°C) Unit
*Self-refresh option available generation device only. Contact Alliance more information.
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Absolute maximum ratings
Parameter Input voltage Output voltage Power supply voltage Operating temperature Storage temperature (plastic) Soldering temperature time Power dissipation Short circuit output current Latch-up current Symbol Vout TOPR TSTG TSOLDER Iout -1.0 -1.0 -1.0 +7.0 +7.0 +7.0 +150 Unit
NOTE: Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
electrical characteristics
Parameter
Input leakage current Output leakage current Operating power supply current
Symbol
ICC1
Test conditions
+5.5V pins under test DOUT disabled, Vout +5.5V RAS, UCAS, LCAS, address cycling; tRC=min UCAS LCAS cycling, UCAS LCAS VIH, RAS=UCAS=LCAS=VIL, address cycling: RAS=UCAS=LCAS= 0.2V RAS, UCAS, LCAS, cycling; IOUT -5.0 IOUT UCAS LCAS=VIL, A0-A8 VCC-0.2V, DQ0-DQ15 VCC-0.2V, 0.2V open
Unit Note
standby power ICC2 supply current Average power supply current, refresh mode page mode average power supply current CMOS standby power supply current CAS-before-RAS refresh power supply current Output Voltage ICC3
ICC4
ICC5
ICC6 ICC7
Self refresh current
Shaded areas contain advance information.
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
parameters common waveforms
Symbol tRAS tCAS tRCD tRAD tRSH(R) tCSH tCRP tASR tRAH tREF tCLZ Parameter Random read write cycle time
precharge time pulse width pulse width delay time column address delay time hold time (read cycle) hold time precharge time
Unit Notes
address setup time address hold time Transition time (rise fall) Refresh period
output
Shaded areas contain advance information.
Read cycle
Symbol tRAC tCAC tAR(R) tRCS tRCH
tRRH
Parameter Access time from Access time from Access time from address Column hold from Read command setup time Read command hold time Read command hold time Column address Lead time
precharge time
Unit 8,10 Notes 6,13 7,13
tRAL tCPN tOFF
Output buffer turn-off time
Shaded areas contain advance information.
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Write cycle
Symbol tASC tCAH tAWR tWCS tWCH tWCR tRWL tCWL Parameter
Column address setup time
Unit Notes
Column address hold time Column address hold time Write command setup time Write command hold time Write command hold time Write command pulse width Write command lead time Write command lead time Data-in setup time Data-in hold time
tDHR Data-in hold time Shaded areas contain advance information.
Read-modify-write cycle
Symbol tRWC tRWD tCWD tAWD tRSH(W) Parameter
Read-write cycle time delay time delay time
Unit Notes
Column address delay time
hold time (write)
pulse width (write) tCAS(W) Shaded areas contain advance information.
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
page mode cycle
Symbol tCAP tPCM tCRW tRASP Parameter
Read write cycle time
Unit Notes
Access time from precharge
precharge time
page mode cycle Page mode pulse width (RMW)
pulse width
Shaded areas contain advance information.
Refresh cycle
Symbol tCSR tCHR tRPC tCPT Parameter
setup time (CAS-before-RAS) hold time (CAS-before-RAS)
Unit Notes
precharge hold time
precharge time (CAS-before-RAS counter test)
Shaded areas contain advance information.
Output enable
Symbol tROH tOEA tOED tOEZ tOEH Parameter
hold time referenced access time data delay
Unit Notes
Output buffer turnoff delay from
command hold time
Shaded areas contain advance information.
Self refresh cycle
Symbol tRASS tRPS tCHS Parameter
pulse width (CBR self refresh) precharge time (CBR self refresh) hold time (CBR self refresh)
100K
Unit Notes
100K
100K
Shaded areas contain advance information.
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Notes
ICC1, ICC3, ICC4, ICC6 depend cycle rate. ICC1 ICC4 depend output loading. Specified values obtained with output open. initial pause required after power-up followed cycles before proper device operation achieved. case internal refresh counter, minimum CAS-before-RAS initialization cycles instead cycles required. initialization cycles required after extended periods bias without clocks (greater than ms). Characteristics assume parameters measured with load equivalent loads (min) (max) VCC. (min) (max) reference levels measuring timing input signals. Transition times measured between VIL. Operation within tRCD (max) limit insures that tRAC (max) met. tRCD (max) specified reference point only. tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation within tRAD (max) limit insures that tRAC (max) met. tRAD (max) specified reference point only. tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. Assumes three state test load Thevenin equivalent). Either tRCH tRRH must satisfied read cycle. tOFF (max) defines time which output achieves open circuit condition; referenced output voltage levels. tWCS, tWCH, tRWD, tCWD tAWD restrictive operating parameters. They included datasheet electrical characteristics only. (min) (min), cycle early write cycle data pins will remain open circuit, high impedance, throughout cycle. tRWD tRWD (min), tCWD tCWD (min) tAWD tAWD (min), cycle read-write cycle data will contain data read from selected cell. neither above conditions satisfied, condition data access time indeterminate. These parameters referenced leading edge early write cycles leading edge read-write cycles. Access time determined longest tCAA tCAC tCAP. tASC achieve (min) tCAP (max) values. These parameters sampled 100% tested.
switching waveform
Undefined/don't care Rising input Falling input
Read cycle waveform
tRAS tRCD tRSH
tCSH tCRP tASC tRCS tCAH tCAS
UCAS, LCAS
tRAD tASR tRAH tRAL
Address
Address
Address
tRRH tRCH
tROH
tRAC tOEA tCAC tCLZ tOEZ tOFF
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Upper byte read cycle waveform
tRAS
tRCD tCSH tCRP tCAS tRSH tCRP
UCAS
tCRP
LCAS
tRAH tRAD tASR tASC tRAL tCAH
Address
tRCS
Column
tRCH tRRH tROH
tOEA tRAC tCAC tCLZ tOFF tOEZ
Upper Lower
Data
Lower byte read cycle waveform
tRAS
tRCD tCSH tCRP tCAS tRSH tCRP
LCAS
tCRP
UCAS
tRAH tRAD tASR tASC tRAL tCAH
Address
tRCS
Column
tRRH tROH tRCH
Upper
tOEA tRAC tCAC tCLZ tOFF tOEZ
Lower
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Early write cycle waveform
tRAS
tCSH tRSH tCRP tRCD tAWR tRAD tASC tASR tRAH tCAH tRAL tCAS
UCAS, LCAS
Address
Address
Address
tWCR tCWL tRWL tWCS tWCH
tDHR
Data
Upper byte early write cycle waveform
tRAS
tAWR tASR tRAH tRAD tRAL
Address
Address
tASC tRCD
Column Address
tCAH tRSH tCSH tCAS tRPC tCWL tWCS tRWL tWCR tWCH tCRP
tCRP
UCAS
tCRP
LCAS
tDHR
Upper Lower
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Lower byte early write cycle waveform
tRAS
tRAD tASR tRAH tAWR tRAL
Address UCAS
Address
tCRP
Column Address
tRPC tASC tRCD tCSH tCAH tCAS tRSH tWCR tRWL tCWL tWCS tWCH tCRP
tCRP
LCAS
Upper
tDHR
Lower
Data
Write cycle waveform
tRAS
controlled)
tCSH tCRP tRCD tRSH tCAS tRAL tAWR tRAD tASR tRAH tASC tCAH
UCAS, LCAS
Address
Address
Address
tWCR tCWL tRWL
tOEH
tDHR tOED
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Upper byte write cycle waveform
tRAS
controlled)
tRAD tAWR tASR tRAH tRAL
Address
Address
tRCD tCRP
Column Address
tCSH tRSH tCAH tASC tCAS tCRP
UCAS
tCRP tRPC tCWL tRWL
LCAS
tOEH
Upper Lower
Data
tOED
Lower byte write cycle waveform
tRAS
controlled)
tRAD tASR tRAH tAWR tRAL
Address
Address
tRCD
Column Address
tCAH tCAS tCSH tACS tRSH tRPC tCWL tRWL tCRP
tCRP
LCAS
tCRP
UCAS
tOEH
Upper
Lower
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Read-modify-write cycle waveform
tRWC tRAS tCAS tCRP tRCD tCSH tRSH
UCAS, LCAS
tRAD tASR tRAH
tRAL tASC tCAH
Address
Address
Address
tRWD tAWD tRCS tCWD tOEA tOEZ tOED tRWL tCWL
tRAC
tCAC tCLZ
Data
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Upper byte read-modify-write cycle waveform
tRWC tRAS
tCSH tRCD tCRP tCAS tRSH tCRP
UCAS
tCRP tRPC tACS tRAL tCAH
LCAS
tRAD tASR tRAH
Address
Column Address
tRWD tAWD tRCS tCWD tOEA tOED tCWL tRWL
Upper Input
tCLZ tCAC tRAC
Data
tOEZ
Upper Output
Data
tOED
Lower Input Lower Output
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Lower byte read-modify-write cycle waveform
tRWC tRAS
tCRP tRPC tCSH tRCD tCRP tCAS tRSH tCRP
UCAS
LCAS
tRAD tASR tACS tRAH tRAL tCAH
Address
Column Address
tRWD tAWD tRCS tCWD tOEA tCWL tRWL
Upper Input Upper Output
Data
tOED
Lower Input
tRAC tCAC tCLZ
Data
tOEZ
Lower Output
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
page mode read cycle waveform
tRASP
tCSH tCRP tRCD tCAS tRSH
UCAS, LCAS
tRAD tASR tRAH
tASC
tCAH tRAL
Address
Address
tRCS tRCH tOEA
Address
tRCS
Address
tRCH tOEA tRRH
tRAC tCLZ tCAC tCAC tCAP
Data
Data
page mode byte read cycle waveform
tRASP tRSH tCAS tCRP tCAS tRAH tRAD tASC tCAH tASC tCAH tRAL tASC tRPC tCRP
tCSH tCRP tRCD tCAS
UCAS
LCAS
tASR
tCAH
Address
Column
tRCS tRCH tOEA
Column
tRCS tOEA tCAC tCLZ tCAP
Column
tRCS tRCH tOEA
tOFF tOEZ
Lower
tRAC tCAC tCLZ tOFF tOEZ
Data
tCAP tCAC tCLZ
tOFF tOEZ
Upper
Data Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
page mode early write cycle waveform
tRASP tRAH tRWL tRCD tCSH tCAS tASC tWCS tRAL tCAH tRSH
tCRP
UCAS, LCAS
tASR tRAD
Address
address
address
Address
Address
tCWL tWCH tOEH
tHDR
Data
Data
Data
page mode byte early write cycle waveform
tRASP tRSH tCAS tCRP tCAS tRAD tRAH tASR tASC tRAL tCAH tRPC
tCSH tCRP tRCD tCAS tCRP
UCAS
LCAS
tCAH tASC tCAH tASC
Address
Column
Column
Column
tRWL tWCH tWCS tCWL
tWCH tWCS tCWL
tWCH tWCS tCWL
Lower
Data
Upper
Data Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
page mode read-modify-write cycle waveform
tRASP
tPCM tCSH tRCD tCAS tCRP
UCAS, LCAS Address
tASR
tRAD tRAH tCAH tCAH
tRAL tCAH
tRCS
tRWD tCWD tAWD
tCWL tCWD
Address
tRWL tCWD tAWD tCWL
tOEA tOEZ tRAC tCLZ tCAC tCLZ tCAC tCAP tCLZ tCAC tOED tOEA
Data Data
Data Data
Data Data
CAS-before-RAS refresh cycle waveform
tRAS
tRPC tCPN tCSR tCHR
UCAS, LCAS
tOFF
only refresh cycle waveform
tRAS tRPC
VIL)
tCRP
UCAS, LCAS Address
tARS
tRAH
Address
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
page mode byte read-modify-write cycle
tRASP
tCSH tRCD tCRP tCAS tRSH tCAS
tCRP
UCAS
tPCM tCAS
LCAS
tRAD tRAH tASR tASC tCAH tCAH tAWD tASC tRAL tCAH tAWD tASC
Address
tRCS
tAWD tCWD tRWD
tRWL tCWD tCWD tCWL tOEA tOEA tOED tCAP tCWL
tCWL
tOEA
tOED
Upper Input
tRAC tCAC
Data
tOEZ tCLZ tOED
Data
tCAC tCLZ tOEZ
Upper Output
Data
Data
Lower Input
tOEZ tCAC tCLZ
Data
Lower Output
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Hidden refresh cycle (read) waveform
tRAS tCHR tRCD tRSH tCRP tRAS
tCRP
tRAD tRAH tASR tASC
Address
tRCS
Address
tRRH tOEA
tRAC tCAC tCLZ tOFF tOEZ
Data
Hidden refresh cycle (write) waveform
tRAS
tCRP tRCD tRSH
UCAS, LCAS
tRAD tRAH tASR tASC tRAL tCAH
Address
Address
Address
tRWL tWCR
tWCS
tWCH
tDHR
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
CAS-before-RAS refresh counter test cycle waveform
tRAS tRSH
tCSR tCHR tCPT tCAS
UCAS, LCAS
tCAH tRAL
Address
Address
tCAC tCLZ tOFF
Read Cycle
tRCS
Data
tRRH tRCH tOEA tROH
tRWL tCWL tWCH tWCS
Write Cycle
Data
tRCS tCWD tAWD
tCWL
Read-Write Cycle
tOEA tOED
tCLZ tCAC tOEZ
Data
Data
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
CAS-before-RAS self refresh cycle
tRASS tRPS
tRPC tCSR tCHS tRPC
UCAS, LCAS
tCEZ
Typical characteristics
Normalized access time Supply voltage Typical supply current supply voltage 25°C Normalized access time tRAC supply voltage Normalized access time Ambient temperature (°C) Typical supply current ambient temperature Typical access time Normalized access time tRAC ambient temperature Load capacitance (pF) Typical access time tRAC load capacitance
Supply current (mA)
Power-on current (mA)
Typical power-on current cycle rate 1/tRC
Supply current (mA) Supply voltage
Ambient temperature (°C)
Cycle rate (MHz)
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Refresh current (mA)
Typical refresh current ICC3 supply voltage
Typical refresh current ICC3 Ambient temperature Stand-by current (mA) Ambient temperature (°C) Refresh current (mA)
Typical stand-by current ICC2 supply voltage
Supply voltage
Supply voltage
Typical stand-by current ICC2 ambient temperature Output sink current (mA) Stand-by current (mA) Ambient temperature (°C)
Typical output sink current output voltage Output source current (mA) Output voltage
Typical output source current output voltage
Output voltage
Typical page mode current ICC4 ambient temperature page mode current (mA) Ambient temperature (°C) page mode current (mA)
Typical page mode current ICC4 supply voltage Supply voltage
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
Package dimensions
44-pin TSOP
0-5°
44-pin TSOP (mm) (mm) 0.05 0.95 1.05 0.30 0.45 0.127 (typical) 18.28 18.54 10.03 10.29 11.56 11.96 0.80 (typical) 0.40 0.60
40-pin
Seating Plane
40-pin 0.128 0.148 0.025 1.105 1.115 0.026 0.032 0.015 0.020 0.007 0.013 1.020 1.035 0.370 (typical) 0.390 0.410 0.435 0.445 0.050 (typical)
Capacitance
Parameter Input capacitance capacitance Symbol CIN1 CIN2 CI/O Signals
RAS, UCAS, LCAS,
MHz, room temperature, 0.5V Test conditions Vout Unit
I/O0 I/O15
Ordering codes
Package Access time Plastic SOJ, mil, 40-pin TSOP mil, 40/44-pin
Shaded areas contain advance information.
AS4C256K16E0-30JC
AS4C256K16E0-35JC
AS4C256K16E0-50JC AS4C256K16E0-50TC
Part numbering system
AS4C DRAM prefix 256K16E0 Device number
access time
Package: TSOP
Commercial temperature range,
4/11/01; v.1.1
Alliance Semiconductor
AS4C256K16E0
4/11/01; v.1.1
Alliance Semiconductor
Copyright Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights, mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such life-supporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

CMOS DRAM (EDO) Features Organization: 262,144 words bits High sp

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