Integrated 32-Bit Microcontroller with PC/AT-Compatible Peripherals, H
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Microcontroller
Integrated 32-Bit Microcontroller with PC/AT-Compatible Peripherals, Host Bridge, Synchronous DRAM Controller
DISTINCTIVE CHARACTERISTICS
Industry-standard Am5x86® with floating ROM/Flash controller 16-, 32-bit devices Enhanced PC/AT-compatible peripherals
point unit (FPU) 16-Kbyte write-back cache 100-MHz 133-MHz operating frequencies Low-voltage operation (core tolerant (3.3-V output levels) E86family embedded processors Part software-compatible family microprocessors microcontrollers well supported wide variety development tools Integrated host bridge controller leverages standard peripherals software MHz, 32-bit Revision 2.2-compliant High-throughput 132-Mbyte/s peak transfer Supports five external masters Integrated write-posting read-buffering high-throughput applications Synchronous DRAM (SDRAM) controller Supports 16-, 64-, 128-, 256-Mbit SDRAM Supports banks total Mbytes Error Correction Code provides system reliability Buffers improve read write performance AMDebugtechnology offers low-cost solution advanced debugging capabilities required embedded designers Allows instruction tracing during execution from Am5x86 CPU's internal cache Uses enhanced JTAG port low-cost debugging Parallel debug port high-speed data exchange during in-circuit emulation General-Purpose (GP) with programmable timing 16-bit devices provides good performance cost
provide improved performance Enhanced programmable interrupt controller (PIC) prioritizes interrupt levels external sources) with flexible routing Enhanced controller includes double buffer chaining, extended address transfer counts, flexible channel routing 16550-compatible UARTs operate baud rates 1.15 Mbit/s with optional interface Standard PC/AT-compatible peripherals Programmable interval timer (PIT) Real-time clock (RTC) with battery backup capability bytes Additional integrated peripherals Three general-purpose 16-bit timers provide flexible cascading 32-bit operation Watchdog timer guards against runaway software Software timer Synchronous serial interface (SSI) offers full-duplex half-duplex operation Flexible address decoding programmable memory mapping system addressing configuration programmable input/output (PIO) pins
Native support pSOS, QNX, RTXC, VxWorks,
Windows® operating systems Industry-standard BIOS support Plastic Ball Grid Array (PBGA388) package
GENERAL DESCRIPTION
microcontroller full-featured microcontroller developed general embedded market. microcontroller combines 32-bit, low-voltage with integrated peripherals suitable both real-time AT-compatible embedded applications. integrated host bridge, SDRAM controller, enhanced PC/AT-compatible peripherals, advanced debugging features provide system designer with wide range on-chip resources, allowing support legacy devices well devices available current marketplace.
Copyright 2001 Advanced Micro Devices, Inc. rights reserved.
Designed medium- high-performance applications telecommunications, data communications, information appliance markets, microcontroller particularly well suited applications requiring high throughput combined with latency. compact Plastic Ball Grid Array (PBGA) package provides high degree functionality very small form factor, making cost-effective many applications. 0.25-micron CMOS manufacturing process allows power consumption along with high performance.
Final Draft# 22003 Rev: Amendment/0 Issue Date: March 2001
ORDERING INFORMATION
-133
TEMPERATURE RANGE Commercial +85C) where: case temperature
PACKAGE TYPE 388-Pin Plastic Ball Grid Array (PBGA)
SPEED OPTION -100 -133
DEVICE NUMBER/DESCRIPTION integrated 32-bit microcontroller with PC/AT-compatible peripherals, host bridge, synchronous DRAM controller
Valid Combinations
Valid Combinations Valid combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Microcontroller Data Sheet
TABLE CONTENTS
Distinctive Characteristics General Description Ordering Information Logic Diagram Interface Logic Diagram Default Function Connection Diagram Designations Designations (Pin Number) Designations (Pin Name) Signal Descriptions Architectural Overview Industry-Standard Architecture AMDebugTechnology Advanced Debugging Industry-Standard Interface High-Performance SDRAM Controller ROM/Flash Controller Flexible Address-Mapping Hardware Easy-to-Use Interface Clock Generation Integrated Peripherals JTAG Boundary Scan Test Interface System Test Debug Features Applications Clock Generation Control Internal Clocks Clock Specifications Clock Loading Selecting Crystal 32.768-kHz Crystal Selection 33-MHz Crystal Selection. Third Overtone Crystal Component Selection Running Microcontroller 33.333 Bypassing Internal Oscillators Voltage Monitor Backup Battery Considerations Using External Backup Battery Using External Backup Battery. Absolute Maximum Ratings Operating Ranges Commercial Temperatures Voltage Levels Non-PCI Interface Pins Voltage Levels Interface Pins Characteristics Over Commercial Operating Ranges Capacitance Non-PCI Interface Capacitance Interface Capacitance Crystal Capacitance Derating Curves Power Characteristics Thermal Characteristics 388-Pin PBGA Package Switching Characteristics Waveforms Switching Waveforms
Microcontroller Data Sheet
Switching Test Waveforms Non-PCI Interface Pins Interface Pins Switching Characteristics over Commercial Operating Ranges Power-On Reset Timing Reset Timing with Power Applied Timing Timing SDRAM Timing SDRAM Clock Timing Timing Read Cycle Timing Write Cycle Timing Timing JTAG Timing Appendix Tables .A-1 List Summary Table Column Definitions Appendix Physical Dimensions .B-1 388-Pin Plastic (PBGA) Package .B-1 View .B-1 Bottom View .B-2 Circuit Board Layout Considerations .B-3 Appendix Customer Support .C-1 Related Documents .C-2 Additional Information .C-2 Customer Development Platform .C-2 Third-Party Development Support Products .C-2 Customer Service .C-3 Hotline World Wide Support. Corporate Applications Hotline. World Wide Home Page Documentation Literature Literature Ordering Index Index-1
LIST FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Microcontroller Block Diagram Microcontroller-Based Smart Residential Gateway Reference Design Microcontroller-Based Thin Client Reference Design Microcontroller-Based Digital Reference Design Microcontroller-Based Telephone Line Concentrator Reference Design System Clock Distribution Block Diagram Clock Source Block Diagram 32.768-kHz Crystal Circuit 33.333-MHz Third Overtone Crystal Implementation Bypassing 32.768-kHz Oscillator Bypassing 33-MHz Oscillator Voltage Monitor Block Diagram Circuit with Backup Battery Circuit without Backup Battery Drive 6-mA Rise Time
Microcontroller Data Sheet
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Drive 6-mA Fall Time Drive 12-mA Rise Time Drive 12-mA Fall Time Drive 24-mA Rise Time Drive 24-mA Fall Time Pads Rise Time with 1-ns Rise/Fall Pads Fall Time with 1-ns Rise/Fall Thermal Resistance (C/Watt) Thermal Characteristics Equations Switching Test Waveforms Power-Up Timing Sequence PWRGOOD Timing Standalone Mode External System Reset Timing with Power Applied PRGRESET Timing Internal System Reset Timing Non-Burst Read Cycle Timing Page-Mode Read Cycle Timing Flash Write Cycle Timing SDRAM Write Read Timing SDRAM Clock Timing Non-DMA Cycle Timing GP-DMA Read Cycle Timing GP-DMA Write Cycle Timing Timing JTAG Boundary Scan Timing Ball Layout .B-3
LIST TABLES
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Signal Descriptions Table Definitions. Signal Descriptions Clock Jitter Specifications Clock Startup Lock Times Oscillator Input Specifications Analog (VCC_ANLG) Specifications PLL1 Loop Filter Components Timing Error Translates Clock Accuracy 32.768-kHz Crystal Specifications 33-MHz Crystal Specifications Voltage Monitor Component Specifications Device Power Dissipation VCC_ANLG VCC_RTC Power Dissipation Thermal Resistance (°C/W) Package with 6-Layer Board Maximum Plastic Package with 6-Layer Board with TCASE 85°C Multiplexed Signal Trade-Offs .A-2 PIOs Sorted Number .A-4 PIOs Sorted Signal Name .A-5 List Summary Table Abbreviations .A-6 List Summary .A-7 Related Products-E86Family Devices .C-1
Microcontroller Data Sheet
LOGIC DIAGRAM INTERFACE1
GPA25-GPA0
GPD15-GPD0 AD31-AD0 CBE3-CBE0 SERR PERR FRAME TRDY IRDY STOP DEVSEL CLKPCIOUT CLKPCIIN INTA-INTD REQ4-REQ0 GNT4-GNT0 GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR GPALE GPBHE GPRDY GPAEN GPTC GPDRQ3-GPDRQ0 GPDACK3-GPDACK0 GPIRQ10-GPIRQ0 GPDBUFOE GPIOCS16 GPMEMCS16
SDRAM
MA12-MA0 BA1-BA0 MD31-MD0 SCS3-SCS0 CLKMEMOUT CLKMEMIN SRASA-SRASB SCASA-SCASB SWEA-SWEB SDQM3-SDQM0 MECC6-MECC0
GPCS7-GPCS0 GPA25-GPA0* GPD15-GPD0* MD31-MD0* BOOTCS ROMCS2-ROMCS1 ROMRD FLASHWR ROMBUFOE TMRIN1-TMRIN0 TMROUT1-TMROUT0
ROM/Flash
Timers
Serial Ports: UART UART
SOUT2-SOUT1 SIN2-SIN1 RTS2-RTS1 CTS2-CTS1 DSR2-DSR1 DTR2-DTR1 DCD2-DCD1 RIN2-RIN1 SSI_CLK SSI_DO SSI_DI
PITGATE2 PITOUT2 JTAG_TRST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS CMDACK BR/TC STOP/TX TRIG/TRACE WBMSTR2-WBMSTR0 CF_DRAM
JTAG
AMDebug
Programmable Input/Output Clocks Reset
PIO31-PIO0
System Test
32KXTAL2-32KXTAL1 33MXTAL2-33MXTAL1 LF_PLL1 CLKTIMER CLKTEST PWRGOOD PRGRESET BBATSEN
DATASTRB CF_ROM_GPCS DEBUG_ENTER INST_TRCE AMDEBUG_DIS CFG3-CFG0 RSTLD7-RSTLD0
Configuration
Notes: Pins noted with asterisks duplicated this diagram clarify which signals used each interface.
Microcontroller Data Sheet
LOGIC DIAGRAM DEFAULT FUNCTION1
AD31-AD0 CBE3-CBE0 SERR PERR FRAME TRDY IRDY STOP DEVSEL CLKPCIOUT CLKPCIIN INTA-INTD REQ4-REQ0 GNT4-GNT0 MA12-MA0 GPA25 {DEBUG_ENTER} GPA24 {INST_TRCE} GPA23 {AMDEBUG_DIS} GPA22-GPA15 {RSTLD7-RSTLD0} GPA13-GPA0 GPD15-GPD0 GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR PIO0 [GPALE] PIO1 [GPBHE] PIO2 [GPRDY] PIO3 [GPAEN] PIO4 [GPTC] PIO5-PIO8 [GPDRQ3-GPDRQ0] PIO9-PIO12 [GPDACK3-GPDACK0] PIO13-PIO23 [GPIRQ10-GPIRQ0] PIO24 [GPDBUFOE] PIO25 [GPIOCS16] PIO26 [GPMEMCS16] PIO27 [GPCS0]
SDRAM
BA1-BA0 MD31-MD0 SCS3-SCS0 CLKMEMOUT CLKMEMIN SRASA-SRASB SCASA-SCASB SWEA-SWEB SDQM3-SDQM0 MECC6-MECC0 SOUT2-SOUT1 SIN2-SIN1 RTS2-RTS1 CTS1 DSR1 DTR2-DTR1 DCD1 RIN1 PIO28 [CTS2] PIO29 [DSR2] PIO30 [DCD2] PIO31 [RIN2] SSI_CLK SSI_DO SSI_DI
GPA25-GPA0* GPD15-GPD0* MD31-MD0* BOOTCS ROMCS2-ROMCS1 [GPCS2-GPCS1] ROMRD
ROM/Flash
Serial Ports: UART UART
FLASHWR ROMBUFOE
TMRIN1-TMRIN0 [GPCS4-GPCS5] TMROUT1-TMROUT0 [GPCS6-GPCS7] PITGATE2 [GPCS3] PITOUT2 {CFG3}
Timers
JTAG_TRST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
JTAG
CMDACK BR/TC
AMDebug
Clocks Reset
32KXTAL2-32KXTAL1 32MXTAL2-32MXTAL1 LF_PLL1 CLKTIMER [CLKTEST] PWRGOOD PRGRESET BBATSEN
STOP/TX TRIG/TRACE
CF_DRAM [WBMSTR2] {CFG2} DATASTRB [WBMSTR1] {CFG1} CF_ROM_GPCS [WBMSTR0] {CFG0}
System Test
Notes: names bold indicate default function. Brackets, indicate alternate, multiplexed functions. Braces, indicate pinstrap pins. Pins noted with asterisks duplicated this diagram clarify which signals used each interface.
Microcontroller Data Sheet
CONNECTION DIAGRAM 388-Pin Plastic Package View
AD30 AD29 GPA6 AD31 AD28 GPA9 CLKMEMIN GPD1 CLKPCIOUT MD17 GPD4 MD18 GPD7 MD19 GPD8 MD20 GPD9 MD21 GPD10 CLKTIMER [CLKTEST] GPD2 MD16 GPD3
GPD0 GPA25 {DEBUG_ ENTER} GPA24 GPA23 {AMDEBUG {INST _TRCE} _DIS} VCC_CORE
AD26
AD27
VCC_I/O
VCC_I/O
VCC_I/O
VCC_I/O
GPD5
GPD6
VCC_CORE VCC_CORE GPD11
AD25 AD23
AD24 CBE3 AD21 AD20 AD17 AD16 IRDY TRDY PERR SERR AD15 AD14 AD11 AD10 CBE0
GPA22 VCC_CORE {RSTLD7} CLKPCIIN GPA1 INTC INTB INTA REQ0 GNT0 REQ1 GNT2 REQ3 GNT3 REQ4 CTS1 DTR1 INTD VCC_I/O VCC_I/O VCC_I/O VCC_I/O GNT1 REQ2 VCC_CORE VCC_CORE GNT4 DCD1 RTS1
AD22 AD19 AD18
CBE2 FRAME
DEVSEL STOP CBE1 AD13
AD12
DSR1 RIN1
VCC_I/O VCC_I/O VCC_CORE VCC_CORE VCC_CORE PIO12 PIO11 VCC_I/O PIO25 [GPDACK0] [GPDACK1] [GPIOCS16] PIO26 [GPMEMCS16] PIO27 [GPCS0] PIO28 [CTS2] PIO24 [GPDBUFOE] VCC_I/O TRIG/ TRACE
PIO31 [RIN2]
PIO19 PIO18 PIO13 PIO10 PIO5 PIO4 [GPIRQ4] [GPIRQ5] [GPIRQ10] [GPDACK2] [GPDRQ3] [GPTC]
SIN1 SOUT1
PIO30 [DCD2] PIO29 [DSR2]
PIO23 PIO20 PIO17 PIO14 PIO9 PIO6 PIO3 [GPIRQ0] [GPIRQ3] [GPIRQ6] [GPIRQ9] [GPDACK3] [GPDRQ2] [GPAEN] PIO22 PIO21 PIO16 PIO15 PIO8 PIO7 PIO2 [GPIRQ1] [GPIRQ2] [GPIRQ7] [GPIRQ8] [GPDRQ0] [GPDRQ1] [GPRDY]
PIO0 [GPALE] PIO1 [GPBHE]
Microcontroller Data Sheet
CONNECTION DIAGRAM (Continued) 388-Pin Plastic Package View
MD22 MD23 MD24 GPIOWR MD25 MD10 GPD14 MD11 MD26 MD27 MD28 MD13 MD29 MD14 MD30 MD31 GND_ANLG VCC_RTC
CLKMD12 MEMOUT
GPA18 MD15 {RSTLD3}
ROMCS1 BBATSEN VCC_ANLG [GPCS1] MECC4
GPA20 GPD13 {RSTLD5} GPD12 VCC_I/O
GPMEMWR GPA21 PWRGOOD GPA19 {RSTLD6} {RSTLD4} VCC_CORE VCC_CORE PRGRESET VCC_I/O VCC_I/O
MECC0 ROMCS2 GPA15 [GPCS2] {RSTLD0} GPA16 MECC5 {RSTLD1} GPA17 SWEB {RSTLD2} GPMEMRD SCASA SDQM0 SDQM3 SCS2 SRASA
VCC_I/O
GPD15
MECC1
GPA7
SWEA SCASB SDQM2 SDQM1 SCS3 SRASB MA10 MA11 MA12 MECC2
VCC_CORE GPIORD VCC_CORE GPA5 GPA3 VCC_I/O VCC_I/O GPA10 GPA11 GPA0 GPA2 GPA4 GPA8 GPA12
VCC_CORE GPA13 VCC_CORE GPA14 SOUT2 VCC_I/O VCC_I/O
CMDACK SIN2 SCS0
CF_DRAM SCS1 [WBMSTR2] {CFG2} PITOUT2 {CFG3} TMRIN1 [GPCS4] MECC3
VCC_CORE VCC_CORE VCC_I/O VCC_I/O TMRIN0 [GPCS5]
VCC_I/O VCC_I/O ROMRD
MECC6
ROMBUFOE
FLASHWR BOOTCS
33MXTAL1 33MXTAL2
PITGATE2 GPRESET TMROUT1 DATASTRB [GPCS3] [GPCS6] [WBMSTR1] {CFG1} TMROUT0 BR/TC [GPCS7]
SSI_CLK
CF_ROM_ JTAG_TCK RTS2 GPCS [WBMSTR0] {CFG0}
SSI_DI SSI_DO
JTAG_TMS JTAG_TRST DTR2 JTAG_TDI JTAG_TDO
LF_PLL1
32KXTAL2 32KXTAL1
STOP/TX
Microcontroller Data Sheet
DESIGNATIONS
This section identifies pins microcontroller lists signals associated with each pin. tables brackets, indicate alternate, multiplexed functions, braces, indicate reset configuration pins (pinstraps). line over name indicates active signal. word refers physical wire; word signal refers electrical signal that flows through
designations listed "Pin Designations
Refer Appendix "Pin Tables," page additional group tables with following information:
Multiplexed
signal
tradeoffs-Table
page A-2.
Programmable pins ordered
(Pin Number)" table page Designations (Pin Name) table page
Table "Signal Descriptions" page contains
respectively, including numbers, multiplexed functions, configuration following system reset-Table page Table page A-5.
Comprehensive signal summary showing
descr iption microcontroller signals organized alphabetically functional group. Table page defines terms used Table table includes columns listing multiplexed functions type.
signal name alternate function, number, type, maximum load values, power-on reset default function, reset state, power-on reset default operati e-Ta page A-7.
Microcontroller Data Sheet
Designations (Pin Number1)
Signal Name AD30 AD31 CLKMEMIN CLKPCIOUT CLKTIMER [CLKTEST] MD17 MD19 MD21 MD23 MD25 MD11 MD27 MD28 MD13 MD14 MD30 MD31 GND_ANLG VCC_RTC AD29 AD28 GPD1 MD16 MD18 MD20 MD22 MD24 MD10 MD26 Signal Name CLKMEMOUT MD12 MD29 GPA18{RSTLD3} MD15 ROMCS1[GPCS1] BBATSEN VCC_ANLG GPA6 GPA9 GPA25 {DEBUG_ENTER} GPD0 GPD2 GPD3 GPD4 GPD7 GPD8 GPD9 GPD10 GPA20{RSTLD5} GPD13 GPIOWR GPD14 GPMEMWR GPA21{RSTLD6} PWRGOOD GPA19{RSTLD4} ROMCS2[GPCS2] GPA15{RSTLD0} MECC0 MECC4 AD26 AD27 GPA23 {AMDEBUG_DIS} GPA24 {INST_TRCE} VCC_I/O VCC_I/O VCC_I/O VCC_I/O GPD5 GPD6 Signal Name VCC_CORE VCC_CORE GPD11 GPD12 VCC_I/O VCC_I/O GPD15 VCC_CORE VCC_CORE PRGRESET VCC_I/O VCC_I/O GPA16{RSTLD1} MECC5 MECC1 AD25 AD24 VCC_CORE GPA17{RSTLD2} SWEB SWEA AD23 CBE3 GPA22{RSTLD7} VCC_CORE GPA7 GPMEMRD SCASA SCASB AD22 AD21 CLKPCIIN GPA1 VCC_CORE GPIORD SDQM0 SDQM2 AD19 AD20 INTC INTD Signal Name VCC_CORE GPA5 SDQM3 SDQM1 AD18 AD17 INTB VCC_I/O GPA3 GPA0 SCS2 SCS3 CBE2 AD16 INTA VCC_I/O VCC_I/O GPA2 SRASA SRASB FRAME IRDY REQ0 VCC_I/O VCC_I/O GPA4 DEVSEL TRDY GNT0 VCC_I/O Signal Name GPA10 GPA8 STOP PERR REQ1 GNT1 GPA11 GPA12 SERR GNT2 REQ2 VCC_CORE GPA13 CBE1 AD15 REQ3 VCC_CORE VCC_CORE GPA14
Microcontroller Data Sheet
Designations (Pin Number1) (Continued)
Signal Name AD13 AD14 GNT3 VCC_CORE MA10 AD12 AD11 REQ4 GNT4 SOUT2 CMDACK MA11 AD10 CTS1 DCD1 VCC_I/O SIN2 SCS0 MA12 CBE0 AA23 AA24 AA25 AA26 AB23 AB24 AB25 AB26 Signal Name DTR1 RTS1 VCC_I/O CF_DRAM [WBMSTR2]{CFG2} SCS1 MECC2 DSR1 VCC_I/O VCC_I/O PITOUT2{CFG3} MECC3 MECC6 RIN1 VCC_I/O VCC_I/O TMRIN1[GPCS4] ROMBUFOE ROMRD FLASHWR BOOTCS 33MXTAL1 PIO25 [GPIOCS16] AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD10 AD11 AD12 Signal Name VCC_CORE VCC_CORE VCC_CORE PIO12 [GPDACK0] PIO11[GPDACK1] VCC_I/O VCC_I/O TRIG/TRACE VCC_CORE VCC_CORE VCC_I/O VCC_I/O TMRIN0[GPCS5] PITGATE2[GPCS3] GPRESET TMROUT1[GPCS6] DATASTRB [WBMSTR1]{CFG1} 33MXTAL2 PIO31[RIN2] PIO26 [GPMEMCS16] PIO24[GPDBUFOE] PIO19[GPIRQ4] PIO18[GPIRQ5] PIO13[GPIRQ10] PIO10[GPDACK2] PIO5[GPDRQ3] PIO4[GPTC] AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 Signal Name SSI_CLK CF_ROM_GPCS [WBMSTR0]{CFG0} JTAG_TCK RTS2 TMROUT0 [GPCS7] BR/TC SIN1 PIO30[DCD2] PIO27[GPCS0] PIO23[GPIRQ0] PIO20[GPIRQ3] PIO17[GPIRQ6] PIO14[GPIRQ9] PIO9[GPDACK3] PIO6[GPDRQ2] PIO3[GPAEN] PIO0[GPALE] SSI_DI AE21 AE22 AE23 AE24 AE25 AE26 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal Name JTAG_TMS JTAG_TRST DTR2 32KXTAL2 SOUT1 PIO29[DSR2] PIO28[CTS2] PIO22[GPIRQ1] PIO21[GPIRQ2] PIO16[GPIRQ7] PIO15[GPIRQ8] PIO8[GPDRQ0] PIO7[GPDRQ1] PIO2[GPRDY] PIO1[GPBHE] STOP/TX SSI_DO JTAG_TDI JTAG_TDO LF_PLL1 32KXTAL1
Notes: Table page PIOs sorted number.
Microcontroller Data Sheet
Designations (Pin Name1)
Signal Name 32KXTAL1 32KXTAL2 33MXTAL1 33MXTAL2 AF26 AE26 AB26 AC26 Signal Name {AMDEBUG_DIS} GPA23 BBATSEN BOOTCS BR/TC CBE0 CBE1 CBE2 CBE3 CF_DRAM [WBMSTR2]{CFG2} CF_ROM_GPCS [WBMSTR0]{CFG0} {CFG0} CF_ROM_GPCS [WBMSTR0] {CFG1}DATASTRB [WBMSTR1] {CFG2]CF_DRAM [WBMSTR2} {CFG3}PITOUT2 CLKMEMIN CLKMEMOUT CLKPCIIN CLKPCIOUT CLKTEST [CLKTIMER] [CLKTIMER] CLKTEST CMDACK CTS1 [CTS2]PIO28 DATASTRB [WBMSTR1]{CFG1} DCD1 [DCD2]PIO30 {DEBUG_ENTER} GPA25 DEVSEL DSR1 [DSR2]PIO29 DTR1 DTR2 FLASHWR FRAME AB25 AD24 AD20 AD20 Signal Name Signal Name GND_ANLG GNT0 GNT1 GNT2 GNT3 GNT4 GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 Signal Name [GPCS1]ROMCS1 [GPCS2]ROMCS2 [GPCS3]PITGATE2 [GPCS4]TMRIN1 [GPCS5]TMRIN0 [GPCS6]TMROUT1 [GPCS7]TMROUT0 GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 AC21 AA24 AC20 AC23 AD23
AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
AC24 AC24 AE23 AB24
GPA7 GPA8 GPA9 GPA10 GPA11 GPA12 GPA13 GPA14 GPA15{RSTLD0} GPA16{RSTLD1} GPA17{RSTLD2} GPA18{RSTLD3} GPA19{RSTLD4] GPA20{RSTLD5} GPA21[RSTLD6} GPA22{RSTLD7} GPA23 {AMDEBUG_DIS} GPA24 {INST_TRCE] GPA25 {DEBUG_ENTER] [GPAEN]PIO3 [GPALE]PIO0 [GPBHE]PIO1 [GPCS0]PIO27
AE11 AE12 AF12
GPD6 GPD7 GPD8 GPD9 GPD10 GPD11 GPD12 GPD13 GPD14 GPD15 [GPDACK0]PIO12 [GPDACK1]PIO11 [GPDACK2]PIO10 [GPDACK3]PIO9 [GPDBUFOE] PIO24 [GPDRQ0]PIO8 [GPDRQ1]PIO7 [GPDRQ2]PIO6 [GPDRQ3]PIO5 [GPIOCS16]PIO25 GPIORD GPIOWR [GPIRQ0]PIO23
AF10 AE10 AD10
Microcontroller Data Sheet
Designations (Pin Name1) (Continued)
Signal Name [GPIRQ1]PIO22 [GPIRQ2]PIO21 [GPIRQ3]PIO20 [GPIRQ4]PIO19 [GPIRQ5]PIO18 [GPIRQ6]PIO17 [GPIRQ7]PIO16 [GPIRQ8]PIO15 [GPIRQ9]PIO14 [GPIRQ10]PIO13 [GPMEMCS16] PIO26 GPMEMRD GPMEMWR [GPRDY]PIO2 GPRESET [GPTC]PIO4 {INST_TRCE} GPA24 INTA INTB INTC INTD IRDY JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST LF_PLL1 AF11 AC22 AD11 AD21 AF21 AF22 AE21 AE22 AF24 Signal Name MA10 MA11 MA12 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 Signal Name MD31 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 AA26 AC12 AC16 AC17 AC25 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD25 AD26 AE13 AE14 AE15 AE16 AE17 AE18 AE20 Signal Name PERR PIO0[GPALE] PIO1[GPBHE] PIO2[GPRDY] PIO3[GPAEN] PIO4[GPTC] PIO5[GPDRQ3] PIO6[GPDRQ2] PIO7[GPDRQ1] PIO8[GPDRQ0] PIO9[GPDACK3] PIO10[GPDACK2] PIO11[GPDACK1] AE24 AE25 AF13 AF14 AF15 AF16 AF18 AF20 AF23 AF25 AE12 AF12 AF11 AE11 AD11 AD10 AE10 AF10 Signal Name PIO12[GPDACK0] PIO13[GPIRQ10] PIO14[GPIRQ9] PIO15[GPIRQ8] PIO16[GPIRQ7] PIO17[GPIRQ6] PIO18[GPIRQ5] PIO19[GPIRQ4] PIO20[GPIRQ3] PIO21[GPIRQ2] PIO22[GPIRQ1] PIO23[GPIRQ0] PIO24 [GPDBUFOE] PIO25 [GPIOCS16] PIO26 [GPMEMCS16] PIO27[GPCS0] PIO28[CTS2] PIO29[DSR2] PIO30[DCD2] PIO31[RIN2] PITGATE2 [GPCS3] PITOUT2{CFG3} PRGRESET PWRGOOD REQ0 REQ1 REQ2 REQ3 REQ4 RIN1 [RIN2]PIO31 ROMBUFOE ROMCS1[GPCS1] ROMCS2 [GPCS2 ROMRD AC21 AA25 AB23
Microcontroller Data Sheet
Designations (Pin Name1) (Continued)
Signal Name {RSTLD0}GPA15 {RSTLD1}GPA16 {RSTLD2}GPA17 {RSTLD3}GPA18 {RSTLD4}GPA19 {RSTLD5}GPA20 {RSTLD6}GPA21 {RSTLD7}GPA22 RTS1 RTS2 SCASA SCASB SCS0 SCS1 SCS2 SCS3 SDQM0 AD22 Signal Name SDQM1 SDQM2 SDQM3 SERR SIN1 SIN2 SOUT1 SOUT2 SRASA SRASB SSI_CLK SSI_DI SSI_DO STOP STOP/TX SWEA SWEB AD19 AE19 AF19 AF17 Signal Name TMRIN0[GPCS5] TMRIN1[GPCS4] TMROUT0 [GPCS7] TMROUT1 [GPCS6] TRDY TRIG/TRACE VCC_ANLG VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE AC20 AA24 AD23 AC23 AC13 AC14 AC15 Signal Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O AA23 AC10 AC11 AC18 AC19 Signal Name VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_RTC [WBMSTR0]{CFG0} CF_ROM_GPCS [WBMSTR1]{CFG1} DATASTRB [WBMSTR2]{CFG2} CF_DRAM AD20 AC24
Notes: Table page PIOs sorted number.
Microcontroller Data Sheet
SIGNAL DESCRIPTIONS
Table "Signal Descriptions" page contains description microcontroller signals. microcontroller contains signal pins addition power ground pins Plastic Ball Grid Array (PBGA) package. Table describes terms used signal description table. signals organized alphabetically within following functional groups:
Synchronous DRAM (page ROM/Flash (page (page (page Serial ports (page Clocks reset (page JTAG (page AMDebugInterface (page System test (page Chip selects (page Programmable (PIO) (page Timers (page Configuration (page Power (page
Table
Term
Signal Descriptions Table Definitions
Definition Indicates alternate function; defaults signal named without brackets. Indicates reset configuration (pinstrap). Refers physical wire. Refers electrical signal that flows across pin. line over signal name indicates that signal active Low; signal name without line active High. Analog voltage Bidirectional High Input Programmable hold last state Totem pole output Totem pole output/three-state output Open-drain output Open-drain output totem pole output Oscillator Internal pulldown resistor (~100-150 Power pins Internal pullup resistor (~100-150 Schmitt trigger input Schmitt trigger input open-drain output Three-state output
General Terms
signal SIGNAL
Signal Types Analog O/TS OD-O Power STI-OD
Microcontroller Data Sheet
Table Signal Descriptions
Signal Synchronous DRAM BA1-BA0 CLKMEMIN Bank Address SDRAM bank address bus. SDRAM Clock Input SDRAM clock return signal used minimize skew between internal SDRAM clock CLKMEMOUT signal provided SDRAM devices. This signal compensates buffer load delays introduced board design. SDRAM Clock Output 66-MHz clock that provides clock signaling synchronous DRAM devices. This clock require external skew buffer system implementations that result heavy loading SDRAM clock signal. SDRAM Address SDRAM multiplexed address bus. SDRAM Data inputs data during SDRAM read cycles outputs data during SDRAM write cycles. Memory Error Correction Code contains checksum (syndrome) bits used validate correct data errors. Column Address Strobes used combination with SRASA- SRASB SWEA-SWEB encode SDRAM command type. SCASA SCASB same signal provided different pins reduce total load connected CAS. Suggested system connection: SCASA SDRAM banks SCASB SDRAM banks SCS3-SCS0 SDRAM Chip Selects SDRAM chip-select outputs. These signals asserted select bank SDRAM devices. chipselect signals enable SDRAM devices decode commands asserted SRASA-SRASB, SCASA-SCASB, SWEA-SWEB. Data Input/Output Masks make SDRAM data output high-impedance blocks data input SDRAM while active. Each four SDQM3-SDQM0 signals associated with byte four throughout array. Each SDQMx signal provides input mask signal write accesses output enable signal read accesses. Address Strobes used combination with SCASA- SCASB SWEA-SWEB encode SDRAM command type. SRASA SRASB same signal provided different pins reduce total load connected RAS. Suggested system connection: SRASA SDRAM banks SRASB SDRAM banks SWEA-SWEB SDRAM Memory Write Enables used combination with SRASA-SRASB SCASA-SCASB encode SDRAM command type. SWEA SWEB same signal provided different pins reduce total load connected Suggested system connection: SWEA SDRAM banks SWEB SDRAM banks Multiplexed Signal Type Description
CLKMEMOUT
MA12-MA0 MD31-MD0 MECC6-MECC0 SCASA-SCASB
SDQM3-SDQM0
SRASA-SRASB
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal ROM/Flash BOOTCS ROM/Flash Boot Chip Select active output that provides chip select startup and/or ROM/Flash array (BIOS, HAL, O/S, etc.). BOOTCS signal asserts accesses made 64-Kbyte segment that contains Am5x86 boot vector: addresses 3FF0000h-3FFFFFFh. addition this linear decode region, BOOTCS asserts response accesses userprogrammable address regions. Flash Write indicates that current cycle write selected Flash device. When this signal asserted, selected Flash device latch data from data bus. General-Purpose Address provides address system's ROM/Flash devices. also address devices. Twenty-six address lines provide maximum addressable space Mbytes each chip select. General-Purpose Data inputs data during memory read cycles outputs data during memory write cycles. reset configuration (CFG2) allows used boot chip-select interface. Configuration registers used select whether ROMCS2 ROMCS1 data data bus. data supports 16-bit 8-bit interfaces. data buses selectable facilitate mixed voltage system. MD31-MD0 Memory Data inputs data during SDRAM read cycles outputs data during SDRAM write cycles. Configuration registers used select whether ROMCS2 ROMCS1 data data bus. reset configuration (CFG2) allows data used BOOTCS. memory data supports 16-, 32-bit interface. Buffer Output Enable optional signal used enable buffer ROM/Flash devices they need isolated from microcontroller, other devices, SDRAM system voltage loading considerations. This signal asserts accesses through controller. buffer direction controlled ROMRD FLASHWR signal. ROM/Flash Chip Selects signals that programmed asserted accesses user-programmable address regions. ROM/Flash Read indicates that current cycle read selected ROM/Flash device. When this signal asserted, selected device drive data onto data bus. Address Data time-multiplexed address/data bus. Command Byte-Enable functions time-multiplexed command that defines type transaction bus, byte enables: CBE0 AD7-AD0 CBE1 AD15-AD8 CBE2 AD23-AD16 CBE3 AD31-AD24 Clock Input 33-MHz clock. This connected CLKPCIOUT systems where microcontroller source clock. Multiplexed Signal Type Description
FLASHWR
GPA25-GPA0
GPD15-GPD0
ROMBUFOE
ROMCS2 ROMCS1 ROMRD
[GPCS2] [GPCS1]
Peripheral Component Interconnect (PCI) AD31-AD0 CBE3-CBE0
CLKPCIIN
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal CLKPCIOUT Multiplexed Signal Type Description Clock Output 33-MHz clock output devices. This signal derived from 33MXTAL1/33MXTAL2 interface. Device Select asserted target when decoded address target current transaction. Frame driven transaction initiator indicate start duration transaction. Grants asserted microcontroller grant access bus. Interrupt Requests asserted request interrupt. These four interrupts same type interrupt GPIRQ10-GPIRQ0 signals, they same interrupt controller. They named INTx match common interrupt naming convention. Configuration registers allow inversion these interrupt requests recognize active interrupt requests. These interrupt requests routed generate NMI. IRDY Initiator Ready asserted current master indicate that data ready (write) that master ready accept data (read). Parity driven initiator target indicate parity AD31-AD0 CBE3-CBE0 buses. Parity Error asserted indicate data parity error previous clock cycle. Requests asserted master request access bus. Reset asserted reset devices. System Error used reporting address parity errors other system error where result catastrophic. Stop asserted target request that current transaction stopped. Target Ready asserted currently addressed target indicate ability complete current data phase transaction. General-Purpose Address outputs physical memory port address. Twenty-six address lines provide maximum addressable space Mbytes. This also provides address system's ROM/Flash devices.
DEVSEL FRAME GNT4-GNT0 INTA-INTD
PERR REQ4-REQ0 SERR STOP TRDY
General-Purpose Bus) GPA14-GPA0 GPA15 GPA16 GPA17 GPA18 GPA19 GPA20 GPA21 GPA22 GPA23 GPA24 GPA25 {RSTLD0} {RSTLD1} {RSTLD2} {RSTLD3} {RSTLD4} {RSTLD5} {RSTLD6} {RSTLD7} {AMDEBUG_DIS} {INST_TRCE} {DEBUG_ENTER} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I}
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal [GPAEN] Multiplexed Signal PIO3 Type Description Address Enable indicates that current address GPA25-GPA0 address memory address, that current cycle cycle. devices should this signal decoding their addresses should respond when this signal asserted. When GPAEN asserted, GPDACKx signals used select appropriate device transfer. GPAEN also asserts when cycle occurring internally. Address Latch Enable driven beginning cycle with valid address. This signal used external devices latch address current cycle. Byte High Enable driven active when data transferred upper bits data bus. General-Purpose Data inputs data during memory read cycles, outputs data during memory write cycles. Acknowledge each mapped seven available channels. They asserted active acknowledge corresponding requests.
[GPALE]
PIO0
[GPBHE] GPD15-GPD0 [GPDACK0] [GPDACK1] [GPDACK2] [GPDACK3] [GPDBUFOE]
PIO1 PIO12 PIO11 PIO10 PIO9 PIO24
Data Buffer Output Enable used control output enable external transceiver that data bus. Using this transceiver optional system design necessary only alleviate loading voltage issues. This asserted external accesses. asserted during accesses internal peripherals even echo mode enabled. Note that configured data bus, then bytes controlled this buffer enable; they controlled ROMBUFOE signal.
[GPDRQ0] [GPDRQ1] [GPDRQ2] [GPDRQ3] [GPIOCS16] GPIORD
PIO8 PIO7 PIO6 PIO5 PIO25
Request each mapped seven available channels. They asserted active High request service.
Chip-Select driven active early cycle targeted device request 16-bit transfer. Read indicates that current cycle read currently addressed device bus. When this signal asserted, selected device drive data onto data bus. Write indicates that current cycle write currently addressed device bus. When this signal asserted, selected device latch data from data bus.
GPIOWR
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal [GPIRQ0] [GPIRQ1] [GPIRQ2] [GPIRQ3] [GPIRQ4] [GPIRQ5] [GPIRQ6] [GPIRQ7] [GPIRQ8] [GPIRQ9] [GPIRQ10] [GPMEMCS16] Multiplexed Signal PIO23 PIO22 PIO21 PIO20 PIO19 PIO18 PIO17 PIO16 PIO15 PIO14 PIO13 PIO26 Type Memory Chip-Select driven active early cycle targeted memory device request 16-bit memory transfer. Memory Read indicates that current cycle read selected memory device. When this signal asserted, selected memory device drive data onto data bus. Memory Write indicates that current cycle write selected memory device. When this signal asserted, selected memory device latch data from data bus. Ready driven open-drain devices. When pulled during access, wait states inserted current cycle. This internal weak pullup that should supplemented stronger external pullup faster rise time. Reset, when asserted, re-initializes reset state devices connected bus. Terminal Count driven from internal controller indicate that transfer count currently active channel reached zero, that current cycle last transfer. Clear Send driven back serial port indicate that external data carrier equipment (DCE) ready accept data. Data Carrier Detect driven back serial port from piece when detected carrier signal from communications target. Data Ready used indicate that external ready establish communication link with internal serial port controller. Data Terminal Ready indicates external that internal serial port controller ready communicate. Ring Indicate used external modem inform serial port that ring signal detected. Request Send indicates external that internal serial port controller ready send data. Serial Data used receive serial data from external serial device into internal serial port controller. Serial Data used transmit serial data from internal serial port controller external serial device DCE. Description Interrupt Request each mapped available interrupt channels NMI. They asserted when peripheral requires interrupt service. Configuration registers allow inversion these interrupt requests recognize active interrupt requests. These interrupt requests routed generate NMI.
[GPMEMRD]
[GPMEMWR]
[GPRDY]
PIO2
GPRESET [GPTC] PIO4
Serial Ports CTS1 [CTS2] DCD1 [DCD2] DSR1 [DSR2] DTR2-DTR1 RIN1 [RIN2] RTS2-RTS1 SIN2-SIN1 SOUT2-SOUT1 PIO31 PIO29 PIO30 PIO28
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal SSI_CLK Multiplexed Signal Type Description Clock driven microcontroller port during active transmit receive transactions. idle state clock assertion/sample edge configurable. Data Input receives incoming data from peripheral device port. Data shifted opposite SSI_CLK signal edge which SSI_DO drives data. SSI_DO SSI_DI tied together interface three-pin peripheral. Data Output drives data peripheral device port. Data driven opposite SSI_CLK signal edge which SSI_DI latches data. signal normally high-impedance when transmit transaction active port. 32.768-kHz Crystal Interface used connecting external crystal oscillator microcontroller. This clock source used clock real-time clock (RTC). addition, internal PLLs generate clocks timers UARTs based this clock source. When external oscillator used, 32KXTAL1 should grounded clock source driven 32KXTAL2. 33MXTAL2- 33MXTAL1 33-MHz Crystal Interface main system clock chip. This clock source used derive SDRAM, CPU, clocks. When external oscillator used, 33MXTAL1 should unconnected clock source driven 33MXTAL2. [CLKTEST] CLKTIMER Test Clock Output shared that allows many internal clocks driven externally. CLKTEST drive internal clocks UARTs, PLL1, PLL2, programmable interval timer (PIT), real-time clock (RTC) testing driving external device. Timer Clock Input shared clock that used input frequency programmable interval timer (PIT). Loop Filter Interface used connecting external loop filter components. Component values circuit descriptions contained "Clock Generation Control" page Programmable Reset programmed reset microcontroller, allow SDRAM refresh continue during reset. This allows system reset without losing information stored SDRAM. power-up, PRGRESET disabled must programmed operational. When disabled, this effect microcontroller. PWRGOOD Power Good reset signal that indicates microcontroller that levels within normal operation range. used reset entire chip must held second after signals (except VCC_RTC) chip High. This signal must returned before signals degrade into correct state operation RTC-only mode.
SSI_DI
SSI_DO
Clocks Reset 32KXTAL2- 32KXTAL1
CLKTIMER LF_PLL1
[CLKTEST]
PRGRESET
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal JTAG JTAG_TCK JTAG_TDI Test Clock input clock test access port. Test Data Input serial input stream input data. This weak internal pullup resistor. sampled rising edge JTAG_TCK. driven, this input sampled High internally. Test Data Output serial output stream result data. high-impedance state except when scanning progress. Test Mode Select input controlling test access port. This weak internal pullup resistor. driven, sampled High internally. JTAG Reset test access port (TAP) reset. This weak internal pulldown resistor. driven, this input sampled internally causes controller logic remain reset state. Break Request/Trace Capture requests entry AMDebug technology mode. AMDebug technology serial/parallel interface reconfigure this turn instruction trace capture off. Command Acknowledge indicates command completion status. asserted High when in-circuit emulator logic ready receive commands from host. driven when in-circuit emulator core executing command from host remains until command completed. Stop/Transmit asserted High entry AMDebug mode. During normal mode, this High when there data transmitted host (during operating system/application communication). Trigger/Trace triggers events logic analyzer (optional, from Am5x86 debug registers) indicates trace status. AMDebug technology used enable configure this pin. Code Fetch SDRAM, during SDRAM reads, provides code fetch status. When Low, this indicates that current SDRAM read code fetch demanded CPU, read prefetch initiated demand code fetch CPU. When High during reads, this indicates that SDRAM read code fetch, could have been initiated CPU, master, GP-DMA controller, either demand prefetch. During SDRAM write cycles this provides indication source data, either GP-DMA controller/PCI master CPU. When High, this indicates that either initiator external master contributed current SDRAM write cycle (the also have contributed). indicates that only master that contributed this write cycle. CF_ROM_GPCS [WBMSTR0] {CFG0} O{I} Code Fetch ROM/GPCS provides indication that performing code fetch from either SDRAM data bus), from GPCSx pin. When during read cycle indicated either GPMEMRD ROMRD), performing code fetch from chip select. other times (including writes), this signal High. Data Strobe debug signal that asserted allow external system latch SDRAM data. This used trace data SDRAM interface with in-circuit emulator probe logic analyzer. Multiplexed Signal Type Description
JTAG_TDO JTAG_TMS
O/TS
JTAG_TRST
AMDebug Interface BR/TC
CMDACK
STOP/TX
TRIG/TRACE
System Test CF_DRAM [WBMSTR2] {CFG2} O{I}
DATASTRB
[WBMSTR1] {CFG1}
O{I}
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal [WBMSTR0] Multiplexed Signal CF_ROM_GPCS {CFG0} Type O{I} Description Write Buffer Master indicates which block(s) wrote rank write buffer (during SDRAM write cycles) which block reading from SDRAM (during SDRAM read cycles). WBMSTR0, when logical indicates that internal controller contributed write buffer rank (write cycles) reading from SDRAM (read cycles). [WBMSTR1] DATASTRB {CFG1} CF_DRAM {CFG2} O{I} WBMSTR1, when logical indicates that master contributed write buffer rank (write cycles) reading from SDRAM (read cycles). WBMSTR2, when logical indicates that contributed write buffer rank (write cycles) reading from SDRAM (read cycles). General-Purpose Chip Select signals bus. They used either memory accesses. These chip selects asserted Am5x86 accesses corresponding regions Programmable Address Region (PAR) registers.
[WBMSTR2]
O{I}
Chip Selects [GPCS0] [GPCS1] [GPCS2] [GPCS3] [GPCS4] [GPCS5] [GPCS6] [GPCS7] PIO27 ROMCS1 ROMCS2 PITGATE2 TMRIN1 TMRIN0 TMROUT1 TMROUT0
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal Multiplexed Signal [GPALE] [GPBHE] [GPRDY] [GPAEN] [GPTC] [GPDRQ3] [GPDRQ2] [GPDRQ1] [GPDRQ0] [GPDACK3] [GPDACK2] [GPDACK1] [GPDACK0] [GPIRQ10] [GPIRQ9] [GPIRQ8] [GPIRQ7] [GPIRQ6] [GPIRQ5] [GPIRQ4] [GPIRQ3] [GPIRQ2] [GPIRQ1] [GPIRQ0] [GPDBUFOE] [GPIOCS16] [GPMEMCS16] [GPCS0] [CTS2] [DSR2] [DCD2] [RIN2] [GPCS3] {CFG3} [GPCS5] [GPCS4] [GPCS7] [GPCS6] Type Description
Programmable (PIO) PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 Timers PITGATE2 PITOUT2 TMRIN0 TMRIN1 TMROUT0 TMROUT1 O{I} Programmable Interval Timer Gate provides control Channel Programmable Interval Timer Output output from Channel This signal typically used speaker signal. Timer Inputs programmed control clock general-purpose (GP) timers Timer Outputs outputs from timers. These outputs used pulse-width modulation signals. Programmable Input/Output signals programmed inputs outputs. When they outputs, they driven High programming bits registers.
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal Configuration {AMDEBUG_DIS} GPA23 AMDebug Disable active High configuration signal latched assertion Power Good (PWRGOOD). This built-in pulldown resistor. Power Good assertion: Normal operation, mode enabled software. High AMDebug mode disabled cannot enabled software. {CFG0} CF_ROM_GPCS [WBMSTR0] Configuration Inputs latched into chip when PWRGOOD asserted. These signals shared with other features. These signals have built-in pulldown resistors. CFG0: Choose 16-, 32-bit ROM/Flash interface BOOTCS. {CFG1} DATASTRB [WBMSTR1] CFG1: Choose 16-, 32-bit ROM/Flash interface BOOTCS. CFG1 {CFG2} CF_DRAM [WBMSTR2] CFG0 (don't care) BOOTCS Data Width 8-bit 16-bit 32-bit Multiplexed Signal Type Description
CFG2: When when PWRGOOD asserted, microcontroller uses data BOOTCS. When seen High during PWRGOOD assertion, BOOTCS access across SDRAM data bus. Default built-in pulldown resistor). CFG3 (Internal test mode enable): normal microcontroller operation, pull High during reset. Enter AMDebug Mode active High configuration signal latched assertion Power Good (PWRGOOD). This enables AMDebug mode, which causes processor fetch execute instruction from BOOTCS device, then enter AMDebug mode where waits debug commands delivered JTAG port. This built-in pulldown resistor. PWRGOOD assertion: High AMDebug mode enabled Normal operation
{CFG3} {DEBUG_ENTER}
PITOUT2 GPA25
{INST_TRCE}
GPA24
Instruction Trace active High configuration signal latched assertion Power Good (PWRGOOD). Enables trace record generation from Power Good assertion. This built-in pulldown resistor. PWRGOOD assertion: High Trace controller enabled output trace records Normal operation
Microcontroller Data Sheet
Table Signal Descriptions (Continued)
Signal {RSTLD0} {RSTLD1} {RSTLD2} {RSTLD3} {RSTLD4} {RSTLD5} {RSTLD6} {RSTLD7} Power BBATSEN Analog Backup Battery Sense which real-time clock (RTC) backup battery voltage sampled each time PWRGOOD asserted. this samples below Valid Time (VRT) index cleared until read. After read, until BBATSEN sensed subsequent PWRGOOD assertion. BBATSEN also provides power-on-reset signal when backup battery applied first time. Analog Power Supply analog circuits (PLLs). Power Supply microcontroller core logic. Power Supply ring. Power Supply real-time clock 32-kHz oscillator. Digital Ground remaining microcontroller core logic. Analog Ground analog circuits. Multiplexed Signal GPA15 GPA16 GPA17 GPA18 GPA19 GPA20 GPA21 GPA22 Type Description Reset Latched Inputs shared signals that latched into register when PWRGOOD asserted. They used input static information software (i.e., board revision). These signals have builtin pulldown resistors.
VCC_ANLG VCC_CORE VCC_I/O VCC_RTC GND_ANLG
Power Power Power Power Power Power
Microcontroller Data Sheet
ARCHITECTURAL OVERVIEW
microcontroller designed provide:
balanced high performance low-cost industry-standard, 32-bit provided
interface mechanisms
high-performance, industry-standard 32-bit Glueless interfacing many 16-bit
high bandwidth peripherals such local area network controllers, synchronous communications controllers, disk storage controllers.
simple 8/16-bit, 33-MHz general-purpose
ripherals 16-bit with programmable timing
cost-effective system architecture that meets
bus) provides glueless connection lower bandwidth peripherals NVRAM, SRAM, ROM, custom ASICs; supports dynamic sizing compatibility with many common devices. These three buses listed above provided operating modes microcontroller. addition these three primary interfaces, microcontroller also contains internal oscillator circuitry phase locked loop (PLL) circuitry, requiring only simple crystals virtually system clock generation. Diagrams showing microcontroller used various system designs included "Applications" page
wide range performance criteria while retaining lower cost 32-bit system
high degree leverage from present hard-
ware software technologies Figure page illustrates integrated Am5x86 CPU, structure, on-chip peripherals microcontroller. Three primary interfaces provided:
high-performance, 66-MHz, 32-bit synchronous
DRAM (SDRAM) interface Mbytes used Am5x86 code execution, well buffer storage external masters initiators. high-performance ROM/Flash interface also connected SDRAM interface.
Microcontroller Data Sheet
Address
SDRAM Controller Interface Address Decode Unit Read/Write Buffers ROM/Flash Controller
Interface Unit
Data
AMDebugTechnology JTAG
Control/Status
GP-DMA Controller
Controller
Control/Status
Request
Address
GP-DMA Request Grant
Clock Generation External Programmable Interrupt Controller Programmable Interval Timer
Data
Interface Arbiter
Watchdog Timer FIFOs FIFO Control Real-Time Clock CMOS
Arbiter
Master
Target
General-Purpose Timers Software Timer
16550 UART
16550 UART
Requests Grants
Synchronous Serial Interface Programmable Controls PC/AT Compatibility Logic
Microcontroller
Figure
Microcontroller Block Diagram
Microcontroller Data Sheet
Industry-Standard Architecture
Am5x86 microcontroller utilizes industry-standard microprocessor instruction that enables compatibility across variety performance levels from 16-bit Am186processors high-end Athlonprocessor. Software itten architecture family compatible with microcontroller. Other benefits Am5x86 include:
Improved time-to-market easy software migra-
lator manufacturers. parallel AMDebug port greatly simplifies task supporting high speed data exchange.
Industry-Standard Interface
microcontroller provides 33-MHz, 32-bit Revision 2.2-compliant host bridge interface, including integrated write-posting readbuffering capabilities suitable high-throughput applications. host bridge leverages standard peripherals software. also provides:
High throughput (132 Mbytes/s peak transfer rate) Deep buffering support burst transactions
tion
Existing availability multiple operating systems
that directly support architecture. Whether application requires real-time operating system (RTOS) popular Microsoft® operating systems, microcontroller provides consistent compatibility with many off-theshelf operating systems.
Multiple sources field-proven development tools Integrated floating point unit (FPU) (compliant with
from masters SDRAM
Flexible arbitration mechanism Support five external masters
High-Performance SDRAM Controller
microcontroller provides integrated SDRAM controller that supports popular industry-standard synchronous DRAMs (SDRAM).
SDRAM controller interfaces with SDRAM
ANSI/IEEE standard)
16-KByte unified cache configurable either write-
back write-through cache mode
AMDebugTechnology Advanced Debugging
microcontroller provides support low-cost, full-featured, in-circuit emulation capability. This in-circuit emulation support developed specifically enable users test debug their software earlier design cycle. Utilizing this capability, software more extensively exercised, full execution speeds. also allows tracing during execution from Am5x86 CPU's internal cache. AMDebug technology provides product design team with different communication paths microcontroller, each which supported powerful debug tools from third-party vendors AMD's FusionE86SM program.
Serial AMDebug technology uses serial connec-
chips well with most standard DIMMs enable standard off-the-shelf memory components.
SDRAM controller supports programmable tim-
options provides required external clock.
four 32-bit banks SDRAM supported
with maximum capacity Mbytes.
important reliability-enhancing Error Correction
Code (ECC) feature built into SDRAM controller. resultant increase memory content reliability enables microcontroller effectively utilized applications that require more reliable operation, such communications environments.
SDRAM controller contains write buffer
read ahead buffer subsystem that improves both write read performance.
SDRAM refresh options allow SDRAM contents
tion based enhanced JTAG protocol inexpensive 12-pin connector that placed each board design. This low-cost solution satisfies requirement large number software developers.
Parallel AMDebug technology uses parallel debug
maintained during reset.
ROM/Flash Controller
microcontroller provides integrated controller glueless interfacing Flash devices. microcontroller supports types interfaces such devices-a simple interface (see "Easy-to-Use Interface" page 16-bit devices, interface SDRAM memory data higher performance 16-, 32-bit devices.
port exchange commands data between microcontroller host. higher count requires that extra signal pins provided special bond-out package microcontroller, which only made available tool developers such in-circuit emu-
Microcontroller Data Sheet
ROM/Flash controller:
Reduces system cost gluelessly interfacing
Clock Generation
microcontroller offers user-configurable core clock speed operation different power/performance points depending application. microcontroller devices support clock rates. maximum supported clock rate device indicated part number printed package. clocking circuitry programmed device higher than rated speeds. However, microcontroller programmed higher clock speed than that which rated, then erroneous operation result, physical damage device occur. microcontroller includes on-chip oscillators PLLs, well most required loop filter components. microcontroller requires standard crystals, 32.768 MHz. clocks required inside microcontroller generated from these crystals. microcontroller also supplies clocks SDRAM bus; however, external clock buffering required some systems.
static memory with three ROM/Flash chip selects
Supports execute-in-place (XIP) operating systems
applications that require executing Flash memory instead DRAM
Supports high-performance page-mode devices
Flexible Address-Mapping Hardware
addition memory management unit (MMU) within Am5x86 core, microcontroller provides Programmable Address Region (PAR) registers that enable flexible placement memory (SDRAM, ROM, Flash, SRAM, etc.) peripherals into address spaces Am5x86 (memory address space address space). hardware allows designers flexibly configure both address spaces place memory and/or external peripherals, required application. internal memory-mapped configuration registers space also remapped accommodate system requirements. registers also allow control important attributes, such cacheability, write protection, code execution protection memory resources.
Easy-to-Use Interface
microcontroller includes simple general-purpose bus) that provides programmable timing allows connection 8/16-bit peripheral devices memory microcontroller. operates MHz, which offers good performance very interface cost. microcontroller provides eight chip selects external devices such offthe-shelf peripherals, custom ASICs, SRAM NVRAM. interface supports programmable timing dynamic width cycle stretching accommodate wide variety standard peripherals, such UARTs, 10-Mbit controller chips serial communications controllers. four external channels provide fly-by transfers between peripheral devices system SDRAM. Internally, used provide complement integrated peripherals, such controller, programmable interrupt controller, timers, UARTs, described "Integrated Peripherals" page These internal peripherals designed operate full clock rate bus. internal peripherals also configured operate PC/AT-compatible configuration, generally restricted this configuration. microcontroller provides view accesses internal peripherals external debugging purposes.
Note: microcontroller supports either 33.000-MHz 33.333-MHz crystal. this document, generic term MHz" refers system clock derived from whichever 33-MHz crystal frequency being used system.
Integrated Peripherals
microcontroller highly integrated single-chip with integrated peripherals that superset common PC/AT peripherals, plus memory-mapped peripherals that enhance usability various applications.
programmable interrupt controller (PIC) that pro-
vides capability prioritize interrupt levels, these being external sources. programmed operate PC/AT-compatible mode, also contains extended features, including support more sources flexible routing that allows interrupt request steered input. Interrupt requests programmed generate either non-maskable interrupt (NMI) maskable interrupt requests.
integrated controller included trans-
ferring data between SDRAM peripherals. GP-DMA controller operates single-cycle (fly-by) mode more efficient transfers. GPDMA controller programmed PC/AT compatibility, also contains enhanced features: double buffer-chaining mode provides more efficient software interface Extended address transfer counts Flexible routing channels
Microcontroller Data Sheet
Three general-purpose 16-bit timers that provide
JTAG Boundary Scan Test Interface
microcontroller provides JTAG test port that compliant with IEEE 1149.1 during board testing.
flexible cascading extension 32-bit operation. These timers provide ability configure down resolution four clock periods where clock period 33-MHz clock. Timer input output pins provide ability interface with offchip hardware.
standard PC/AT-compatible programmable inter-
System Test Debug Features
facilitate debugging, microcontroller provides observability many portions internal operation, including:
three-pin interface that used either sys-
timer (PIT) that consists three 16-bit timers.
software timer that eases task keeping sys-
time. provides 1-ms resolution also used performance monitoring.
watchdog timer guard against runaway soft-
ware.
real-time clock (RTC) with battery backup capa-
test mode write buffer test mode, determining internal initiators SDRAM cycles, determining when SDRAM data valid interface. additional mode provides observability integrated peripheral accesses.
nonconcurrent arbitration mode reduce debug
bility. also provides bytes batterybacked storage configuration parameters.
integrated 16550-compatible UARTs that pro-
complexity when masters initiators also accessing SDRAM.
cache control dynamic core clock speed
vide full handshaking capability with eight pins each. Enhancements enable UARTs operate baud rates 1.152 Mbits/s. UARTs configured integrated controller transfer data between serial ports SDRAM.
synchronous serial interface (SSI) that compat-
control under program control.
Ability disable write posting read prefetching
SDRAM controller simplify tracing SDRAM cycles.
Notification memory write protection non-ex-
ecutable memory region violations.
ible with SCP, SPI, Microwire slave devices. interface configured either fullduplex half-duplex operation using 4-wire 3-wire interface.
programmable pins provided. These pins
multiplexed with other peripherals interface functions.
microcontroller also provides
AT-compatible functions control gate soft reset (Por 0060h, 0064h, 0092h).
Microcontroller Data Sheet
APPLICATIONS
lowi microcontroller might used several reference design applications data commun telecommunication markets.
Figure page shows micros Figure page shows micro-
controller-based Smart Resident Gateway (SRG), which router home network between wide area network (WAN) (the internet) local area network (LAN) intranet computers information appliances home). provides firewall protection from unauthorized access through internet. common internet access medium shared users LAN. variety connections possible both LAN. example, connection V.90 modem, cable modem, ISDN, ADSL, Ethernet. connection HomePNA-Home Phoneline Networking Alliance, alliance with widely endorsed home networking specification; Bluetooth-a computing telecommunications industry specification that describes computing devices easily interconnect with each other with home business phones computers using short-range wireless connection); Home RF-a standard competing with Bluetooth interconnection computing devices using radio frequency; Ethernet-local area network technology; power line-a using power distribution network home business interconnect devices. Digital information transmitted high-frequency carrier signal power.
controller-based "thin client," which modern replacement traditional terminal remote computing paradigm. Application programs remotely server, data warehoused centrally managed disks "server farm." efficient communications protocol transmits keyboard mouse commands upstream transmits video BIOS calls downstream. thin client renders displays graphics user. thin client typically connected Ethernet LAN, although remote location connect server connection such modem. minimum speed kbaud required communication protocol, unless application graphics-intensive, which case faster connection required.
Figure page shows micro-
controller-based digital (DSTB), which consumer client device that uses television display. Common applications DSTB internet access, e-mail, streaming audio video content. minimal system includes connection modem, ADSL, cable modem; output InfraRed (IR) link remote control wireless keyboard. Expanded systems include drives MPEG2 decoders deliver digital video content. hard drive employed store video data future replay. Keyboard, mouse, printer, video camera options that included.
Figure page shows micro-
controller-based telephone line concentrator located neighborhood that converts multiple analog subscriber loops into high-speed digitally multiplexed line connection central office switching network.
Microcontroller Data Sheet
RJ-11
RJ-11
RJ-45
Interface ADSL, Cable Modem V.90
RJ-45
PCnetTM-Home
Interface Am79C978
AD31-AD0
MD31-MD0 Control
Microcontroller
GPD15-GPD0 Control
33-MHz Crystal
Figure
Microcontroller-Based Smart Residential Gateway Reference Design
Microcontroller Data Sheet
32-kHz Crystal
Flash
MA12-MA0 SDRAM SDRAM
Control GPA25-GPA0
VGA/LCD
CRT/LCD
Controller
PS/2 Keyboard
PS/2 Mouse
Parallel Super
Interface Am79C973/Am79C975 PCnetTM-Fast
RJ-45
AD31-AD0
Control
Control
MA12-MA0 SDRAM SDRAM MD31-MD0 GPD15-GPD0 GPA25-GPA0 Flash Memory
Microcontroller
Control
Control
Figure
Microcontroller-Based Thin Client Reference Design
Microcontroller Data Sheet
33-MHz Crystal
32-kHz Crystal
Serial
NTSC/PAL
PS/2 Keyboard
PS/2 Mouse
Parallel Super
Interface ADSL, Cable Modem V.90
RJ-11
AD31-AD0
Control
MA12-MA0 SDRAM SDRAM GPD15-GPD0 Flash Memory
MD31-MD0
Control
Microcontroller
GPA25-GPA0
Control
Control
33-MHz Crystal
32-kHz Crystal
Figure
Microcontroller-Based Digital Reference Design
Microcontroller Data Sheet
EIDE
GPD15-GPD0
GPA1-GPA0
Control
Figure
ISLIC Am79R241 SDRAM Quad ISLAC Am79Q2241 ISLIC Am79R241 ISLIC Am79R241 ISLIC Am79R241 MD31-MD0 SDRAM MA12-MA0 Control 10X) Highway ISLIC Am79R241 ISLIC Am79R241 Quad ISLAC Am79Q2241 Control ISLIC Am79R241 ISLIC Am79R241 Microcontroller
Analog Phone Lines
33-MHz Crystal
Microcontroller-Based Telephone Line Concentrator Reference Design
Microcontroller Data Sheet
GPD15-GPD0 Flash Memory GPA25-GPA0 Control HDLC T1/E1 Interface
32-kHz Crystal
CLOCK GENERATION CONTROL
microcontroller designed generate internal system clocks requires. microcontroller includes on-chip oscillators PLLs, well most required loop filter components. microcontroller requires standard crystals, 32.768 MHz. clocks required inside microcontroller generated from these crystals. Output clock pins provided selected clocks, providing sink source current. microcontroller also supplies clocks SDRAM bus; however, external clock buffering required some systems. Figure shows system block diagram microcontroller's external clocks.
Note: microcontroller supports either 33.000-MHz 33.333-MHz crystal. this document, generic term MHz" refers system clock derived from whichever 33-MHz crystal frequency being used system.
VCC_ANLG 32KXTAL1 32.768-kHz Crystal 32KXTAL2 33MXTAL1 33-MHz Crystal LF_PLL1 33MXTAL2 Optional Clock Driver
SDRAM
CLKMEMOUT CLKMEMIN CLKPCIIN CLKPCIOUT CLKTIMER/ [CLKTEST] Microcontroller
Programmable
Optional Clock Driver
Note: Dotted line ovals,
signify frequency groups.
Device
Device
Figure
System Clock Distribution Block Diagram
Microcontroller Data Sheet
Internal Clocks
Figure shows block diagram microcontroller's internal clocks. clocks generated from local oscillators. 32.768-kHz oscillator used drive PLL1 (1.47456-MHz PLL), which turn drives PLL2 (36.864-
PLL). 36.864-MHz clock divided produce 18.432-MHz UART clock. divided produce 1.1892-MHz clock. 33-MHz oscillator produces 33-MHz clocks. 33-MHz oscillator also used drive PLL3 (66-MHz PLL) produce SDRAM clock.
32.768-kHz 32.768-kHz Crystal 32.768-kHz Oscillator 32.768-kHz SDRAM Refresh 36.864 1.47456 PLL1 LF_PLL1 33-MHz Crystal PLL2 1.1892-MHz
18.432-MHz UART 33-MHz Oscillator PLL3 SDRAM Timers1
Notes: Includes programmable interval timer (PIT), general-purpose timers, watchdog timer, software timer.
Figure
Clock Source Block Diagram
Microcontroller Data Sheet
Clock Specifications
period jitter specifications summarized Table Jitter specifications only guaranteed when analog supply noise restrictions met. Table shows lock times oscillator start-up times. Table shows oscillator input specifications. Loop filter components 1.47456-MHz (PLL1) must supplied externally. They connected between analog (VCC_ANLG) microcontroller pin, LF_PLL1. Specifications VCC_ANLG shown Table Figure page shows loop filter circuit composed Component values given Table page
Figure page external clock driver necessary when system presents large capacitive load. Clock pads designed either source sink maximum amount capacitive load that placed clock determined required rise/fall times. following equation determine maximum capacitive loading. I/(dV/dt) where current, voltage change, time change. example, suppose that system requires rise/fall time with voltage swing Then, maximum capacitive load CMAX mA/(2.5
Clock Loading
microcontroller's clock driver pins designed source sink shown
Table
Clock Name UART SDRAM Clock Frequency 1.1892 18.432
Clock Jitter Specifications
828.3 53.44 14.775 Nominal 840.9 54.25 15.0 853.5 55.07 15.225
33.000 33.333 66.000 66.666
Table
Clock Source 32.768-kHz Oscillator 33-MHz Oscillator PLL1 (1.47456 MHz) PLL2 (36.864 MHz) PLL3 MHz)
Clock Startup Lock Times
Table Oscillator Input Specifications
Parameter 32KXTAL2 Input Voltage 32KXTAL2 Input Voltage High 33MXTAL2 Input Voltage 33MXTAL2 Input Voltage High -0.3 VCC_RTC -0.3 VCC_ANLG +0.8 VCC_RTC +0.8 VCC_ANLG
Table
Parameter Peak-to-Peak Noise VCC_ANLG VCC_ANLG Voltage Level VCC_ANLG Current
Analog (VCC_ANLG) Specifications
2.25 2.75
Microcontroller Data Sheet
Table PLL1 Loop Filter Components
Parameter 0.009 0.0009 4.465 0.01 0.001 0.011 0.0011 4.935
Selecting Crystal
accuracy depends several factors relating crystal selection board design. clock timing budget determines clock accuracy. designer should determine timing budget before selecting crystal. There four major contributors clock timing budget.
Frequency Tolerance-This crystal calibration
multiply Error 106, error given. above equation, crystal motional capacitance, crystal static capacitance. CLxtal crystal load capacitance, CLsystem system load capacitance. Once complete timing error been calculated adding errors together, compare initial timing budget. Table provides convenient translation seconds month.
frequency. states actual crystal frequency from nominal frequency. typical 32.768-kHz crystal (watch crystal), frequency tolerance parts million (ppm). Frequency tolerance specified room temperature.
Frequency
Table Timing Error Translates Clock Accuracy
Timing Error (Parts million) Seconds/Month 25.9 51.8 77.8 103.7 129.6
Stability-This parameter measure much ystal resonant frequency influenced operating temperature. watch crystals, typical numbers around over temperature range. resonant frequency changes with time. Typical Aging numbers year.
Aging-This parameter much crystal
Load Capacitance-The crystal calibrated with
32.768-kHz Crystal Selection 32.768-kHz crystal oscillator shown Figure oscillator load capacitance Table provides specifications selecting proper 32.768-kHz crystal. Ecliptek ECPSM29T recommended.
specific load capacitance. system load capacitance does equal ystal load capacitance, timing error introduced. timing error calculated following equation. Error C1/(CLxtal+Co)]1/2 +C1/ (CLsystem+Co)]1/2}/ C1/(CLxtal+Co)]1/2
Internal
External 32KXTAL1 32KXTAL2 32.768-kHz Crystal
Figure 32.768-kHz Crystal Circuit Microcontroller Data Sheet
Table 32.768-kHz Crystal Specifications
Parameter Nominal Frequency Effective Series Resistance (ESR) Drive Level Load Capacitance microcontroller) Resonant Mode Crystal Operating Mode 32.768 60000 Parallel Fundamental Comment
Table 33-MHz Crystal Specifications
Parameter Characteristic Nominal Frequency Drive Level Load Capacitance microcontroller) Resonant Mode Crystal Operating Mode 33.000 33.333 Parallel Fundamental Comment
33-MHz Crystal Selection same information related 32.768-kHz crystal selection applies 33-MHz crystal selection. microcontroller supports either 33.000MHz 33.333-MHz crystal. Specifications 33-MHz crystal shown Table recommends using fundamental mode 33.333MHz crystal. third overtone crystal used, oscillator gain large enough produce reliable clock.
Third Overtone Crystal Component Selection third overtone crystal circuit implementation, refer Figure page Components selected user. parasitic capacitor composed board parasitics. Typical values range from required isolation. nominal value conjunction with form resonant circuit. value selected that resonant frequency between fundamental frequency third overtone frequency. 33.333-MHz third overtone crystal, fundamental frequency 11.111 MHz. From this, desirable resonant frequency between 11.111 33.333 MHz. good target frequency 22.222 MHz. selected from basic equation: 1/[(2 frequency)2 C3)] Assuming that board parasitics then: 22.222 MHz)2 pF)]
Microcontroller Data Sheet
Internal
External 33MXTAL1 33MXTAL2
Figure
33.333-MHz Third Overtone Crystal Implementation
Running Microcontroller 33.333 clock that supplied (CLKPCIOUT) exactly same frequency crystal. microcontroller simply buffers 33-MHz crystal input provides CLKPCIOUT pin. Since crystals have inaccuracies, possible that these inaccuracies cause period CLKPCIOUT become marginally less than system designer choose accuracy crystal used with microcontroller. 33.000-MHz frequency provides better guard band than 33.333-MHz crystal. practice, most devices tolerate both frequencies, important aware impact choosing crysta specifications. specification requires that minimum clock period
Microcontroller Data Sheet
Bypassing Internal Oscillators
32.768-kHz 33-MHz microcontroller oscillators bypassed connecting external clock crystal pins. Refer Figure Figure suggested circuitry.
External 32.768-kHz Oscillator ±10% typical 32KXTAL2
32KXTAL1
Microcontroller
Note: required when external oscillator voltage, VOSC, exceeds value depends VOSC according formula (VOSC 2.5) 2.5, where fixed value typical voltage 32KXTAL2 (±10%).
Figure Bypassing 32.768-kHz Oscillator
External 33-MHz Oscillator
2.5-V ±10% typical 33MXTAL2
Connect 33MXTAL1 Microcontroller
Figure
Bypassing 33-MHz Oscillator
Microcontroller Data Sheet
Bandgap Voltage Generator
Amplifier
OneShot Reset
BBATSEN
PWRGOOD
FlipFlop
Internal Power-Down
Figure Voltage Monitor Block Diagram
VOLTAGE MONITOR
external backup battery connected microcontroller's VCC_RTC pin, realtime clock (RTC) remains operational even other power supplies turned off. microcontroller's voltage monitor designed signal core when backup battery installed low. Additionally, voltage monitor circuit signals core when rest system being powered down. Features voltage monitor include:
Bandgap voltage generator precision reference
tery voltage, BBATSEN. BBATSEN drops below reference, invalidate signal generated notify user RTC_VRT (RTC index 0Dh[7]) that contents longer valid. There three conditions that trigger invalidation. They following:
BBATSEN drops below (sampled when PWR-
GOOD asserts)-During operation from main power supply, backup battery voltage might drop below trip voltage invalidated until PWRGOOD assertion occurs.
Power applied VCC_RTC (the backup battery
voltage
High-gain amplifier adjusting bandgap voltage
"low battery" trip voltage
connected main power plane
plugged in)-When backup battery plugged immediately invalidated.
battery during power-up (sampled after PWR-
backup battery needed system. Figure shows block diagram voltage monitor. voltage monitor circuit uses delta voltage (voltage from base emitter) source generate bandgap voltage approximately 1.23 This voltage input amplifier whose gain such that output voltage reference. This reference signal input comparator, along with backup bat-
GOOD asserts)-If system does contain backup battery BBATSEN line potential below invalidated when PWRGOOD asserts. addition backup battery monitor function, voltage monitor also provides power-down signal RTC. This signal used isolate core from rest integrated peripherals. timing diagram this sequence shown Figure page
Microcontroller Data Sheet
Table Voltage Monitor Component Specifications
Component Parameter Forward Voltage Drop Forward Voltage Drop Forward Current Capacitance Capacitance Resistance Nominal 0.25 Note
Notes: Diode should selected that voltage into power (VCC_RTC) does exceed
Backup Battery Considerations
behavior when primary power supply turned depends whether external backup battery included system design. Using External Backup Battery implementation using backup battery shown Figure page primary power source VCC_RTC main power plane (VCC). should chosen that forward voltage drop small, less than 0.25 also prevents backup battery from powering power plane when main supply turned off. backup battery voltage must exceed (affects BBATSEN VCC_RTC pins); higher voltages damage microcontroller. network composed provides time delay internal circuit power-up sequence. Accuracy tolerances nominal values given Table high-frequency filtering purposes. Using External Backup Battery system that using backup battery, Figure page shows circuit should designed. uses same that needed battery system, connected VCC_RTC. this configuration, invalidated after power-up, invalidated subsequent PWRGOOD assertions.
invalidated after power-up. this
case, power been removed from RTC, should invalidated.
When reset switch tied PWRGOOD pressed
remains High), PWRGOOD reasserts with BBATSEN High, invalidated. this case, power away, contents still good. VCC_ANLG selected power plane VCC_RTC because well-filtered power plane that well below VCC_RTC maximum Component values resistor capacitor shown Table
Microcontroller Data Sheet
VCC_RTC
BATT (3.3 max)
VCC_RTC BBATSEN
Microcontroller
Figure
Circuit with Backup Battery
VCC_ANLG
VCC_RTC BBATSEN
Microcontroller
Figure
Circuit without Backup Battery
Microcontroller Data Sheet
ABSOLUTE MAXIMUM RATINGS1
Symbol VCC_CORE VCC_I/O VCC_RTC VCC_ANLG Parameter Storage temperature Core voltage voltage
Minimum -0.5 -0.5 -0.5 -0.5
Maximum +125
Unit
Real-time clock voltage Analog voltage2
Notes: WARNING-the "Absolute Maximum Ratings" stress ratings only. Stresses above those listed cause permanent damage. Operation beyond values specified Operating Ranges Commercial Temperatures recommended, extended exposure beyond these operating range values affect device reliability. Referenced from GND. inputs tolerant.
OPERATING RANGES COMMERCIAL TEMPERATURES1
Symbol TCASE VCC_CORE VCC_I/O VCC_RTC VCC_ANLG Parameter Description Commercial case temperature operating free Core voltage voltage
Minimum +2.375 +3.0 +2.0 +2.25
Typical +2.5 +3.3 +2.5 +2.5
Maximum +2.625 +3.6 +3.3 +2.75
Unit
Real-time clock voltage Analog voltage2
Notes: Operating ranges define temperature voltage limits between which functionality device guaranteed. Referenced from GND. inputs tolerant.
Microcontroller Data Sheet
VOLTAGE LEVELS NON-PCI INTERFACE PINS1
Advance Information Symbol VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 Parameter Description Input voltage Input High voltage Output High voltage (IOH Output voltage (IOL Output High voltage (IOH Output voltage (IOL Output High voltage (IOH Output voltage (IOL Output High voltage (IOH Output voltage (IOL VCC_I/O 0.45 VCC_I/O 0.45 VCC_I/O 0.45 VCC_I/O 0.45 VCC_I/O 0.45 0.45 0.45 0.45 Unit
Notes: drive strengths pins listed Table "Pin List Summary," page A-7. pins with variable drive strengths take characteristics 12-, 18-, 24-mA signals.
VOLTAGE LEVELS INTERFACE PINS
voltage characteristics interface input pins specified Local Specification, Revision 2.2, section 4.2.1 Signaling Environment section 4.2.2 3.3V Signaling Environment. voltage characteristics interface output pins specified Local Specification, Revision 2.2, 4.2.2 3.3V Signaling Environment.
Microcontroller Data Sheet
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Advance Information Symbol ICC_CORE ICC_CORE ICC_I/O ICC_RTC ICC_ANLG ILI1 Parameter Description Current VCC_CORE supply Current VCC_CORE supply Current VCC_ supply 33-MHz Current RTC-only mode Current ANLG-only mode Input leakage current (0.1 VCC_I/O) (All pins except those with internal pullup pulldown resistors) Input leakage current (VCC_I/O (All pins with internal pulldown resistors) Input leakage current (All pins with internal pullup resistors) Output leakage current
Notes
Unit
ILI2 ILI3
Notes: Estimate based 3.3-V operation. Current supply constant, independent frequency. Value determined simulation will updated once characterization complete. Current measured with power applied only VCC_RTC supplies. VCC_I/O Table "Pin List Summary," page shows which pins have internal pullups pulldowns.
Microcontroller Data Sheet
CAPACITANCE Non-PCI Interface Capacitance
Advance Information Symbol C32KXTAL C33MXTAL COUT Parameter Description Input capacitance 32KXTAL1, 33KXTAL2 capacitance 33MXTAL1, 33MXTAL2 capacitance Output capacitance capacitance Test Conditions FC=1 Unit
Interface Capacitance
capacitance values specified Local Specification, Revision 2.2, section 4.2.2.1 Specifications, Table 4-3: Specifications 3.3V Signaling.
Derating Curves
programmable pins driven maximum drive current once. derating curves following pages used determine potential specified timing variations based system capacitive loading. Table "Pin List Summary," page column named "Max Load (pF)." This column describes specification load presented specific pin, when testing performed, generate timing specification documented Characteristics section this data sheet. capacitive load GPA0 then typical rise time From Figure same load gives typical fall time
Crystal Capacitance
crystal specifications found Table "32.768-kHz Crystal Specifications" page Table "33-MHz Crystal Specifications" page
Microcontroller Data Sheet
Worst Case Typical
Figure
Drive 6-mA Rise Time
Worst Case Typical
Figure Drive 6-mA Fall Time
Microcontroller Data Sheet
Worst Case Typical
Figure
Drive 12-mA Rise Time
Worst Case Typical
Figure
Drive 12-mA Fall Time
Microcontroller Data Sheet
Worst Case
Typical
Figure
Drive 24-mA Rise Time
Worst Case Typical
Figure
Drive 24-mA Fall Time
Microcontroller Data Sheet
Best Case Typical Worst Case
Figure
Pads Rise Time with 1-ns Rise/Fall
Typical Best Case
Worst Case
Figure
Pads Fall Time with 1-ns Rise/Fall
Microcontroller Data Sheet
POWER CHARACTERISTICS
Dynamic measurements dependent upon chip activity, operating frequency, output buffer logic, capacitive/resistive loading outputs. Actual power supply current dependent system design greater less than typical number present here. Maximum power measured maximum maximum case temperature. Typical power measured typical 55°C. power dissipation values, refer Table Table
Table
Power Maximum power Typical power
Device Power Dissipation1
Unit
Notes: Device power dissipation calculation assumes that power consumed chip.
Table
Supply
VCC_ANLG VCC_RTC Power Dissipation
Typical 4.75 12.5 2.75 5.78 Unit
VCC_ANLG voltage level VCC_ANLG current VCC_ANLG power VCC_RTC voltage level VCC_RTC current VCC_RTC power
THERMAL CHARACTERISTICS 388-Pin PBGA Package
microcontroller specified operation with case temperature ranges from +85C VCC_CORE VCC_I/O 10%. Case temperature measured center package shown Figure various temperatures thermal resistances determined using equations Figure with information given Table Thermal, electrical, mechanical characteristics qualified packages (including PBGA) found AMD's website www.amd.com. Click link Products, then click document link Packages Packing Methodologies.
Figure Thermal Resistance (C/Watt)
Microcontroller Data Sheet
Table Thermal Resistance (°C/W) Package with 6-Layer Board
Board Type1 6-layer
Airflow
16.6 14.7 13.6 12.9 12.5
Notes: board type described JEDEC standards document entitled Thermal Test Chip Guideline (Wire Bond Type Chip) www.jedec.org. home page click link Free Standards Docs, then click document link JESD51-4 under JEDEC PUBLICATIONS.
Table Maximum Plastic Package with 6-Layer Board1 with TCASE 85°C
Clock Rate Airflow (Linear Feet Minute) 67°C 70°C 70°C 72°C 71°C 74°C 72°C 74°C 73°C 75°C
Notes: board type described JEDEC standards document entitled Thermal Test Chip Guideline (Wire Bond Type Chip) www.jedec.org. home page click link Free Standards Docs, then click document link JESD51-4 under JEDEC PUBLICATIONS.
qJC)
where:
qJA)
Thermal resistance from junction ambient Thermal resistance from junction case Thermal resistance from case ambient Junction temperature Ambient temperature Case temperature Power Watts Power supply current
Figure
Thermal Characteristics Equations
Microcontroller Data Sheet
SWITCHING CHARACTERISTICS WAVEFORMS
switching specifications provided characteristics tables that follow consist output delays, input setup requirements, input hold requirements. specifications measurement defined figures that follow each timing table. timings referenced unless otherwise specified. Output delays specified with minimum maximum limits, measured shown. minimum delay times hold times provided external circuitry. Input setup hold times specified minimums, defining smallest acceptable sampling window. Within sampling window, synchronous input signal must stable correct microcontroller operation.
Switching Waveforms
WAVEFORMS INPUTS Must Steady OUTPUTS Will Steady
Change from
Will Changing from
Change from
Will Changing from
Don't Care, Change Permitted
Changing, State Unknown
Does Apply
Center Line High-Impedance "Off" State
SWITCHING TEST WAVEFORMS Non-PCI Interface Pins
VCC_I/O VCC_I/O Test Points VCC_I/O
VIL=
Input
Output
Note: testing, inputs driven logic logic
Figure Switching Test Waveforms
Interface Pins
timing interface pins, refer Local Specification Revision 2.2, 4.2.3.3 Measurement Test Conditions, Figure 4-7: Output Timing Measurement Conditions, Figure 4-8: Input Timing Measurement Conditions.
Microcontroller Data Sheet
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
this section, following timings timing waveforms shown:
Power-on reset (page Reset (page (page (page SDRAM (page SDRAM clock (page (page read (page write (page (page JTAG (page
Power-On Reset Timing
Advance Information Symbol Parameter Description VCC_RTC valid hold before other VCCs valid PWRGOOD valid hold from valid (except VCC_RTC) VCC_RTC valid BBATSEN active CFGx, RSTLDx, DEBUG_ENTER, INST_TRCE, AMDEBUG_DIS setup PWRGOOD active CFGx, RSTLDx, DEBUG_ENTER, INST_TRCE, AMDEBUG_DIS hold from PWRGOOD active GPRESET inactive from PWRGOOD active inactive from PWRGOOD active PWRGOOD inactive VCCs invalid (except VCC_RTC)
Notes
Unit
Notes: This parameter dependent 32-kHz oscillator startup time, which dependent characteristics crystal, leakage capacitive coupling board, ambient temperature. This parameter ensures that internal valid status cleared indicate that time CMOS contents invalid. This parameter must ensure that date time invalidated.
Microcontroller Data Sheet
VCC_RTC
other VCCs
PWRGOOD CFGx, RSTLDx, DEBUG_ENTER, INST_TRCE, AMDEBUG_DIS BBATSEN GPRESET
Figure
Power-Up Timing Sequence
PWRGOOD VCC1
Notes: Applies VCCs except VCC_RTC, which left this mode. These timings apply only when powering down chip while leaving only powered. Guarantees least rising edge 32-kHz signal after reset before reached.
Figure
PWRGOOD Timing Standalone Mode
Microcontroller Data Sheet
Reset Timing with Power Applied
Advance Information Symbol Parameter Description PWRGOOD inactive pulse width CFGx, RSTLDx setup PWRGOOD active CFGx, RSTLDx hold from PWRGOOD active PWRGOOD inactive GPRESET, outputs active PWRGOOD active GPRESET, outputs inactive PRGRESET active pulse width PRGRESET active GPRESET, outputs active PRGRESET inactive GPRESET, outputs inactive Reset outputs (GPRESET, RST) active pulse width internally generated system reset
Notes
1000
Unit
Notes: Internal system reset sources include software system reset (SYS_RST bit), AMDebug interface system reset, watchdog timer reset.
PWRGOOD CFGx, RSTLDx GPRESET
Figure
External System Reset Timing with Power Applied
Microcontroller Data Sheet
PRGRESET GPRESET
Figure PRGRESET Timing
GPRESET
Figure Internal System Reset Timing
Microcontroller Data Sheet
Timing
Advance Information Symbol Parameter Description1 GPA25-GPA4, chip select setup before ROMBUFOE, ROMRD, GPA3-GPA0 active GPA25-GPA4, chip select active pulse-width read access Read data valid required from GPA3-GPA0, ROMRD ROMBUFOE, non-page-mode access Read data valid from GPA3-GPA0, page-mode access Read data hold from address, chip select, ROMRD, ROMBUFOE GPA25-GPA0, chip select hold time from ROMBUFOE, ROMRD read access ROMBUFOE, ROMRD read recovery time GPA3-GPA0 valid, first access
Notes
(PFWS ((PFWS 303) ((PFWS 303) ((PSWS 303)
((PFWS 303) ((PSWS 303)
Unit
GPA3-GPA0 valid time, non-page-mode access
GPA3-GPA0 valid time, page-mode access GPA25-GPA0, chip select setup ROMBUFOE, FLASHWR active GPA25-GPA0 valid, chip select active pulse-width write access Write data valid setup ROMBUFOE, FLASHWR GPA25-GPA0, chip select hold time from ROMBUFOE, FLASHWR write access Write data hold time from ROMBUFOE, FLASHWR write access ROMBUFOE, FLASHWR write recovery time
(PFWS
Notes: Chip Select includes BOOTCS, ROMCS1, ROMCS2. PFWS represents programmable first wait state timing parameter controller register corresponding chip select. value corresponds 33-MHz crystal frequency assumes 33.333 MHz. PSWS represents programmable subsequent wait state timing parameter controller register corresponding chip select.
Microcontroller Data Sheet
GPA25-GPA4, Chip Select GPA3-GPA0 ROMBUFOE ROMRD DATA (In)
Notes: Chip select includes BOOTCS, ROMCS1, ROMCS2. Data includes GPD15-GPD0 MD31-MD0.
Figure Non-Burst Read Cycle Timing
GPA25-GPA4, Chip Select GPA3-GPA0 ROMBUFOE ROMRD DATA (In)
Notes: Chip select includes BOOTCS, ROMCS1, ROMCS2. Data includes GPD15-GPD0 MD31-MD0.
Figure Page-Mode Read Cycle Timing
Microcontroller Data Sheet
GPA25-GPA0, Chip Select ROMBUFOE FLASHWR
DATA (Out)
Notes: Chip select includes BOOTCS, ROMCS1, ROMCS2. Data includes GPD15-GPD0 MD31-MD0.
Figure
Flash Write Cycle Timing
Timing
characteristics interface pins specified Local Specification, Revision 2.2, section 4.2.1.1 Specifications, Table 4-1: Specifications Signaling, section 4.2.2.1 Specifications, Table 4-3: Specifications 3.3V Signaling.
Microcontroller Data Sheet
SDRAM Timing
Parameter Name Parameter Description TRAS TRCD TDPL TCKH TCKL Refresh active active command period Active command precharge command period TRAS Active command column command same bank TRCD Precharge command active command period Write recovery data-in precharge lead time TDPL High pulse width TCKH pulse width TCKL period Command setup Command hold Access time from Data-in (read) hold time data-out high-impedance data-out low-impedance Transition time rise fall Data-out (write) setup time Data-out hold time Address setup time Address hold time
Advance Information Notes 1351 7500 Unit
Symbol
Notes: Corresponds 33-MHz crystal frequency assumes 33.333 with guardband. This access time based clock period assuming minimal delay between CLKMEMOUT output CLKMEMIN input. does take into account external delays clock buffering/skew, clock loading/routing, data loading/routing. delays that system designer must take into consideration identified equation below:
TSKEW TCK_LD TD_LD
where: Access time SDRAM device (not impacted board design) TSKEW Delay between CLKMEMOUT CLKMEMIN TCK_LD Additional clock delay loading TD_LD Data delay loading SDRAM memory clock (assumes 33.333 crystal)
Microcontroller Data Sheet
CLKMEMIN column bank CMD1 write prechrg data data t113 data column bank column
Microcontroller Data Sheet
active
write
prechrg
active
read
write
precharge
active
write
precharge
active
read
Notes: applies SRAS, SCAS, BA0, BA1, SWE, SCSx, SDQM. Prechrg abbreviation precharge. shown latency includes SDRAM data lines MECC lines. Parameter (TRC) shown.
Figure
SDRAM Write Read Timing
SDRAM Clock Timing
Symbol Parameter Description CLKMEMOUT period CLKMEMOUT High time CLKMEMOUT time CLKMEMIN delay rising from CLKMEMOUT rising Notes
Advance Information -0.5
Unit
Notes: This parameter based PLL, multiplier frequency 33-MHz crystal. value affected chosen frequency crystal (33.000 33.333 MHz).
CLKMEMOUT CLKMEMIN
Figure SDRAM Clock Timing
Microcontroller Data Sheet
Timing1
Advance Information Symbol Parameter Description Setup, GPA, GPBHE stable command assertion, 8/16-bit memory access Setup, GPIOCS16, GPMEMCS16 asserted programmed command deassertion Delay, GPIOCS16, GPMEMCS16 hold from programmed command deassertion Command pulse width, GPIOWR, GPMEMWR, GPIORD, GPIOWR, 8/16-bit cycles GPA, GPBHE hold from command deassertion Setup, GPRDY deasserted programmed command deassertion GPRDY pulse width Command High (deassertion) time Setup, write command assertion Hold, from write command deassertion Setup, stable read command deassertion Hold, from read command deassertion Setup, GPA, GPBHE stable GPALE falling edge
Notes
((OFFS+1) 303) ((PW 303) ((OFFS+1) 303) (OFFS PW+2) ((PW 303) ((OFFS+1) 303)
Unit
t207 t217 t227
GPALE pulse width Setup, GPAEN GPIORD/GPIOWR assertion (echo mode) Setup, GPA, GPBHE stable GPCS Hold, GPA, GPBHE stable from GPCS Pulse width, GPCS Hold, GPAEN GPIORD/GPIOWR deassertion (echo mode) Setup, GPDBUFOE assertion command assertion Hold, GPDBUFOE assertion from command assertion
(OFFS+1) (RCOV+1) ((PW 303) ((OFFS+1) 303)
Notes: GPCS7-GPCS0 signals internally qualified with command, GPCS7-GPCS0 command pads switch simultaneously. GPCSx deassert prior deassertion command. OFFS represents programmable offset timing parameter corresponding pin. corresponds 33-MHz crystal frequency assumes 33.333 MHz. represents programmable pulse width parameter corresponding pin. This increased based programmed chip-select offset pulse width along with recovery time. This parameter must ensure that cycle extended GPRDY. This parameter assumes that GPCS7-GPCS0 signals internally qualified with command. RCOV represents programmable recovery time chip selects.
Microcontroller Data Sheet
GPA25-GPA0, GPBHE GPCS7-GPCS0 GPALE GPIOWR/GPMEMWR GPIORD/GPMEMRD GPIOCS16/GPMEMCS16 GPDBUFOE GPAEN
GPRDY GPD15-GPD0 (Write) GPD15-GPD0 (Read)
Figure
Non-DMA Cycle Timing
Microcontroller Data Sheet
Read Cycle Timing
Advance Information Symbol TCLK Parameter Description GP-DMA clock cycle GPDRQ asserted GPDACK assertion GPDACK asserted GPAEN GPDBUFOE assertion setup time GPIOWR, GPMEMWR non-compressed non-extended write mode GPDACK asserted GPIOWR, GPMEMWR assertion GPIOWR, GPMEMWR pulse width GPDACK asserted GPTC assertion GPTC pulse width GPAEN GPDBUFOE deasserted from command deasserted GPDRQ deasserted from GPDACK assertion GPDACK deasserted from command deasserted hold from GPIOWR, GPMEMWR setup time GPIOWR, GPMEMWR compressed extended write mode Unit TCLK TCLK TCLK TCLK TCLK TCLK TCLK TCLK TCLK TCLK
GPDRQ GPDACK GPAEN GPDBUFOE GPD15-GPD0 GPIOWR, GPMEMWR GPTC
Figure GP-DMA Read Cycle Timing
Microcontroller Data Sheet
Write Cycle Timing
Advance Information Symbol TCLK Parameter Description GP-DMA clock cycle GPDRQ GPDACK assertion GPDACK asserted GPAEN GPDBUFOE assertion GPIORD, GPMEMRD asserted valid GPDACK asserted GPIORD, GPMEMRD assertion GPIORD, GPMEMRD pulse width GPDACK asserted GPTC assertion GPTC pulse width GPAEN GPDBUFOE deasserted from command deasserted GPDRQ deasserted from GPDACK assertion GPDACK deasserted from command deasserted GPIORD, GPMEMRD deasserted invalid Unit TCLK TCLK TCLK TCLK TCLK TCLK TCLK TCLK TCLK
GPDRQ GPDACK GPAEN GPDBUFOE GPD15-GPD0 GPIORD, GPMEMRD GPTC
Figure
GP-DMA Write Cycle Timing
Microcontroller Data Sheet
Timing
Advance Information Symbol Parameter Description SSI_CLK period SSI_CLK High time SSI_CLK time SSI_DI setup time sample edge SSI_DI hold time from sample edge SSI_DO hold time from assert edge SSI_DO setup sample edge SSI_DO high impedance from sample edge last
Notes
(0.5 TCLK) TCLK
(0.5 TCLK)
Unit
Notes: clock period interface programmable divisor 33-MHz crystal input. Rates provided binary multiples from divide (~110 divide (~15526 ns). actual period affected frequency crystal (33.000 33.333 MHz). sample/assert clock edge interface programmable. TCLK refers programmed period SSI_CLK pin.
SSI_CLK SSI_DI SSI_DO
Notes: Asserted rising edge, sampled falling edge.
Figure Timing
Microcontroller Data Sheet
JTAG Timing
Advance Information Symbol Parameter Description JTAG_TRST active pulse width JTAG_TCK period JTAG_TCK High time JTAG_TCK time JTAG_TMS, JTAG_TDI setup time JTAG_TMS, JTAG_TDI hold time JTAG_TDO delay Input setup time Input hold time Output delay Unit
JTAG_TRST JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO Input Output
Figure
JTAG Boundary Scan Timing
Microcontroller Data Sheet
APPENDIX TABLES
This appendix contains tables microcontroller. Several different tables included with following characteristics:
Multiplexed
signal
tradeoffs-Table
tables showing pins sorted number signal name, respectively, "Pin Designations (Pin Number)" page "Pin Designations (Pin Name)" page signal descriptions, Table "Signal Descriptions" page tables brackets, indicate alternate, multiplexed functions, braces, indicate reset configuration pins (pinstraps). line over name indicates active signal. word refers physical wire; word signal refers electrical signal that flows through
page A-2.
Programmable pins ordered number
multiplexed signal name, respectively, including column showing configurations following system reset-Table page Table page A-5.
summary showing signal name alternate
function, number, type, termination, reset state, output drive, maximum load-Table page A-7.
Microcontroller Data Sheet
Table
Signal Want ROM/Flash Control ROMCS1 ROMCS2 GPAEN GPALE GPBHE GPCS0 GPCS1 GPCS2 GPCS3 GPCS4 GPCS5 GPCS6 GPCS7 GPDACK0 GPDACK1 GPDACK2 GPDACK3 GPDBUFOE GPDRQ0 GPDRQ1 GPDRQ2 GPDRQ3 GPIOCS16 GPIRQ0 GPIRQ1 GPIRQ2 GPIRQ3 GPIRQ4 GPIRQ5 GPIRQ6 GPIRQ7 GPIRQ8 GPIRQ9 GPIRQ10 GPMEMCS16 GPRDY GPTC Serial Ports CTS2 DCD2 DSR2 RIN2 PIO28 PIO30 PIO29 PIO31 PIO3 PIO0 PIO1 PIO27 ROMCS1 ROMCS2 PITGATE2 TMRIN1 TMRIN0 TMROUT1 TMROUT0 PIO12 PIO11 PIO10 PIO9 PIO24 PIO8 PIO7 PIO6 PIO5 PIO25 PIO23 PIO22 PIO21 PIO20 PIO19 PIO18 PIO17 PIO16 PIO15 PIO14 PIO13 PIO26 PIO2 PIO4 AE11 AE12 AF12 AC21 AA24 AC20 AC23 AD23 AF10 AE10 AD10 AF11 AD11 GPCS1 GPCS2
Multiplexed Signal Trade-Offs
Signal Give
Microcontroller Data Sheet
Table
Clocks CLKTEST CLKTIMER Timers PITGATE2 TMRIN0 TMRIN1 TMROUT0 TMROUT1 System Test CF_DRAM CF_ROM_GPCS DATASTRB WBMSTR0 WBMSTR1 WBMSTR2 WBMSTR2 WBMSTR0 WBMSTR1 CF_ROM_GPCS DATASTRB CF_DRAM AD20 AC24 AD20 AC24 GPCS3 GPCS5 GPCS4 GPCS7 GPCS6 AC21 AC20 AA24 AD23 AC23 CLKTIMER CLKTEST
Multiplexed Signal Trade-Offs (Continued)
Signal Give
Signal Want
Configuration Pins (Pinstraps)-See "Configuration" page Programmable PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 GPALE GPBHE GPRDY GPAEN GPTC GPDRQ3 GPDRQ2 GPDRQ1 GPDRQ0 GPDACK3 GPDACK2 GPDACK1 GPDACK0 GPIRQ10 GPIRQ9 GPIRQ8 GPIRQ7 GPIRQ6 GPIRQ5 GPIRQ4 GPIRQ3 GPIRQ2 GPIRQ1 GPIRQ0 GPDBUFOE GPIOCS16 GPMEMCS16 GPCS0 AE12 AF12 AF11 AE11 AD11 AD10 AE10 AF10
Microcontroller Data Sheet
Table
(Default Function) PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 AE12 AF12 AF11 AE11 AD11 AD10 AE10 AF10
PIOs Sorted Number
Multiplexed Signal GPALE GPBHE GPRDY GPAEN GPTC GPDRQ3 GPDRQ2 GPDRQ1 GPDRQ0 GPDACK3 GPDACK2 GPDACK1 GPDACK0 GPIRQ10 GPIRQ9 GPIRQ8 GPIRQ7 GPIRQ6 GPIRQ5 GPIRQ4 GPIRQ3 GPIRQ2 GPIRQ1 GPIRQ0 GPDBUFOE GPIOCS16 GPMEMCS16 GPCS0 CTS2 DSR2 DCD2 RIN2 Configuration Following System Reset Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup
Microcontroller Data Sheet
Table PIOs Sorted Signal Name
Multiplexed Signal CTS2 DCD2 DSR2 GPAEN GPALE GPBHE GPCS0 GPDACK0 GPDACK1 GPDACK2 GPDACK3 GPDBUFOE GPDRQ0 GPDRQ1 GPDRQ2 GPDRQ3 GPIOCS16 GPIRQ0 GPIRQ1 GPIRQ10 GPIRQ2 GPIRQ3 GPIRQ4 GPIRQ5 GPIRQ6 GPIRQ7 GPIRQ8 GPIRQ9 GPMEMCS16 GPRDY GPTC RIN2 (Default Function) PIO28 PIO30 PIO29 PIO3 PIO0 PIO1 PIO27 PIO12 PIO11 PIO10 PIO9 PIO24 PIO8 PIO7 PIO6 PIO5 PIO25 PIO23 PIO22 PIO13 PIO21 PIO20 PIO19 PIO18 PIO17 PIO16 PIO15 PIO14 PIO26 PIO2 PIO4 PIO31 Configuration Following System Reset Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup AE11 AE12 AF12 AF10 AE10 AD10 AF11 AD11
Microcontroller Data Sheet
List Summary Table Column Definitions
following paragraphs describe individual columns information Table "Pin List Summary," page A-7. pins grouped alphabetically function.
Table
Type
List Summary Table Abbreviations
Definition None applicable. Brackets signify programmable alternate state. Reset configuration pin. These configuration pins latched during reset. Used Reset State column indicate signals active during reset. analog input. Bidirectional. Driven High logical input. Input open-drain output. Driven logical Used Reset State column indicate signal latched reset. applicable. active output. Open-drain output. Oscillator. Built-in pulldown resistor (~100-150 kW). Power pins. Built-in pullup resistor (~100-150 kW). Schmitt trigger input. Sustained three-state (PCI drive). Three-state output.
Active Analog Latched Power
Column #1-Signal Name, [Alternate Function], {Pinstrap}
This column denotes primary alternate functions pins. Brackets, used indicate alternate, multiplexed function pin. Braces, used indicate functionality only during processor reset. These signals called pinstraps. pinstraps, "Configuration" page
Column #2-Pin
number column identifies number individual signal package.
Column #3-Type
Definitions abbreviations Type column shown Table
Column #4-Termination
Termination column specifies presence pullups pulldowns pins.
Column #5-Reset State
Definitions abbreviations Reset State column shown Table
Column #6-Output Drive
Output Drive column shows output amperage.
Column #7-Max Load (pF)
Load column designates capacitive load which timing that guaranteed.
Column #8-Note
Note column shows footnote numbers.
Microcontroller Data Sheet
Table
Signal Name [Alternate Function] {Pinstrap} SDRAM CLKMEMIN CLKMEMOUT MA10 MA11 MA12 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 Active 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 Type
List Summary
Reset State Output Drive Load (pF)
Termination
Microcontroller Data Sheet
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 SCASA SCASB SCS0 SCS1 SCS2 SCS3 SDQM0 SDQM1 SDQM2 SDQM3 SRASA SRASB SWEA SWEB ROM/Flash Control BOOTCS FLASHWR ROMBUFOE ROMCS1 [GPCS1] ROMCS2 [GPCS2] ROMRD STS-B STS-B STS-B STS-B AB25 AB24 AA25 AB23 Type Termination Reset State Output Drive 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18 12/18 12/18 12/18 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 12/18/24 Load (pF)
Microcontroller Data Sheet
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0 CBE1 CBE2 CBE3 CLKPCIIN CLKPCIOUT DEVSEL FRAME GNT0 GNT1 GNT2 GNT3 GNT4 INTA Type STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B STS-B Termination Reset State Active Output Drive Load (pF)
Microcontroller Data Sheet
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} INTB INTC INTD IRDY PERR REQ0 REQ1 REQ2 REQ3 REQ4 SERR STOP TRDY GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 GPA8 GPA9 GPA10 GPA11 GPA12 GPA13 GPA14 GPA15 {RSTLD0} GPA16 {RSTLD1} GPA17 {RSTLD2} GPA18 {RSTLD3} GPA19 {RSTLD4} GPA20 {RSTLD5} Latched Latched Latched Latched Latched Latched Type STS-B STS-B STS-B STS-I STS-B STS-B Termination Reset State Output Drive Load (pF)
A-10
Microcontroller Data Sheet
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} GPA21 {RSTLD6} GPA22 {RSTLD7} GPA23 {AMDEBUG_DIS} GPA24 {INST_TRCE} GPA25 {DEBUG_ENTER} GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 GPD8 GPD9 GPD10 GPD11 GPD12 GPD13 GPD14 GPD15 GPIORD GPIOWR GPMEMRD GPMEMWR GPRESET PIO0 [GPALE] PIO1 [GPBHE] PIO2 [GPRDY] PIO3 [GPAEN] PIO4 [GPTC] PIO5 [GPDRQ3] PIO6 [GPDRQ2] AC22 AE12 AF12 AF11 AE11 AD11 AD10 AE10 Type [STI] Termination Reset State Latched Latched Latched Latched Latched Output Drive Load (pF)
Microcontroller Data Sheet
A-11
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} PIO7 [GPDRQ1] PIO8 [GPDRQ0] PIO9 [GPDACK3] PIO10 [GPDACK2] PIO11 [GPDACK1] PIO12 [GPDACK0] PIO13 [GPIRQ10] PIO14 [GPIRQ9] PIO15 [GPIRQ8] PIO16 [GPIRQ7] PIO17 [GPIRQ6] PIO18 [GPIRQ5] PIO19 [GPIRQ4] PIO20 [GPIRQ3] PIO21 [GPIRQ2] PIO22 [GPIRQ1] PIO23 [GPIRQ0] PIO24 [GPDBUFOE] PIO25 [GPIOCS16] PIO26 [GPMEMCS16] PIO27 [GPCS0] Serial Ports CTS1 DCD1 DSR1 DTR1 DTR2 AE23 AF10 Type [STI] [STI] Termination Reset State Output Drive Load (pF)
A-12
Microcontroller Data Sheet
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} PIO28 [CTS2] PIO29 [DSR2] PIO30 [DCD2] PIO31 [RIN2] RIN1 RTS1 RTS2 SIN1 SIN2 SOUT1 SOUT2 SSI_CLK SSI_DI SSI_DO Clocks Reset 32KXTAL1 32KXTAL2 33MXTAL1 33MXTAL2 CLKTIMER [CLKTEST] LF_PLL1 PRGRESET PWRGOOD JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST AMDebug Interface BR/TC CMDACK STOP/TX TRIG/TRACE System Test CF_DRAM [WBMSTR2] {CFG2} Latched AD24 AF17 AC13 AD21 AF21 AF22 AE21 AE22 O/TS AF26 AE26 AB26 AC26 AF24 Active Active Active Active Active AD22 AD19 AE19 AF19 Type Termination Reset State Output Drive Load (pF)
Microcontroller Data Sheet
A-13
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} CF_ROM_GPCS [WBMSTR0] {CFG0} DATASTRB [WBMSTR1] {CFG1} Timers PITGATE2 [GPCS3] PITOUT2 {CFG3} TMRIN0 [GPCS5] TMRIN1 [GPCS4] TMROUT0 [GPCS7] TMROUT1 [GPCS6] Power Ground BBATSEN Analog Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Latched AC21 AC20 AA24 AD23 AC23 Latched AD20 Type Termination Reset State Latched Output Drive Load (pF)
AC24
Latched
A-14
Microcontroller Data Sheet
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} GND_ANLG VCC_ANLG VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O AC14 AC15 AA23 AC10 AC11 AC18 AC19 Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Termination Reset State Output Drive Load (pF)
Microcontroller Data Sheet
A-15
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_I/O VCC_RTC Connects
AA26 AC12 AC16 AC17 AC25 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD25 AD26 AE13 AE14 AE15 AE16 AE17 AE18
Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power
Termination
Reset State
Output Drive
Load (pF)
A-16
Microcontroller Data Sheet
Table List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} AE20 AE24 AE25 AF13 AF14 AF15 AF16 AF18 AF20 AF23 AF25 Type Termination Reset State Output Drive Load (pF)
Notes: true connects" should left disconnected.
Microcontroller Data Sheet
A-17
A-18
Microcontroller Data Sheet
APPENDIX PHYSICAL DIMENSIONS 388-Pin Plastic (PBGA) Package View
35.00 29.90 30.10 28.00 0.50
CORNER CORNER I.D.
ENCAPSULATION
35.00 17.0 14.0 FLAT AREA
4.00 SIDE (DIE SIDE)
0.50 0.70 0.51 0.61
0.15 0.15
2.20 2.46
SIDE VIEW 0.15
SEATING PLANE
DETAIL
SCALE:NONE
Microcontroller Data Sheet
Bottom View
31.75 (DATUM
CORNER CORNER I.D.
0.60 388X 0.90
0.635 31.75 (DATUM
0.635 BOTTOM VIEW
1.27 ROWS COLUMNS
16-038-BGA388-2 ET118 10.26.98
Microcontroller Data Sheet
Circuit Board Layout Considerations
There basic ways ball pad, solder-mask defined solder-pad defined.
Solder-mask defined when solder mask
opening smaller than copper pad, solder surface defined solder mask rather than copper pad.
Solder-pad defined when copper
board pad-defined, then problem occur where there more surface area board making contact than part itself. When part heats cools, different amount stress placed chip than board (because there more surface area soldered board), chip warp. definition board should match chip. microcontroller solder-mask defined, circuit board design should soldermask defined with solder-mask opening 0.60 over 0.80-mm shown Figure
smaller than solder mask, solder surface defined copper pad. problem occur when these methods. example, chip solder-pad defined
0.80 Copper
Exposed Copper Solder Mask Covered Copper
0.60 Solder Mask Opening View
Solder Mask
Copper Printed Circuit Board
Side View
Figure
Ball Layout
Microcontroller Data Sheet
Microcontroller Data Sheet
APPENDIX CUSTOMER SUPPORT
AMD-K6TME Microprocessor Am5x86 Microprocessor Am486®DX Microprocessor Am386®SX/DX Microprocessors Microcontroller Am186CC Communications Controller Am186CH HDLC Microcontroller Am186TMCU Microcontroller Microcontroller
AMD-K6TM-2E Microprocessor
Microcontroller Microcontroller
Microcontroller
Am186EM Am188TMEM Microcontrollers Am186EMLV Am188EMLV Microcontrollers
Am186ES Am188ES Microcontrollers Am186ESLV Am188ESLV Micr
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