M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32

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M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32

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'97.4.7
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD 8-BIT) CMOS STATIC
DESCRIPTION
M5M5255DP,FP 262,144-bit CMOS static RAMs organized 32,768-words 8-bits which fabricated using high-performance polysilicon CMOS technology. resistive load NMOS cells CMOS periphery results high density power static RAM. Stand-by current small enough battery back-up application. ideal memory systems which require simple interface.
CONFIGURATION (TOP VIEW)
M5M5255DP,FP
FEATURE
Type Access Power supply current time Active Stand-by (max) (max) (max) 45ns 55ns 70ns 45ns 55ns 70ns 55mA
(Vcc=5.5V)
M5M5255DP, FP-45LL M5M5255DP, FP-55LL M5M5255DP, FP-70LL M5M5255DP, FP-45XL M5M5255DP, FP-55XL M5M5255DP, FP-70XL
Outline 28P4 (DP) 28P2W-C (DFP) 20µA
(Vcc=5.5V)
(Vcc=5.5V)
0.05µA
(Vcc=3.0V, Typical)
power supply clocks, refresh +2.0V power supply compatible inputs outputs outputs OR-tie capability memory expantion /S1, Data backup capability stand-by
PACKAGE
M5M255DP M5M5255DFP
APPLICATION
Small capacity memory units
MITSUBISHI ELECTRIC
'97.4.7
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD 8-BIT) CMOS STATIC
FUNCTION
operation mode M5M5255DP,FP determined combination device control inputs /S1, Each mode summarized function table. write cycle executed whenever level overlaps with level high level address must before write cycle must stable during entire cycle. data latched into cell trailing edge whichever occurs first, requiring set-up hold time relative these edge maintained. read cycle executed setting high level while active state(/S1="L", S2="H"). When setting high level level, chip non-selectable mode which both reading writing disabled. this mode, output stage high-impedance state, allowing OR-tie with other chips memory expansion power supply current reduced stand-by current which specified Icc3 Icc4, memory data held power supply, enabling battery back-up operation during power failure power-down operation non-selected mode.
FUNCTION TABLE
Mode selection selection Write Read High-impedance High-impedance DOUT Stand-by Stand-by Active Active
FUNCTION TABLE
ADDRESS INPUT
ADDRESS INPUT BUFFER DECODER 32768 WORD SENSE ANPLIFIER OUTPUT BUFFER 8BIT
DATA
(512 ROWS COLUMNS)
WRITE CONTROL INPUT CHIP SELECT INPUT1 CHIP SELECT INPUT2
DATA INPUT BUFFER COLUMN DECODER ADDRESS INPUT BUFFER
CLOCK GENERATOR
(5V) (0V)
MITSUBISHI ELECTRIC
'97.4.7
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD 8-BIT) CMOS STATIC
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Topr Tstg Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect Ta=25°C Ratings -0.3*~7.0 -0.3*~Vcc+0.3
(Max 7.0)
Unit
0~Vcc 0~70 -65~150
-3.0V case Pulse width 30ns
ELECTRICAL CHARACTERISTICS
Symbol VOH1 VOH2 Parameter High-level input voltage Low-level input voltage High-level output voltage High-level output voltage Low-level output voltage Input current Output current off-state Active supply current
(AC, level
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Test conditions
Limits -0.3
+0.3
Unit
IOH=-1mA IOH=-0.1mA IOL=2mA VI=0~Vcc /S1=VIH S2=VIL /OE=VIH VI/O=0~Vcc 45ns /S10.2V, S2>Vcc-0.2V Other inputs<0.2V >Vcc-0.2V 55ns Output-open(duty 100%) 70ns /S1=VIL,S2=VIH other inputs=VIH Output-open(duty 100%) S20.2V /S1Vcc-0.2V, S2Vcc-0.2V other inputs=0~Vcc /S1=VIH S2=VIL, other inputs=0~Vcc 45ns 55ns 70ns
-0.5
Icc1
Icc2
Active supply current
(AC, level
Icc3
Stand-by current
Icc4
Stand-by current
-3.0V case Pulse width 30ns
CAPACITANCE
Symbol
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Parameter Input capacitance Output capacitance
Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
Limits
Unit
Note Direction current flowing into positive mark). Typical value 25°C. periodically sampled 100% tested.
MITSUBISHI ELECTRIC
'97.4.7
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD 8-BIT) CMOS STATIC
ELECTRICAL CHARACTERISTICS MEASUREMENT CONDITIONS
0~70°C, Vcc=5V±10%, unless otherwise noted 1.8k
(Including scope JIG)
Input pulse Input rise fall Reference Output (-45LL,-45XL CL=50pF (-55LL,-55XL CL=100pF (-70LL,-70XL CL=5pF (for ten,tdis) Transition measured ±500mV from steady state voltage. (for ten,tdis)
Fig.1 Output load
READ CYCLE
Limits -55LL,
Symbol ta(A) ta(S1) ta(S2) tdis(S1) tdis(S2) ten(S1) ten(S2) tV(A)
Parameter Read cycle time Address access time Chip select access time Chip select access time Output disable time after high Output disable time after Output enable time after Output enable time after high Data valid time after address
-45LL,
-70LL,
Unit
WRITE CYCLE
Limits -55LL,
-45LL, Write cycle time tw(W) Write pulse width tsu(A) Address setup time tsu(A-WH) Address setup time with respect tsu(S1) Chip select setup time tsu(S2) Chip select setup time tsu(D) Data setup time th(D) Data hold time trec(W) Write recovery time tdis(W) Output disable time from ten(W) Output enable time from high Symbol Parameter
-70LL,
Unit
MITSUBISHI ELECTRIC
'97.4.7
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD 8-BIT) CMOS STATIC
TIMING DIAGRAMS Read cycle
A0~14 ta(A) (S1)
(Note
tdis (S1)
(Note
(Note
(S2) (S1) (S2) tdis (S2) DATA VALID
level (Note
DQ1~8
Write cycle control mode)
A0~14
(S1)
(Note (Note
(Note
(S2) (A-WH) trec
(Note
tdis
DQ1~8
DATA STABLE
MITSUBISHI ELECTRIC
'97.4.7
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD 8-BIT) CMOS STATIC
Write cycle control mode)
A0~14 (S1) trec
(Note (Note (Note
(Note
(Note
(Note
DQ1~8
DATA STABLE
Write cycle control mode)
A0~14
(Note (Note
(S2)
trec
(Note
(Note
(Note
(Note
DQ1~8
DATA STABLE
Note Hatching indicates state "don't care". Writing executed while high overlaps low. When falling edge simultaneously prior falling edge rising edge outputs maintained high impedance state. Don't apply inverted phase signal externally when output mode.
MITSUBISHI ELECTRIC
'97.4.7
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD 8-BIT) CMOS STATIC
POWER DOWN CHARACTERISTICS ELECTRICAL CHARACTERISTICS
Symbol
(PD) (/S1) (S2)
0~70°C, Vcc=5V±10%, unless otherwise noted)
Parameter
Power down supply voltage Chip select input Chip select input
Test conditions
2.2VVCC(PD) 2VVCC(PD)2.2V 4.5VVCC(PD) VCC(PD)<4.5V S20.2V /S1Vcc-0.2V,S2Vcc-0.2V
Limits
Unit
VCC(PD)
(PD)
Power down supply current
(Note
(Note
Note7: (PD) case 25°C Note8: (PD) 0.5uA case 25°C
TIMING REQUIREMENTS 0~70°C, Vcc=5V±10%, unless otherwise noted
Symbol (PD) trec (PD) Parameter
Power down time Power down recovery time
Test conditions
Limits
Unit
POWER DOWN CHARACTERISTICS control mode
(PD)
2.2V 4.5V 4.5V
trec (PD)
2.2V
/S1Vcc-0.2V
control mode
0.2V S20.2V
(PD)
4.5V
4.5V
trec (PD)
0.2V
MITSUBISHI ELECTRIC

M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32

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