1997.11.20 Rev.F 4194304-BIT (1048576-WORD 4-BIT) CMOS STATIC

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1997.11.20 Rev.F 4194304-BIT (1048576-WORD 4-BIT) CMOS STATIC

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M5M54R04J-12,-15
1997.11.20 Rev.F
4194304-BIT (1048576-WORD 4-BIT) CMOS STATIC
DESCRIPTION M5M54R04J family 1048576-word 4-bit static RAMs, fabricated with high performance CMOS silicon gate CONFIGURATION (TOP VIEW)
address lead package(SOJ). inputs These device operate single supply, directly chip select compatible. They include power down feature well. input data inputs/ FEATURES outputs (5V) Fast access time M5M54R04J-12 12ns(max) (0V) M5M54R04J-15 15ns(max) data inputs/ power dissipation Active 450mW(typ) outputs write control Stand 5mW(typ) input Single power supply Fully static operation clocks, refresh address Common data inputs Easy memory expansion Three-state outputs OR-tie capability prevents data contention Directly compatible inputs outputs Outline
M5M54R04J offered 32-pin plastic small outline
process designed high speed application.
address inputs output enable input data inputs/ (0V) outputs (5V) data inputs/ outputs address inputs
M5M54R04J
32P0K(SOJ)
APPLICATION
High-speed memory units
PACKAGE
32pin 400mil
BLOCK DIAGRAM
address inputs
ADDRESS DECODERS
INPUT BUFFERS
OUTPUT BUFFERS
data inputs/ outputs
MEMORY ARRAY ROWS 8192 COLUMNS
COLUMN CIRCUITS
COLUMN COLUMN ADDRESS DECODERS ADDRESS DECODERS COLUMN INPUT BUFFERS
DATA INPUT BUFFERS
(5V)
(0V)
address inputs
MITSUBISHI ELECTRIC
M5M54R04J-12,-15
4194304-BIT (1048576-WORD 4-BIT) CMOS STATIC
FUNCTION
operation mode M5M54R04J determined combination device control inputs Each mode summarized function table. write cycle executed whenever level overlaps with level address must set-up before write cycle must stable during entire cycle. data latched into cell trailing edge whichever occurs first, requiring set-up hold time relative these edge maintained. output enable input directly controls output stage. Setting high level, output stage high impedance state, data contention problem write cycle eliminated. read cycle excuted setting high level level while active state (S=L). When setting high level, chip nonselectable mode which both reading writing disable. this mode, output stage highimpedance state, allowing OR-tie with other chips memory expansion Signal-S controls power-down feature. When goes high, power dissapation reduced extremely. access time from equivalent address access time.
FUNCTION TABLE
Mode selection Write Read High-impedance Dout High-impedance Stand Active Active Active
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Ta=25 With respect Conditions
Ratings -3.5 -3.5 VCC+0.3 -3.5 VCC+0.3 1000
Unit
Tstg(bias) Storage temperature (bias) Storage temperature
*Pulse width 20ns, case DC:-0.5V
ELECTRICAL CHARACTERISTICS
Symbol Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current
(Ta=0 Vcc=5V±10% unless otherwise noted) Condition Limits -0.3 Vcc+0.3 12ns cycle 12ns cycle 15ns cycle 15ns cycle Unit
=-4mA IOL= 0~Vcc (S)= Output current off-state 0~Vcc Active supply current (TTL level) (S)= other inputs Output-open(duty 100%)
Stand current (TTL level)
(S)= (S)= Vcc0.2V other inputs I0.2V VIVcc-0.2V
Stand current
MITSUBISHI ELECTRIC
M5M54R04J-12,-15
4194304-BIT (1048576-WORD 4-BIT) CMOS STATIC
CAPACITANCE (Ta=0 Vcc=5V±10% unless otherwise noted)
Symbol Parameter Input capacitance Output capacitance Test Condition =GND, =25mVrms,f=1MHz O=GND, =25mVrms,f=1MHz Limit Unit
Note Direction current flowing into positive mark). Typical value Vcc=5V,Ta=25 CI,CO periodically sampled 100% tested.
ELECTRICAL CHARACTERISTICS (1)MEASUREMENT CONDITION
(Ta=0 Vcc=5V±10% unless otherwise noted)
Input pulse levels =3.0V, =0.0V Input rise fall time Input timing reference levels =1.5V, IL=1.5V Output timing reference levels OH=1.5V, =1.5V Output loads Fig1 ,Fig2
OUTPUT Z0=50 RL=50 VL=1.5V (including scope JIG)
Fig.1 Output load
Fig.2 Output load
MITSUBISHI ELECTRIC
M5M54R04J-12,-15
4194304-BIT (1048576-WORD 4-BIT) CMOS STATIC
(2)READ CYCLE
Limits
Symbol Parameter
M5M54R04J
M5M54R04J
Unit
ta(S) (OE) tdis(S) tdis (OE) ten(S) (OE) tv(A)
Read cycle time Address access time Chip select access time Output enable access time Output disable time after high Output disable time after high Output enable time after Output enable time after Data valid time after address change Power-up time after chip selection Power-down time after chip selection
(3)WRITE CYCLE
Limits
Symbol Parameter
M5M54R04J
M5M54R04J
Unit
tw(W) (A)1 (A)2 trec(W) tdis tdis
(OE)
Write cycle time Write pulse width Address setup time(W) Address setup time(S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after Output disable time after high Output enable time after high Output enable time after Address High
(OE) tsu(A-WH)
MITSUBISHI ELECTRIC
M5M54R04J-12,-15
4194304-BIT (1048576-WORD 4-BIT) CMOS STATIC
(4)TIMING DIAGRAMS Read cycle 0~19
UNKNOWN DATA VALID PREVIOUS DATA VALID
DQ1~4
OE=L
Read cycle (Note
ta(S)
(Note
tdis
(Note
DQ1~4
UNKNOWN
DATA VALID
ICC1 ICC2 OE=L
Note Addresses valid prior coincident with transition low. Transition measured ±500mv from steady state voltage with specified loading Figure
Read cycle (Note
(OE)
(Note
tdis (OE)
(Note
(OE)
UNKNOWN DATA VALID
DQ1~4
Note Addresses valid prior transition (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI ELECTRIC
M5M54R04J-12,-15
4194304-BIT (1048576-WORD 4-BIT) CMOS STATIC
Write cycle control mode
0~19
(Note7)
(Note7)
(A-WH)
trec
th(D)
DQ1~4
(Input Data)
DATA STABLE
tdis(W) (Note tdis(OE)
(OE) (Note
DQ1~4
(Output Data)
Hi-Z
Write cycle control mode
0~19
trec
tw(W)
(Note7) (Note7)
DQ1~4
(Input Data)
DATA STABLE
tdis
(Note5)
DQ1~4
(Output Data)
(Note5)
Hi-Z
(Note8)
Note Hatching indicates state don't care. When falling edge simultaneous prior falling edge output maintained high impedance. en,tdis periodically sampled 100% tested.
MITSUBISHI ELECTRIC

1997.11.20 Rev.F 4194304-BIT (1048576-WORD 4-BIT) CMOS STATIC

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