1048576-BIT(65536-WORD 16-BIT)CMOS STATIC DESCRIPTION M5M51R16AWG
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M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD 16-BIT)CMOS STATIC
DESCRIPTION M5M51R16AWG 1048576-bit CMOS static organized 65536 words 16-bits, which fabricated using high-performance CMOS technology. CMOS cells periphery results high density power static RAM. M5M51R16AWG achieve stand-by current operation current ideal battery back-up application. M5M51R16AWG packaged 48-pin chip scale package which high reliability high density surface mount device (SMD). Using this type devices, becomes very easy design small system. M5M51R16AWG fully compatible with M5M51R16WG.
CONFIGURATION (TOP VIEW)
DQ16
DQ14 DQ15
DQ13
DQ11 DQ10 DQ12
FEATURE Power supply current Type name M5M51R16AWG- 10LI M5M51R16AWG- 12LI M5M51R16AWG- 15LI M5M51R16AWG- 10HI M5M51R16AWG- 12HI M5M51R16AWG- 15HI Access time (max) 100ns 120ns 150ns 100ns 120ns 150ns Active (max) Stand-by (max) 10mA (1MHz)
CONFIGURATION (BOTTOM VIEW)
Single +1.8V~2.7V power supply power down current 0.05µA(typ.) Directly compatible inputs outputs Easy memory expansion power down S,BC1 Data hold +1.0V power supply Three-state outputs OR-tie capability prevents data contention Common data Separate control lower upper bytes Package 48-pin chip scale package(CSP) Ball pitch 0.75mm Package size: 7.0mm 8.5mm APPLICATION Small capacity memory units.
DQ16
DQ15 DQ14 DQ13 DQ12 DQ10 DQ11
Outline
48FJA
CONNECTION
Aug.1. 1998
MITSUBISHI ELECTRIC
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD 16-BIT)CMOS STATIC FUNCTION operation mode M5M51R16A series determined combination device control inputs BC2. Each mode summarized function table. write cycle executed whenever level overlaps with level and/or level address must before write cycle must stable during entire cycle. data latched into cell trailing edge BC1, whichever occurs first, requiring set-up hold time relative these edge maintained. output enable input directly controls output stage. Setting high level, output stage high-impedance state, data contention problem write cycle eliminated. read cycle executed setting high level level while and/or active state. (BC1 and/or BC2=L, S=L) When setting high level other pins active state, upper-Byte selectable mode which both reading writing enabled, lower -Byte non-selectable mode. when setting high level other pins active state, lower-Byte selectable mode which both reading writing enabled, upper -Byte non-selectable mode. When setting high level high level, chips non-selectable mode which both reading writing disabled. this mode, output stage high-impedance state, allowing -tie with other chips memory expansion BC1, control power down feature. When high, power supply current reduced stand-by current which specified Icc3 Icc4, memory data held +1.0V power supply, enabling battery back-up operation during power-failure power-down operation non-selected mode. FUNCTION TABLE
Mode Word Read Upper-Byte Read Lower-Byte Read
(Upper-Byte selection)
DQ1~8 DQ9~16 Dout Active Dout Dout High-Z High-Z Active Active Active Active Active
(Lower-Byte selection) High-Z Dout High-Z
Word Write Upper-Byte Write
(Lower-Byte selection)
Lower-Byte Write
(Upper-Byte selection)
Output disable selection selection
High-Z High-Z Active High-Z High-Z Stand-by High-Z High-Z Stand-by (High-Z=High-impedance)
BLOCK DIAGRAM
ADDRESS INPUTS 65536 WORDS BITS ROWS COLUMNS BLOCKS DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 CLOCK GENERATOR CHIP SELECT INPUT WRITE CONTROL INPUT OUTPUT ENABLE INPUT BYTE CONTROL INPUTS (0V) (0V) (0V) DATA INPUTS/ OUTPUTS
Aug.1. 1998
MITSUBISHI ELECTRIC
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD 16-BIT)CMOS STATIC
ABSOLUTE MAXIMUM RATINGS Symbol Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect Ta=25°C Ratings -0.2 -0.2* Vcc+0.2(max.4.6V) ~150 Unit
-1.0V case Pulse width 30ns
ELECTRICAL CHARACTERISTICS Symbol ICC1W ICC2W ICC1B ICC2B ICC3 ICC4 Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Output current off-state Word operation(16bit) Active supply current (AC,TTL level) Byte operation(8bit) Active supply current (AC,TTL level) Stand-by current
40~85°C, 1.8V~2.7V, unless otherwise noted Conditions Limits -0.2* -0.1mA 0.1mA ~Vcc VIH, VI/O VIL, other inputs Output-open(duty 100%) cycle 1MHz Unit Vcc+0.2V
(BC1 VIL) (BC1 cycle VIH) ,other inputs 1MHz Output-open(duty 100%) SVcc-0.2V, other inputs 0~Vcc Vcc-0.2V,S0.2V, other inputs 0~Vcc VIH, other inputs 0~Vcc
Stand-by current
-1.0V case Pulse width 30ns
CAPACITANCE Symbol
~85°C, 1.8V~2.7V, unless otherwise noted Parameter Conditions VI=GND, Vi=25mVrms, f=1MHz VO=GND, Vo=25mVrms, f=1MHz Limits Unit
Input capacitance Output capacitance
Note Direction current flowing into positive mark). Note Typical value 2.0V, 25°C Note CI,CO periodically sampled 100% tested.
Aug.1. 1998
MITSUBISHI ELECTRIC
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD 16-BIT)CMOS STATIC
ELECTRICAL CHARACTERISTICS ~85°C, 1.8V~2.7V, unless otherwise noted MEASUREMENT CONDITIONS Input pulse level 0.2V, 0.2V Input rise fall time Reference level 0.9V, 0.9V Output loads Fig.1,CL 30pF ten, tdis Transition measured ±200mV from steady state voltage. ten, tdis Including scope
Fig.1 Output load (2)READ CYCLE Limits Symbol Parameter Read cycle time Address access time Chip select access time access time access time Output enable access time Output disable time after high Output disable time after high Output disable time after high Output disable time after high Output enable time after Output enable time after Output enable time after Output enable time after Data valid time after address change -10LI,-10HI -12LI,-12HI -15LI,-15HI Unit
ta(A) ta(S) ta(BC1) ta(BC2) ta(OE) tdis(S) tdis(BC1) tdis(BC2) tdis(OE) ten(S) ten(BC1) ten(BC2) ten(OE) tV(A)
(3)WRITE CYCLE Limits Symbol Parameter Write cycle time Write pulse width Address time Address time with respect setup time setup time Chip select time Data time Data hold time Write recovery time Output disable time after Output disable time after high Output enable time after high Output enable time after Output enable time after Output enable time after -10LI,-10HI -12LI,-12HI -15LI,-15HI Unit
tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) ten(BC1) ten(BC2)
Aug.1. 1998
MITSUBISHI ELECTRIC
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD 16-BIT)CMOS STATIC
TIMING DIAGRAMS Read cycle
0~15 ta(A) ta(BC1) ta(BC2)
(Note
tv(A)
and/or
tdis(BC1) tdis(BC2) ta(S)
(Note
(Note
ta(OE) ten(OE)
tdis(S)
(Note
(Note
ten(BC1) ten(BC2) ten(S)
tdis(OE)
DATA VALID
(Note
DQ1~16
level
Write cycle control mode
0~15 tsu(BC1) tsu(BC2) and/or
(Note (Note
(Note
tsu(S)
(Note
tsu(A-WH) tsu(A) tdis(W) tdis(OE)
DATA
tw(W)
trec(W) ten(OE) ten(W)
DQ1~16
STABLE
tsu(D)
Aug.1. 1998 MITSUBISHI ELECTRIC
th(D)
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD 16-BIT)CMOS STATIC Write cycle BC1, control mode
0~15 tsu(A) and/or tsu(BC1) tsu(BC2) trec(W)
(Note (Note (Note
(Note
(Note (Note
DQ1~16
Write cycle control mode)
tsu(D) th(D) DATA STABLE
0~15
and/or
(Note (Note
tsu(A)
(Note
tsu(S)
trec(W)
(Note
(Note (Note
tsu(D) DQ1~16
DATA STABLE
th(D)
Note Hatching indicates state "don't care". Note Writing executed while overlaps and/or low. Note When falling edge simultaneously prior falling edge and/or falling edge outputs maintained high impedance state. Note 7:Don't apply inverted phase signal externally when output mode. Note 8:ten,tdis periodically sampled 100% tested. Note 9:tCR(Read cycle time) defined whole time from reading address this address change under read mode condition S,W,OE,BC1 and/or BC2. Note 10:tCW(Write cycle time) defined whole time from writing address this address change under write mode condition S,W,BC1 and/or BC2. Aug.1. 1998 MITSUBISHI ELECTRIC
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD 16-BIT)CMOS STATIC
POWER DOWN CHARACTERISTICS ELECTRICAL CHARACTERISTICS Symbol Parameter 40~85°C, unless otherwise noted Test conditions Limits
Unit
Vcc(PD) Power down supply voltage VI(S) Chip select input Byte control inputs 1.8V Vcc(PD) 1.0V Vcc(PD) 1.8V 1.8V Vcc(PD) 1.0V Vcc(PD) 1.8V 2.0V 0.2V other inputs 0~Vcc 0.2V 0.2V,other inputs 0~Vcc
Vcc(PD) Vcc(PD) 0.05
VI(BC)
ICC(PD)
Power down supply current
TIMING REQUIREMENTS
~85°C, unless otherwise noted Limits
Symbol
Parameter Power down time
Test conditions
Unit
tsu(PD)
trec(PD) Power down recovery time
POWER DOWN CHARACTERISTICS control mode
tsu(PD) 1.8V 1.8V trec(PD)
control mode
tsu(PD) 1.8V 1.8V trec(PD)
Aug.1. 1998
MITSUBISHI ELECTRIC
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