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Bits Banks (512Mb) SDRAM Tower Burst Mode Operation Auto self ref


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T4S1288-4xxxx
Bits Banks (512Mb) SDRAM Tower
Burst Mode Operation Auto self refresh capability (8192 cycles/64ms refresh) LVTTL compatible inputs outputs +3.3V 0.3V power supply cycle with address programs Latency (access from column address) Burst Length full page) Data scramble (sequential interleave) inputs sampled positive going edge system clock TSOP Tower Stack Single (-4xxx1) Dual (-4xxx2)
GENERAL DESCRIPTION
SiliconTech T4S32M4-4xxxx bits banks Single Data Rate (SDR) Synchronous Dynamic (SDRAM) Tower. Tower consists 3.3V CMOS bits banks SDRAMs 54-pin 400-mil TSOP-II packages mounted stacks stack PCBs. SDRAMs soldered onto both sides PCBs using high temperature solder shown following page. Tower then mounted onto module using temperature solder. stacking technology patented SiliconTech Tower (Patent 5,514,907). Tower used place single allow high capacity memory modules without increasing height memory module.
CONFIGURATION
Symbols
Symbol VCCQ VSSQ VCCQ VSSQ Symbol Symbol CKE0 CKE1* VCCQ VSSQ VCCQ VSSQ
Functions
Symbol A0-A12 BA0, DQ0-DQ3 CKE0, CKE1* CS0, VCC/VSS VCCQ/VSSQ Function Address Input Bank Select Data In/Out Write Enable Clock Input Clock Enable Adress Strobe Column Address Strobe Data Input/Output Mask Chip Select Input System Power (+3.3V)/ Ground Data Output Power/Ground Connected
Locations
CKE1 used dual Towers only.
SiliconTech Datasheets, Visit www.silicontech.com
Document Part Number 61000-01426-101 2000
Page
T4S1288-4xxxx
ORDERING INFORMATION
Please check current revision Tower Ordering Information (Document Number 61000-01093-xxx) available options, contact your Sales Representative. T4S1288-4xxx1 specifies Single option, T4S12884xxx2 specifies Dual option.
TOWER
PACKAGE DIMENSIONS RECOMMENDED FOOTPRINT
0.33mm (0.013") 0.46mm (0.018") 22.60mm (0.890" MAX) (0.382") 0.76mm (0.030") 2.29mm (0.090") 13.04 (0.513")
Units: milimeters (inches); Tolerances: ±0.10mm ±0.004 inches) unless otherwise specified.
12.80mm (0.504")
FUNCTIONAL BLOCK DIAGRAM Single (T4S1288-4xxx1)
DQ0-DQ3 A0-A12, BA0, CKE0
Dual (T4S1288-4xxx2)
DQ0-DQ3 A0-A12, BA0, CKE0 CKE1
Bottom SDRAM
SDRAM
Bottom SDRAM
SDRAM
Document Part Number 61000-01426-101 2000
0.80mm (0.031")
0.80mm (0.031")
Page

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