Organization: 524,288 words bits Intelliwattactive power circuitry 2.3

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Organization: 524,288 words bits Intelliwattactive power circuitry 2.3

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Organization: 524,288 words bits Intelliwattactive power circuitry 2.3V 3.0V operating range 25/35/55/70/100 address access time power consumption Active: (100 cycle) 3.0V Standby: Very component active power, 1.5V data retention Easy memory expansion with inputs Smallest footprint packages ball FBGA 44-pin TSOP Center power ground pins noise protection 2000 volts Latch-up current Industrial temperature range available (-40 +85°C) Other voltage versions available
2.7V 3.6V (AS7C34096LL) 1.65V 1.95V (AS7C184096LL)
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TSOP
I/O0 I/O1 I/O2 I/O3 I/O7 I/O6
Input buffer
I/O7
decoder
1024 Array (4,194,304)
Sense
I/O5 I/O4
I/O0
Column decoder
Control Circuit
48-CSP Ball-Grid-Array Package (shading indicates ball)
I/O4 I/O5 I/O6 I/O7 I/O0 I/O1 I/O2 I/O3
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Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current -100 Unit
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Copyright ©1998 Alliance Semiconductor. rights reserved.
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AS7C254096LL high performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) organized 524,288 words bits. designed portable applications where fast data access, long battery life, simple interfacing desired.
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Equal address access cycle times (tAA, tRC, tWC) 25/35/55/70/100 with output enable access times (tOE) ideal high performance applications. Active high chip enables (CE) permit easy memory expansion with multiple-bank memory systems. When HIGH, device enters standby mode. AS7C254096LL guaranteed exceed power consumption standby mode. This device also returns data when reduced 1.5V, even lower power consumption. write cycle accomplished asserting write enable (WE) chip enable (CE). Data input pins I/O0-I/O7 written rising edge (Write waveform active-to-inactive edge (Write waveform avoid contention, external devices should drive pins only after outputs have been disabled with output enable (OE) write enable (WE). read cycle accomplished asserting output enable (OE) chip enable (CE), with write enable (WE) HIGH. chip drives pins with data word referenced input address. When either chip enable output enable inactive, write enable active, output drivers stay high-impedance mode. This device packaged common industry standard packages. Chip scale packaging, easy manufacturing, provides smallest possible footprint. 48-ball JEDEC registered package ball pitch 0.75 external dimensions 6mm.
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Data High-Z High-Z Dout Mode Standby (ISB) Output disable Read Write
Key: Don't Care, Low, High
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Parameter Voltage input Voltage Power dissipation Storage temperature (plastic) Symbol VtIN VtI/O Tstg -0.5 -0.5 +3.6 +150 Unit
output current Iout Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
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Parameter Supply voltage input voltage Ambient operating temperature
Symbol Commercial Industrial
-0.5
Unit
-3.0V pulse width less than
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Parameter Symbol Test conditions Outputs disabled, Vout -100 -100 Unit
Input leakage current Output leakage current Output voltage
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Condition Operating, active Operating, static Standby, address toggling Symbol IDD1 Test conditions VIL, Max, fMax 1/tRC, IOUT VSS, Max, IOUT VIH, Max, fMax 1/tRC VDD-0.2V, Max, 0.2V 0.2V, -100 Unit
Standby, address static
ISB1
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Parameter Input capacitance capacitance Symbol CI/O Signals
0+]7D 5RRPWHPSHUDWXUH9 Test conditions Vout Unit
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Parameter Read cycle time Symbol -100 Unit Notes
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Address access time
Chip enable (CE) access time tACE Output enable (OE) access time Output hold from address change output tCLZ tOLZ
High output High tCHZ output High output High tOHZ Power time Power down time
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Rising input Falling input Undefined output/don't care $GGUHVVFRQWUROOHG
Address Dout Data valid
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tRC1
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tOLZ tACE Dout tCLZ Current supply Data valid tOHZ tCHZ
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Parameter Write cycle time Chip enable write Address setup write Address setup time Write pulse width Address hold from write Data valid write Data hold time Write enable output High Output active from write Symbol Unit Notes
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Address Dout Data valid
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Address
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Dout Data valid
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Parameter data retention Data retention current Operation recovery time Symbol ICCDR Test conditions 1.5V VDD-0.2V VDD-0.2V 0.2V Unit Notes
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Chip deselect data retention time tCDR
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Data retention mode 2.3V tCDR 1.5V 2.3V
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output load: Figure except noted Figure Input pulse level: VDD. Figure Input rise fall times: Figure Input output timing reference levels: VDD.
20,000 Dout 18,000 Dout 18,000
alen
20,000
*including scope capacitance
Figure Output load
Figure Output load tCLZ, tCHZ, tOLZ, tOHZ,
Figure Input waveform
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During power-up, pull-up resistor required meet specification. This parameter sampled 100% tested. test conditions, Test Conditions, Figures tCLZ tCHZ specified with Figure Transition measured ±500mV from steady-state voltage. This parameter guaranteed tested. HIGH read cycle. read cycle. Address valid prior coincident with transition LOW. read cycle timings referenced from last valid address first transitioning address. must HIGH during address transitions. write cycle timings referenced from last valid address first transitioning address.
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Bottom View
Side View
Ball
View
Ball index
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Minimum 5.90 7.90 0.17
Typical 6.00 3.75 8.00 5.25 0.75 0.35 0.22 0.10
Maximum 6.10 8.10 1.20 0.27
Detail View
Notes Units: Pitch: (x,y)=0.75 0.75 (typ.) coplanarity: 0.10
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Package Access time TSOP 7C254096LL-25TC 7C254096LL-25TI 7C254096LL-25BC 7C254096LL-25BI 7C254096LL-35TC 7C254096LL-35TI 7C254096LL-35BC 7C254096LL-35BI 7C254096LL-55TC 7C254096LL-55TI 7C254096LL-55BC 7C254096LL-55BI 7C254096LL-70TC 7C254096LL-70TI 7C254096LL-70BC 7C254096LL-70BI 7C254096LL-100TC 7C254096LL-100TI 7C254096LL-100BC 7C254096LL-100BI
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AS7C 4096 Device number Intelliwatt Access time Package:T=TSOP B=CSP Temperature range, =Commercial:0°C 70°C =Industrial:-40°C 85°C 3=3.3V CMOS SRAM prefix 25=2.5V CMOS 18=1.8V CMOS
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Organization: 524,288 words bits Intelliwattactive power circuitry 2.3

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