12-Bit with SPIInterface 12-Bit Resolution ±0.2 (typ) (typ) Singl
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MCP4921/4922
12-Bit with SPIInterface
12-Bit Resolution ±0.2 (typ) (typ) Single Dual Channel Rail-to-Rail Output SPIInterface with Clock Support Simultaneous Latching Dual DACs w/LDAC Fast Settling Time Selectable Unity Gain Output Multiplier Mode External VREF Input 2.7V 5.5V Single-Supply Operation Extended Temperature Range: -40°C +125°C
Description
Microchip Technology Inc. MCP492X 5.5V, low-power, DNL, 12-Bit Digital-to-Analog Converters (DACs) with optional buffered output interface. MCP492X DACs that provide high accuracy noise performance industrial applications where calibration compensation signals (such temperature, pressure humidity) required. MCP492X available extended temperature range PDIP, SOIC, MSOP TSSOP packages. MCP492X devices utilize resistive string architecture, with inherent advantages error, ratio metric temperature coefficient fast settling time. These devices specified over extended temperature range. MCP492X include doublebuffered inputs, allowing simultaneous updates using LDAC pin. These devices also incorporate Power-On Reset (POR) circuit ensure reliable power-up.
Applications
Point Offset Trimming Sensor Calibration Digitally-Controlled Multiplier/Divider Portable Instrumentation (Battery-Powered) Motor Feedback Loop Control
Package Types
8-Pin PDIP, SOIC, MSOP
Block Diagram
LDAC
VOUTA AVSS VREFA LDAC
MCP4921
Interface Logic
Power-on Reset
AVSS Input Input Register Register DACA Register VREF String DACA Buffer Gain Logic Output Amps Output Logic String DACB Buffer Gain Logic DACB Register VREF
14-Pin PDIP, SOIC, TSSOP
VOUTA VREFA AVSS VREFB VOUTB SHDN LDAC
MCP4922
VOUTA
SHDN
VOUTB
2004 Microchip Technology Inc.
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MCP4921/4922
ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" cause permanent damage device. This stress rating only functional operation device those other conditions above those indicated operational listings this specification implied. Exposure maximum rating conditions extended periods affect device reliability.
Absolute Maximum Ratings
6.5V inputs outputs w.r.t AVSS -0.3V VDD+0.3V Current Input Pins Current Supply Pins .±50 Current Output Pins .±25 Storage temperature .-65°C +150°C Ambient temp. with power applied .-55°C +125°C protection pins (HBM), 400V (MM) Maximum Junction Temperature (TJ) .+150°C
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, AVSS VREF 2.048V, output buffer gain GND, +85°C. Typical values +25°C. Parameters Power Requirements Input Voltage Input Current MCP4921 Input Current MCP4922 Hardware Shutdown Current Software Shutdown Current Power-on-Reset Threshold Accuracy Resolution Error Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Input Amplifier (VREF Input) Input Range Buffered Mode Input Range Unbuffered Mode Input Impedance Input Capacitance Unbuffered Mode Multiplier Mode Bandwidth VREF VREF RVREF CVREF fVREF fVREF Multiplier Mode Total Harmonic Distortion Note THDVREF 0.040 0.040 VREF 2.5V ±0.2Vp-p, Unbuffered, VREF 2.5V ±0.2 Vp-p, Unbuffered, VREF 2.5V ±0.2Vp-p, Frequency Note Code 2048 VREF 0.2v p-p, Unbuffered Mode VOS/°C -0.75 ±0.2 ±0.02 0.16 -0.44 -0.10 +0.75 Bits ppm/°C ppm/°C Device Monotonic -45°C 25°C +25°C 85°C Code 0x000h Input unbuffered, digital inputs grounded, output unloaded, code 0x000 Units Conditions
ISHDN ISHDN_SW VPOR
G/°C
Code 0xFFFh, including offset error. ppm/°C
design, production tested. small quantify.
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AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, AVSS VREF 2.048V, output buffer gain GND, +85°C. Typical values +25°C. Parameters Output Amplifier Output Swing VOUT 0.010 0.040 0.55 Accuracy better than VOUT (VDD degrees V/µs Within final value from full-scale range Note change around major carry (0111.1111 1000.0000) Note Note Units Conditions
Phase Margin Slew Rate Short Circuit Current Settling Time Dynamic Performance DAC-to-DAC Crosstalk Major Code Transition Glitch Digital Feedthrough Analog Crosstalk Note
tsettling
nV-s nV-s nV-s nV-s
design, production tested. small quantify.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, AVSS VREF 2.048V external, output buffer gain GND, +85°C. Typical values 25°C Parameters Power Requirements Input Voltage Input Current MCP4921 Input Current MCP4922 Hardware Shutdown Current Software Shutdown Current Power-On Reset threshold Accuracy Resolution Error Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Input Amplifier (VREF Input) Input Range Buffered Mode Input Range Unbuffered Mode Input Impedance Note VREF VREF RVREF 0.040 VDD-0.040 Note Code 2048, VREF 0.2v p-p, Unbuffered Mode VOS/°C -0.75 ±0.3 ±0.02 -0.77 -0.15 +0.75 Bits ppm/°C ppm/°C ppm/°C Device Monotonic Code 0x000h -45°C 25°C +25°C 85°C Code 0xFFFh, including offset error. 0.25 Input unbuffered, digital inputs grounded, output unloaded, code 0x000 Units Conditions
ISHDN ISHDN_SW VPOR
G/°C
design, production tested. small quantify.
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AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, AVSS VREF 2.048V external, output buffer gain GND, +85°C. Typical values 25°C Parameters Input Capacitance Unbuffered Mode Multiplier Mode Bandwidth CVREF fVREF fVREF Multiplier Mode Total Harmonic Distortion Output Amplifier Output Swing VOUT 0.010 0.040 0.55 Accuracy better than VOUT (VDD degrees V/µs Within final value from full-scale range Note change around major carry (0111.1111 1000.0000) Note Note THDVREF Units VREF 2.048V ±0.1 Vp-p, unbuffered, VREF 2.048V ±0.1 Vp-p, unbuffered, VREF 2.5V ±0.1 Vp-p, Frequency Conditions
Phase Margin Slew Rate Short Circuit Current Settling Time Dynamic Performance DAC-to-DAC Crosstalk Major Code Transition Glitch Digital Feedthrough Analog Crosstalk Note
tsettling
nV-s nV-s nV-s nV-s
design, production tested. small quantify.
EXTENDED TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, AVSS VREF 2.048V, output buffer gain GND, Typical values +125°C characterization simulation. Parameters Power Requirements Input Voltage Input Current MCP4921 Input Current MCP4922 Hardware Shutdown Current Software Shutdown Current Power-On Reset threshold Accuracy Resolution Error Offset Error Offset Error Temperature Coefficient Note VOS/°C ±0.25 ±0.02 Bits ppm/°C Device Monotonic Code 0x000h +25°C +125°C 1.85 Input unbuffered, digital inputs grounded, output unloaded, code 0x000 Units Conditions
ISHDN ISHDN_SW VPOR
design, production tested. small quantify.
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EXTENDED TEMPERATURE SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, AVSS VREF 2.048V, output buffer gain GND, Typical values +125°C characterization simulation. Parameters Gain Error Gain Error Temperature Coefficient Input Amplifier (VREF Input) Input Range Buffered Mode VREF 0.040 VDD0.040 Note Code 2048, VREF 0.2v p-p, -0.10 Units ppm/°C Conditions Code 0xFFFh, including offset error
G/°C
Input Range Unbuffered Mode Input Impedance Input Capacitance Unbuffered Mode Multiplying Mode Bandwidth
VREF RVREF CVREF fVREF fVREF
VREF 2.5V ±0.1 Vp-p, Unbuffered, VREF 2.5V ±0.1 Vp-p, Unbuffered, VREF 2.5V ±0.1Vp-p, Frequency Accuracy better than VOUT (VDD degrees V/µs Within final value from full-scale range Note change around major carry (0111.1111 1000.0000) Note Note Unbuffered Mode
Multiplying Mode Total Harmonic Distortion Output Amplifier Output Swing
THDVREF
VOUT
Phase Margin Slew Rate Short Circuit Current Settling Time Dynamic Performance Crosstalk Major Code Transition Glitch Digital Feedthrough Analog Crosstalk Note
tsettling
0.010 0.040 0.55
nV-s nV-s nV-s nV-s
design, production tested. small quantify.
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CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V 5.5V, +125°C. Typical values +25°C. Parameters Schmitt Trigger High-Level Input Voltage (All digital input pins) Schmitt Trigger Low-Level Input Voltage (All digital input pins) Hysteresis Schmitt Trigger Inputs Input Leakage Current Digital Capacitance (All inputs/outputs) Clock Frequency Clock High Time Clock Time Fall First Rising Edge Data Input Setup Time Data Input Hold Time Rise Rise Hold Time High Time LDAC Pulse Width LDAC Setup Time Idle Time before Fall Note Units Conditions
VHYS ILEAKAGE CIN, COUT FCLK tCSSR tCHS tCSH tIDLE
0.05
SHDN LDAC VREF AVSS 5.0V, +25°C, fcLK (Note +25°C (Note Note Note Applies only when falls with high. (Note Note Note Note Note Note Note Note
design characterization, production tested.
tCSH tIDLE tCSSR Mode Mode tCHS
LDAC
FIGURE 1-1:
SPIInput Timing.
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TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, +2.7V +5.5V, AVSS GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note °C/W °C/W °C/W °C/W °C/W °C/W +125 +125 +150 Note Units Conditions
MCP492X family DACs operate over this extended temperature range, with reduced performance. Operation this range must cause exceed Maximum Junction Temperature 150°C.
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Note:
TYPICAL PERFORMANCE CURVES
graphs tables provided following this note statistical summary based limited number samples provided informational purposes only. performance characteristics listed herein tested guaranteed. some graphs tables, data presented outside specified operating range (e.g., outside specified power supply range) therefore outside warranted range.
Note: Unless otherwise indicated, +25°C, AVSS VREF 2.048V, Gain
Absolute (LSB) (LSB) -0.1 -0.2 -0.3 1024 2048 Code (Decimal) 3072 4096 0.0766 0.0764 0.0762 0.076 0.0758 0.0756 0.0754 0.0752 0.075
Ambient Temperature
FIGURE 2-1:
Code.
FIGURE 2-4: Temperature.
0.35 Absolute (LSB) 0.25 0.15 0.05
Absolute Ambient
(LSB)
-0.1
-0.2 1024 2048 3072
125C
4096
Code (Decimal)
Voltage Reference
FIGURE 2-2: Temperature.
(LSB) -0.1 -0.2 -0.3 -0.4 1024
Code Ambient
FIGURE 2-5: Reference.
Absolute Voltage
2048
3072
4096
Code (Decimal)
FIGURE 2-3: Gain=1.
Code VREF.
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Note: Unless otherwise indicated, +25°C, AVSS VREF 2.048V, Gain
1024 2048 (LSB) 3072 4096 1024
Ambient Temperature
VREF
125C
(LSB)
Code (Decimal)
2048 3072 Code (Decimal)
4096
FIGURE 2-6: Temperature.
Absolute (LSB)
Code Ambient
FIGURE 2-9:
Code VREF.
(LSB) 1024 2048 Code (Decimal) 3072 4096
Ambient Temperature
FIGURE 2-7: Temperature.
Absolute Ambient
FIGURE 2-10:
Note:
Code.
Single device graph (Figure 2-10) illustration code effect.
Absolute (LSB)
Voltage Reference
FIGURE 2-8:
Absolute VREF.
2004 Microchip Technology Inc.
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Note: Unless otherwise indicated, +25°C, AVSS VREF 2.048V, Gain
(µA) Ambient Temperature (°C)
5.5V 5.0V 4.0V 3.0V 2.7V
5.5V 5.0V 4.0V 3.0V 2.7V
(µA)
Ambient Temperature
FIGURE 2-11: MCP4921 Ambient Temperature VDD.
Occurrence (µA)
FIGURE 2-14: MCP4922 Ambient Temperature VDD.
(µA)
FIGURE 2-12: (VDD 2.7V).
Occurrence
MCP4921 Histogram
Occurrence
FIGURE 2-15: (VDD 2.7V).
Occurrence
MCP4922 Histogram
(µA)
(µA)
FIGURE 2-13: (VDD 5.0V).
MCP4921 Histogram
FIGURE 2-16: (VDD 5.0V).
MCP4922 Histogram
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Note: Unless otherwise indicated, +25°C, AVSS VREF 2.048V, Gain
5.5V
-0.08
5.0V
5.5V
Gain Error
ISHDN (µA)
-0.1
5.0V
4.0V 3.0V 2.7V
-0.12
4.0V 3.0V 2.7V
-0.14
Ambient Temperature
-0.16 Ambient Temperature
FIGURE 2-17: Hardware Shutdown Current Ambient Temperature VDD.
5.5V
FIGURE 2-20: Gain Error Ambient Temperature VDD.
5.5V 5.0V
ISHDN_SW (µA)
5.0V
Threshold
4.0V 3.0V 2.7V
4.0V
Ambient Temperature
3.0V 2.7V
Ambient Temperature
FIGURE 2-18: Software Shutdown Current Ambient Temperature VDD.
0.12
FIGURE 2-21: High Threshold Ambient Temperature VDD.
Threshold Ambient Temperature
3.0V 2.7V 4.0V
Offset Error 0.08 0.06 0.04 0.02 -0.02 Ambient Temperature
5.0V 4.0V 3.0V 2.7V
5.5V 5.0V
5.5V
FIGURE 2-19: Offset Error Ambient Temperature VDD.
FIGURE 2-22: Threshold Ambient Temperature VDD.
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Note: Unless otherwise indicated, +25°C, AVSS VREF 2.048V, Gain
2.25 1.75 1.25 0.75 0.25 Ambient Temperature 0.0045 VOUT_LOW Limit (Y-AVSS)(V) 0.004 0.0035 0.003
5.0V 5.5V
5.5V 5.0V 4.0V 3.0V 2.7V
VIN_SPI Hysteresis
0.0025 0.002 0.0015 Ambient Temperature
4.0V 3.0V 2.7V
FIGURE 2-23: Input Hysteresis Ambient Temperature VDD.
VREF_UNBUFFERED Impedance (kOhm)
FIGURE 2-26: VOUT Limit Ambient Temperature VDD.
IOUT_HI_SHORTED (mA)
5.5V 5.0V 4.0V 3.0V 2.7V
5.5V 2.7V
Ambient Temperature
Ambient Temperature
FIGURE 2-24: VREF Input Impedance Ambient Temperature VDD.
0.045 VOUT_HI Limit (VDD-Y)(V) 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 Ambient Temperature
5.5V 5.0V 4.0V
FIGURE 2-27: IOUT High Short Ambient Temperature VDD.
VREF=4.0
VOUT
Output Shorted
3.0V 2.7V
IOUT (mA)
Output Shorted
FIGURE 2-25: VOUT High Limit Ambient Temperature VDD.
FIGURE 2-28:
IOUT VOUT. Gain
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MCP4921/4922
Note: Unless otherwise indicated, +25°C, AVSS VREF 2.048V, Gain
VOUT VOUT LDAC Time µs/div) LDAC Time µs/div)
FIGURE 2-29:
VOUT Rise Time 100%.
FIGURE 2-32:
VOUT Rise Time
VOUT VOUT LDAC Time µs/div) LDAC Time µs/div)
FIGURE 2-30:
VOUT Fall Time.
FIGURE 2-33: Shutdown.
VOUT Rise Time Exit
VOUT
LDAC Time µs/div)
Ripple Rejection (dB)
Frequency (Hz)
FIGURE 2-31:
VOUT Rise Time 50%.
FIGURE 2-34:
PSRR Frequency.
2004 Microchip Technology Inc.
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Note: Unless otherwise indicated, +25°C, AVSS VREF 2.50V, Gain
Attenuation (dB)
1184 1440 1696 1952 2208 2464 2720 2976 3232 3488 3744
qVREF qVOUT
-135
Frequency (kHz)
1,000
-180
1184 1440 1696 1952 2208 2464 2720 2976 3232 3488 3744
Frequency (kHz)
1,000
FIGURE 2-35:
Multiplier Mode Bandwidth.
FIGURE 2-37:
Phase Shift.
Figure 2-35 calculation: Attenuation (dB) (VOUT/VREF) (G(D/4096))
Bandwidth (kHz)
FIGURE 2-36: Codes.
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Worst Case Codes (decimal)
Bandwidth Worst
2004 Microchip Technology Inc.
MCP4921/4922
DESCRIPTIONS
descriptions pins listed Table 3-1.
TABLE 3-1:
MCP4921
FUNCTION TABLE
MCP4922 Symbol LDAC SHDN VOUTB VREFB AVSS VREFA VOUTA Function Positive Power Supply Input (2.7V 5.5V) Connection Chip Select Input Serial Clock Input Serial Data Input Connection Connection Syncronization input used transfer settings from serial latches output latches. Hardware Shutdown Input DACB Output DACB Voltage Input (AVSS VDD) Analog ground DACA Voltage Input (AVSS VDD) DACA Output
Positive Power Supply Input (VDD)
Hardware Shutdown Input (SHDN)
positive power supply input. input power supply relative AVSS range from 2.7V 5.5V. decoupling capacitor recommended achieve maximum performance.
SHDN hardware shutdown input that requires active-low input signal configure DACs their low-power Standby mode.
Chip Select (CS)
chip select input, which requires active-low signal enable serial clock data functions.
DACx Outputs (VOUTA, VOUTB)
VOUTA VOUTB outputs. output amplifier drives these pins with range AVSS VDD.
Serial Clock Input (SCK)
compatible serial clock input.
DACX Voltage Reference Inputs (VREFA, VREFB)
Serial Data Input (SDI)
compatible serial data input.
VREFA VREFB voltage reference inputs. analog signal these pins utilized reference voltage string DAC. input signal range from AVSS VDD.
Latch Input (LDAC)
Analog Ground (AVSS)
LDAC (the latch syncronization input) transfers input latch registers registers (output latches) when low. also tied transfer rising edge desired.
AVSS analog ground pin.
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GENERAL OVERVIEW
Digital Input Code Output Ideal transfer function Actual transfer function MCP492X devices voltage output string DACs. These devices include input amplifiers, rail-to-rail output amplifiers, reference buffers, shutdown resetmanagement circuitry. Serial communication conforms protocol. MCP492X operates from 2.7V 5.5V supplies. coding these devices straight binary ideal output voltage given Equation 4-1, where selected gain 2x), represents digital input value represents number bits resolution 12).
EQUATION 4-1:
SIZE
VOUT ideal voltage difference between successive codes. Table illustrates calculate LSB.
FIGURE 4-1: 4.0.2
Accuracy.
TABLE 4-1:
Device MCP492X MCP492X
SIZES
VREF, GAIN External VREF, External VREF, SIZE VREF/4096 VREF/4096
ACCURACY
error measure variations code widths from ideal code width. error zero would imply that every code exactly wide.
4.0.1
ACCURACY
Digital Input Code Narrow code Output Actual transfer function Ideal transfer function
error these devices maximum deviation between actual code transition point corresponding ideal transition point once offset gain errors have been removed. These endpoints from 0x000 0xFFF. Refer Figure 4-1. Positive means transition(s) later than ideal. Negative means transition(s) earlier than ideal.
Wide code,
FIGURE 4-2: 4.0.3
Accuracy.
OFFSET ERROR
Offset error deviation from zero voltage output when digital input code zero.
4.0.4
GAIN ERROR
Gain error deviation from ideal output, VREF- LSB, excluding effects offset error.
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MCP4921/4922
4.1.1
Circuit Descriptions
OUTPUT AMPLIFIERS
DACs' outputs buffered with low-power, precision CMOS amplifier. This amplifier provides offset voltage noise. output stage enables device operate with output voltages close power supply rails. Refer Section "Electrical Characteristics" range load conditions. addition resistive load driving capability, amplifier will also drive high capacitive loads without oscillation. amplifiers' strong outputs allow VOUT used programmable voltage reference system. Selecting gain reduces bandwidth amplifier Multiplying mode. Refer Section "Electrical Characteristics" Multiplying mode bandwidth given load conditions.
power supply voltage less than threshold (VPOR 2.0V, typical), DACs will held their reset state. They will remain that state until VPOR subsequent write command received. Figure shows typical power supply transient pulse duration required cause reset occur, well relationship between duration trip voltage. decoupling capacitor mounted close possible provides additional transient immunity.
Supply Voltages VPOR VPOR Transient Duration
4.1.1.1
Programmable Gain Block
Transient Duration (µs)
rail-to-rail output amplifier configurable gain allowing optimal full-scale outputs differing voltage reference inputs. output amplifier gain selections, gain gain output range ideally 0.000V 4095/4096 VREF when 0.000 4095/4096 VREF when default value this gain yielding ideal full-scale output 0.000V 4.096V when utilizing 2.048V VREF. Note that near rail-to-rail CMOS output buffer's ability approach AVSS establish practical range limitations. output swing specification Section "Electrical Characteristics" defines range given load condition.
Time
Transients below curve will cause reset
+25°C
Transients above curve will cause reset
VPOR
4.1.2
VOLTAGE REFERENCE AMPLIFIERS
FIGURE 4-3: Response. 4.1.4
Typical Transient
input buffer amplifiers MCP492X devices provide offset voltage noise. configuration each allows VREF input bypass input buffer amplifiers, achieving Buffered Unbuffered mode. default value this unbuffered. Buffered mode provides very high input impedance, with only minor limitations input range frequency response. Unbuffered mode provides wide input range VDD), with typical input impedance
SHUTDOWN MODE
4.1.3
POWER-ON RESET CIRCUIT
Power-On Reset (POR) circuit ensures that DACs power-up with SHDN (high-impedance). devices will continue have high-impedance output until valid write command performed either registers LDAC meets input threshold.
Shutdown mode entered using either hardware software commands. hardware (SHDN) only available MCP4922. During Shutdown mode, supply current isolated from most internal circuitry. serial interface remains active, thus allowing write command bring device Shutdown mode. When output amplifiers shut down, feedback resistance (typically produces high-impedance path AVSS. device will remain Shutdown mode until SHDN brought high write command with latched into device. When changed from Shutdown Active mode, output settling time takes greater than standard Active mode settling time (4.5 µs).
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SERIAL INTERFACE
Overview
Write Command
MCP492X family designed interface directly with Serial Peripheral Interface (SPI) port, available many microcontrollers, supports Mode Mode 1,1. Commands data sent device pin, with data being clocked-in rising edge SCK. communications unidirectional and, thus, data cannot read MCP492X. must held duration write command. write command consists bits used configure DAC's control data latches. Register details input registers used configure load DACA DACB registers. Refer Figure Section "Electrical Characteristics" Electrical Characteristics table detailed input output timing specifications both Mode Mode operation.
write command initiated driving low, followed clocking four configuration bits data bits into rising edge SCK. then raised, causing data latched into selected DAC's input registers. MCP492X utilizes double-buffered latch structure allow both DACA's DACB's outputs syncronized with LDAC pin, desired. Upon LDAC achieving state, values held DAC's input registers transferred into DACs' output registers. outputs will transition value held DACX register. writes MCP492X 16-bit words. clocks past will ignored. most significant four bits configuration bits. remaining bits data bits. data transferred into device with high. This transfer will only occur clocks have been transferred into device. rising edge occurs prior, shifting data into input registers will aborted.
REGISTER 5-1:
Upper Half:
WRITE COMMAND REGISTER
SHDN Lower Half:
A/B: DACA DACB Select Write DACB Write DACA
BUF: VREF Input Buffer Control Buffered Unbuffered
Output Gain Select (VOUT VREF D/4096) (VOUT VREF D/4096) SHDN: Output Power Down Control Output Power Down Control Output buffer disabled, Output high impedance D11:D0: Data bits number which sets output value. Contains value between 4095.
11-0
Legend Readable Value Writable Unimplemented bit, read cleared unknown
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MCP4921/4922
config bits data bits (mode 1,1) (mode 0,0)
SHDN
LDAC
VOUT
FIGURE 5-1:
Write Command.
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Note:
TYPICAL APPLICATIONS
time this data sheet's release, circuit examples completed testing. Your results vary. VREFA
MCP492X devices general purpose DACs intended used applications where precision, low-power with moderate bandwidth required. Applications generally suited MCP492X devices include: Point Offset Trimming Sensor Calibration Digitally-Controlled Multiplier/Divider Portable Instrumentation (Battery Powered) Motor Feedback Loop Control
MCP492X
VOUTA VREFB VOUTB VREFA VOUTA VREFB VOUTB
MCP492X
AVSS
LDAC
Digital Interface
MCP492X utilizes 3-wire syncronous serial protocol transfer DACs' setup output values from digital source. serial protocol interfaced SPIor Microwire peripherals common many microcontrollers, including Microchip's PICmicro® MCUs dsPICDSC family microcontrollers. addition three serial connections (CS, SDI), LDAC signal syncronizes when serial settings latched into DAC's output from serial input latch. Figure illustrates required connections. Note that LDAC active-low. desired, this input tied reduce required connections from Write commands will latched directly into output latch when valid clock transmission been received been raised.
AVSS
AVSS
FIGURE 6-1: Diagram.
Typical Connection
Layout Considerations
Power Supply Considerations
typical application will require by-pass capacitor order filter high-frequency noise. noise induced onto power supply's traces result changes DAC's output. bypass capacitor helps minimize effect these noise sources signal integrity. Figure illustrates appropriate bypass strategy. this example, recommended bypass capacitor value This capacitor should placed close device power (VDD) possible (within mm). power source supplying these devices should clean possible. application circuit separate digital analog power supplies, AVDD AVSS should reside analog plane.
Inductively-coupled transients digital switching noise degrade input output signal integrity, potentially masking MCP492X's performance. Careful board layout will minimize these effects increase signal-to-noise ratio (SNR). Bench testing shown that multi-layer board utilizing low-inductance ground plane, isolated inputs, isolated outputs proper decoupling critical achieving performance that silicon capable providing. Particularly harsh environments require shielding critical signals. Breadboards wire-wrapped boards recommended noise desired.
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PICmicro® Microcontroller
MCP4921/4922
Single-Supply Operation
6.4.1.1 Decreasing Output Step Size
MCP492X rail-to-rail (R-R) input output designed operate with range 2.7V 5.5V. output amplifier robust enough drive common, small-signal loads directly, thus eliminating cost size external buffer most applications. output range reduced relative AVSS, simply reducing VREF will reduce magnitude each output step. application calibrating threshold diode, transistor resistor tied AVSS VREF, theshold range 0.8V desired provide resolution. common methods achieve 0.8V range either reduce VREF 0.82V voltage divider DAC's output. VREF available with desired output value, using that VREF option. Occasionally, when using low-voltage VREF, noise floor causes error that intolerable. voltage divider method provides some advantages when VREF needs very when desired output voltage available. this case, larger value VREF used while resistors scale output range down precise desired level. Using common VREF output availability cost advantages. Example illustrates this concept. Note that voltage divider connected AVSS VREF, depending application's requirements. MCP492X's low, ±0.75 (max.) performance critical meeting calibration accuracy production.
6.4.1
POINT CALIBRATION
common application with MCP492X's performance digitally-controlled points and/or calibration variable parameters, such sensor offset slope. 12-bit resolution provides 4096 output steps. 4.096V VREF provided, would represent resolution. smaller output step size desired, output range would need reduced.
Rsense VREF VOUT
VCC+
Comparator
Vtrip VCC-
MCP492X
SPI3 trip
Gain select Digital value 4096)
EXAMPLE 6-1:
Point Threshold Calibration.
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MCP4921/4922
6.4.1.2 Building "Window"
When calibrating point threshold sensor, rarely does sensor utilize entire output range DAC. size adequate meet application's accuracy needs, then resolution sacrificed without consequences. greater accuracy needed, then output range will need reduced increase resolution around desired threshold. threshold near VREF AVSS, then creating "window" around threshold several advantages. simple method create this "window" voltage divider network with pull-up pulldown resistor. Example Example illustrates this concept. MCP492X's low, ±0.75 (max.) performance critical meet calibration accuracy production.
VCC+ VREF VOUT
Rsense
VCC+
Comparator Vtrip VCCVCC-
MCP492X
SPI3
Gain select Digital value 4096) VOUT
Thevenin Equivalent
trip
EXAMPLE 6-2:
Single-Supply "Window" DAC.
DS21897A-page
2004 Microchip Technology Inc.
MCP4921/4922
Bipolar Operation
Bipolar operation achievable using MCP492X using external operational amplifier amp). This configuration desirable wide variety availability amps. This allows general purpose DAC, with cost availability advantages, meet almost desired output voltage range, power noise performance. Example illustrates simple bipolar voltage source configuration. allow gain selected, while shift DAC's output selected offset. Note that tied VREF, instead AVSS, higher offset desired. Note that pull-up VREF could used, instead higher offset desired.
VREF VREF VOUT VIN+ VCC- SPI3 VOUT VREF VIN+ VIN+ VCC+
MCP492X
Gain select Digital value 4096)
EXAMPLE 6-3: 6.5.1
Digitally-Controlled Bipolar Voltage Source.
Next, solve setting 4096, knowing that output needs +2.05V. 2.05V 0.5V -1.5VREF then
DESIGN BIPOLAR USING EXAMPLE
output step magnitude with output range ±2.05V desired particular application. Calculate range: +2.05V (-2.05V) 4.1V. Calculate resolution needed: 4.1V/1 4100 Since 4096, 12-bit resolution desired. amplifier gain (R2/R1), multiplied VREF, must equal desired minimum output achieve bipolar operation. Since gain realized choosing resistor values (R1+R2), VREF source needs determined first. VREF 4.1V used, solve gain setting knowing that output needs -2.05V. equation simplified 2.05 2.05
gain will 0.5.
2004 Microchip Technology Inc.
DS21897A-page
MCP4921/4922
Selectable Gain Offset Bipolar Voltage Output Using Dual
This circuit typically used Multiplier mode ideal linearizing sensor whose slope offset varies. Refer Section "Using Multiplier Mode" more information Multiplier mode. equation design bipolar "window" would utilized populated.
some applications, precision digital control output range desirable. Example illustrates MCP4922 achieve this bipolar single-supply application.
VREFA VOUTA VCC+
VCC+
MCP492X
VREFB DACA (Gain Adjust) VOUTB
MCP492X
SPI3
DACB (Offset Adjust)
VCC-
0.1uF
VCC-
VOUTB REFB OUTB VCC- OUTA Offset Adjust Gain Adjust
OUTA VREFA AVSS Gain select Digital value 4096)
Bipolar "Window" using Thevenin Equivalent VCC- OUTB VIN+ OUTA Offset Adjust Gain Adjust
EXAMPLE 6-4:
Bipolar Voltage Source With Selectable Gain Offset.
DS21897A-page
2004 Microchip Technology Inc.
MCP4921/4922
Designing Double-Precision Using Dual
Calculate resolution needed: 4.1V/1uV 4.1e06. Since 4.2e06, 22-bit resolution desired. Since ±0.75 LSB, this design attempted with MCP492X. Since DACB`s VOUTB resolution output only needs "pulled" 1/1000 meet target. Dividing VOUTA 1000 would allow application compensate DACB`s error. 100, then needs resulting transfer function perfectly linear, shown equation Example 6-5.
Example illustrates design single-supply voltage output capable 24-bit resolution from dual 12-bit DAC. This design simply voltage divider with buffered output. example, similar application developed Section 6.5.1 "Design bipolar using Example 6-3" required resolution instead range 4.1V, then 12-bit resolution would adequate.
VREF
DACA (Fine Adjust) VOUTA VOUTB DACB (Course Adjust)
VCC+
MCP492X
MCP492X
SPI3
VCC-
OUTA REFA VOUTA VOUTB
OUTB VREFB
Gain select Digital value 4096)
EXAMPLE 6-5:
Simple, Double-Precision DAC.
2004 Microchip Technology Inc.
DS21897A-page
MCP4921/4922
Building Programmable Current Source Using Multiplier Mode
MCP492X ideally suited multiplier/ divider signal chain. Common applications include: precision programmable gain/attenuator amplifiers loop controls (motor feedback). wide input range VDD) Unbuffered mode near range Buffered mode: bandwidth, selectible 1x/2x gain power consumption give maximum flexibility meet application's needs. configure MCP492X Multiplier mode, connect input signal VREF serially configure DAC's input buffer, gain output value. DAC's output utilize Examples 6-6, depending application requirements. Example illustration operate motor control feedback loop. Gain Select configured mode resulting input signal will attenuated D/4096. Gain Select configured mode codes 2048 attenuate signal, while codes 2048 gain signal. VOUT (D/2048). VCC- -Rsense Gain select Digital value 4096) VREF SPIVDD VOUT VCC+ Rsense 12-bit provides significantly more gain/attenuation resolution when compared typical Programmable Gain Amplifiers. Adding buffer output, illustrated Examples 6-6, extends output range power meet precise needs application. VRPM_SET VRPM
Example illustrates variation voltage follower design where sense resistor used convert DAC's voltage output into digitally-selectable current source. Adding resistor network from Example would advantageous this application. smaller Rsense less power dissipated across However, this also reduces resolution that current controlled with. voltage divider, "window", configuration would allow range reduced, thus increasing resolution around range interest. When working with very small sensor voltages, plan eliminating amplifier's offset error storing DAC's setting under known sensor conditions.
VREF
VOUT VCC+ LOAD
MCP492X
SPI
MCP492X
EXAMPLE 6-6:
Digitally-Controlled Current Source.
VCC- Rsense
EXAMPLE 6-7:
Multiplier Mode.
DS21897A-page
2004 Microchip Technology Inc.
MCP4921/4922
DEVELOPMENT SUPPORT
Evaluation Demonstration Boards Application Notes Tech Briefs
Mixed Signal PICtailBoard supports MCP492X family devices. Please refer www.microchip.com further information this products capabilities availability.
Application notes illustrating performace implementation MCP492X planned currently released. Please refer www.microchip.com further information.
2004 Microchip Technology Inc.
DS21897A-page
MCP4921/4922
PACKAGING INFORMATION
Package Marking Information
8-Lead MSOP XXXXXX YWWNNN Example: 4921E 412256
8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW
Example: MCP4921 E/P256 0412
8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW
Example: MCP4921 E/SN0412
Legend:
XX.X
Customer specific information* Year code (last digits calendar year) Week code (week January week `01') Alphanumeric traceability code
Note:
event full Microchip part number cannot marked line, will carried over next line thus limiting number available characters customer specific information.
Standard marking consists Microchip part number, year code, week code, traceability code (facility code, mask rev#, assembly code). marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
DS21897A-page
2004 Microchip Technology Inc.
MCP4921/4922
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP4922) Example:
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
MCP4922E/P 0412256
14-Lead SOIC (150 mil) (MCP4922)
Example:
XXXXXXXXXX XXXXXXXXXX YYWWNNN
MCP4922E/SL 0412256
14-Lead TSSOP (MCP4922)
Example:
XXXXXX YYWW
4922E/ST 0412
2004 Microchip Technology Inc.
DS21897A-page
MCP4921/4922
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Number Pins .026 Pitch .043 Overall Height .030 .033 .037 Molded Package Thickness .000 .006 Standoff .193 TYP. Overall Width .118 Molded Package Width .118 Overall Length .016 .024 .031 Foot Length Footprint (Reference) .037 Foot Angle Lead Thickness .003 .006 .009 Lead Width .009 .012 .016 Mold Draft Angle Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side.
Units Dimension Limits
INCHES
MILLIMETERS* 0.65 0.75 0.85 0.00 4.90 3.00 3.00 0.40 0.60 0.95 0.08 0.22
1.10 0.95 0.15
0.80 0.23 0.40
JEDEC Equivalent: MO-187
Drawing C04-111
DS21897A-page
2004 Microchip Technology Inc.
MCP4921/4922
8-Lead Plastic Dual In-line (PDIP)
Number Pins Pitch Seating Plane Molded Package Thickness Base Seating Plane Shoulder Shoulder Width Molded Package Width Overall Length Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Spacing Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic
Units Dimension Limits
INCHES* .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430
MILLIMETERS 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92
Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side. JEDEC Equivalent: MS-001 Drawing C04-018
2004 Microchip Technology Inc.
DS21897A-page
MCP4921/4922
8-Lead Plastic Small Outline (SN) Narrow, (SOIC)
Number Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic
Units Dimension Limits
.053 .052 .004 .228 .146 .189 .010 .019 .008 .013
INCHES* .050 .061 .056 .007 .237 .154 .193 .015 .025 .009 .017
.069 .061 .010 .244 .157 .197 .020 .030 .010 .020
MILLIMETERS 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0.20 0.23 0.33 0.42
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 0.25 0.51
Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side. JEDEC Equivalent: MS-012 Drawing C04-057
DS21897A-page
2004 Microchip Technology Inc.
MCP4921/4922
14-Lead Plastic Dual In-line (PDIP)
Number Pins Pitch Seating Plane .140 .170 Molded Package Thickness .115 .145 Base Seating Plane .015 Shoulder Shoulder Width .300 .313 .325 Molded Package Width .240 .250 .260 Overall Length .740 .750 .760 Seating Plane .125 .130 .135 Lead Thickness .008 .012 .015 Upper Lead Width .045 .058 .070 Lower Lead Width .014 .018 .022 Overall Spacing .310 .370 .430 Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side. JEDEC Equivalent: MS-001 Drawing C04-005
Units Dimension Limits
INCHES* .100 .155 .130
MILLIMETERS 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92
2004 Microchip Technology Inc.
DS21897A-page
MCP4921/4922
14-Lead Plastic Small Outline (SL) Narrow, (SOIC)
Number Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic
Units Dimension Limits
.053 .052 .004 .228 .150 .337 .010 .016 .008 .014
INCHES* .050 .061 .056 .007 .236 .154 .342 .015 .033 .009 .017
.069 .061 .010 .244 .157 .347 .020 .050 .010 .020
MILLIMETERS 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0.20 0.23 0.36 0.42
1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 0.25 0.51
Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side. JEDEC Equivalent: MS-012 Drawing C04-065
DS21897A-page
2004 Microchip Technology Inc.
MCP4921/4922
14-Lead Plastic Thin Shrink Small Outline (ST) (TSSOP)
Number Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic
Units Dimension Limits
INCHES .026 .035 .004 .251 .173 .197 .024 .006 .010
.033 .002 .246 .169 .193 .020 .004 .007
.043 .037 .006 .256 .177 .201 .028 .008 .012
MILLIMETERS* 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0.09 0.15 0.20 0.19 0.25 0.30
Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .005" (0.127mm) side. JEDEC Equivalent: MO-153 Drawing C04-087
2004 Microchip Technology Inc.
DS21897A-page
MCP4921/4922
NOTES:
DS21897A-page
2004 Microchip Technology Inc.
MCP4921/4922
PRODUCT IDENTIFICATION SYSTEM
order obtain information, e.g., pricing delivery, refer factory listed sales office. PART Device Temperature Range Package Examples:
MCP4921T-E/SN: Tape Reel Extended Temperature, SOIC package. MCP4921T-E/MS: Tape Reel Extended Temperature, MSOP package. MCP4921-E/SN: Extended Temperature, SOIC package. MCP4921-E/MS: Extended Temperature, MSOP package. MCP4921-E/P: Extended Temperature, PDIP package. MCP4922T-E/SL: Tape Reel Extended Temperature, 14LD SOIC package. Tape Reel Extended Temperature, 14LD TSSOP package. Extended Temperature, 14LD PDIP package. Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD TSSOP package.
Device: MCP4921: MCP4921T: MCP4922: MCP4922T: 12-Bit with Interface 12-Bit with Interface (Tape Reel) (SOIC, MSOP) 12-Bit with Interface 12-Bit with Interface (Tape Reel) (SOIC, MSOP)
Temperature Range:
-40°C +125°C
Package:
Plastic MSOP, 8-lead Plastic (300 Body), 8-lead, 14-lead Plastic SOIC, (150 Body), 8-lead Plastic SOIC (150 Body), 14-lead Plastic TSSOP (4.4mm Body), 14-lead
MCP4922T-E/ST:
MCP4922-E/P: MCP4922-E/SL: MCP4922-E/ST:
Sales Support
Data Sheets Products supported preliminary Data Sheet have errata sheet describing minor operational differences recommended workarounds. determine errata sheet exists particular device, please contact following: Your local Microchip sales office Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision silicon Data Sheet (include Literature using. Customer Notification System Register site (www.microchip.com/cn) receive most current information products.
2004 Microchip Technology Inc.
DS21897A-page
MCP4921/4922
NOTES:
DS21897A-page
2004 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like intended through suggestion only superseded updates. your responsibility ensure that your application meets with your specifications. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel Total Endurance trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2004, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona Mountain View, California October 2003. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2004 Microchip Technology Inc.
DS21897A-page
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05/28/04
DS21897A-page
2004 Microchip Technology Inc.
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