®1400 complete 400ksps, 12-bit converter which draws only 75mW from su

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®1400 complete 400ksps, 12-bit converter which draws only 75mW from su

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LTC1400 Complete SO-8, 12-Bit, 400ksps with Shutdown
®1400 complete 400ksps, 12-bit converter which draws only 75mW from supplies. This easy-to-use device comes complete with 200ns sample-and-hold precision reference. Unipolar bipolar conversion modes flexibility ADC. LTC1400 power saving modes: Sleep. mode, consumes only power wake convert immediately. Sleep mode, consumes 30µW power typically. Upon power-up from Sleep mode, reference ready (REFRDY) signal available serial data word indicate that reference settled chip ready convert. LTC1400 converts 4.096V unipolar inputs from single supply ±2.048V bipolar inputs from supplies. Maximum specs include ±1LSB INL, ±1LSB 45ppm/°C drift over temperature. Guaranteed performance includes 70dB S/(N 76dB input frequency 100kHz, over temperature. 3-wire serial port allows compact efficient data transfer wide range microprocessors, microcontrollers DSPs.
registered trademarks Linear Technology Corporation. MICROWIRE trademark National Semiconductor Corp.
Complete 12-Bit SO-8 Single Supply Operation Sample Rate: 400ksps Power Dissipation: 75mW (Typ) 72dB S/(N 80dB Nyquist Missing Codes over Temperature Mode with Instant Wake-Up: Sleep Mode: 30µW High Impedance Analog Input Input Range (1mV/LSB): 4.096 2.048V Internal Reference Overdriven Externally 3-Wire Interface DSPs Processors (SPI MICROWIRECompatible)
APPLICATIONS
High Speed Data Acquisition Digital Signal Processing Multiplexed Data Acquisition Systems Audio Telecom Processing Digital Radio Spectrum Analysis Power Battery-Operated Systems Handheld Portable Instruments
TYPICAL APPLICATION
Single Supply, 400kHz, 12-Bit Sampling Converter
Power Consumption Sample Rate
10µF ANALOG INPUT 4.096V) 2.42V REFOUT 10µF
0.1µF
LTC1400
SUPPLY CURRENT (mA)
SERIAL DATA LINK
LTC1400 TA01
VREF
SLEEP MODE BETWEEN CONVERSION SLEEP MODE BETWEEN CONVERSION 6.4MHz CLOCK
CONV DOUT
P1.4 P1.3 P1.2
0.1µF
0.01
0.001 0.01
NORMAL CONVERSION MODE BETWEEN CONVERSION
100k SAMPLE RATE (Hz)
LTC1400 TA02
LTC1400
ABSOLUTE MAXIMUM RATINGS
(Notes
PACKAGE/ORDER INFORMATION
VIEW VREF CONV DOUT
Supply Voltage (VCC) Negative Supply Voltage (VSS). Total Supply Voltage (VCC VSS) Bipolar Operation Only Analog Input Voltage (Note Unipolar Operation 0.3V (VCC 0.3V) Bipolar Operation. (VSS 0.3V) (VCC 0.3V) Digital Input Voltage (Note Unipolar Operation 0.3V Bipolar Operation.(VSS 0.3V) Digital Output Voltage Unipolar Operation 0.3V (VCC 0.3V) Bipolar Operation. (VSS 0.3V) (VCC 0.3V) Power Dissipation. 500mW Operation Temperature Range LTC1400C. 70°C LTC1400I. 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1400CS8 LTC1400IS8
PACKAGE 8-LEAD PLASTIC
TJMAX 150°C, 130°C/
PART MARKING 1400 1400I
Consult factory PDIP packages Military grade parts.
POWER REQUIRE
SYMBOL PARAMETER Positive Supply Voltage (Note Negative Supply Voltage (Note Positive Supply Current
(Note
CONDITIONS Unipolar Bipolar Bipolar Only fSAMPLE 400ksps Mode Sleep Mode fSAMPLE 400ksps, Mode Sleep Mode fSAMPLE 400ksps Mode Sleep Mode 4.75 4.75 2.45
Negative Supply Current
Power Dissipation
5.25 5.25 5.25 20.0
UNITS
ALOG
SYMBOL PARAMETER
(Note
CONDITIONS 4.75V 5.25V (Unipolar) 4.75V 5.25V, 5.25V 2.45V (Bipolar) During Conversions (Hold Mode) Between Conversions (Sample Mode) During Conversions (Hold Mode)
4.096 ±2.048
UNITS
Analog Input Range (Note Analog Input Leakage Current Analog Input Capacitance
LTC1400 VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco IOUT(REF)
ACCURACY
SYMBOL PARAMETER S/(N Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Harmonic Peak Harmonic Spurious Noise Intermodulation Distortion Full Power Bandwidth
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Load Regulation VREF Wake-Up Time from Sleep Mode (Note CONDITIONS IOUT IOUT 4.75V 5.25V 5.25V IOUT CVREF 10µF
DIGITAL PUTS OUTPUTS
SYMBOL PARAMETER High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Level Output Voltage
With internal reference (Notes
CONDITIONS (Note (Note
UNITS Bits ppm/°C
fSAMPLE 400kHz
CONDITIONS 100kHz Input Signal 200kHz Input Signal 100kHz Input Signal 200kHz Input Signal 100kHz Input Signal 200kHz Input Signal fIN1 99.51kHz, fIN2 102.44kHz fIN1 199.12kHz, fIN2 202.05kHz
Commercial Industrial
UNITS
Full Linear Bandwidth (S/(N 68dB)
(Note
2.400
2.420 0.01 0.01
2.440
UNITS ppm/°C LSB/ LSB/ LSB/mA
(Note
CONDITIONS 5.25V 4.75V 4.75V, 10µA 4.75V, 200µA 4.75V, 160µA 4.75V, 1.6mA
UNITS
0.05 0.10
LTC1400
DIGITAL PUTS OUTPUTS
SYMBOL PARAMETER ISOURCE ISINK Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT (Note Output Source Current Output Sink Current
CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ fCLK tCLK tWK(NAP) PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time (Unipolar Mode) (Bipolar Mode Frequency Pulse Width Time Wake from Mode Pulse Width Return Active Mode CONV Setup Time CONV After Leading CONV Pulse Width Time from Sample Mode Aperture Delay Sample-and-Hold
Minimum Delay Between Conversion (Unipolar Mode) (Bipolar Mode Delay Time, DOUT Valid Delay Time, DOUT Hi-Z Time from Previous Data Remains Valid After CLOAD 20pF CLOAD 20pF CLOAD 20pF
denotes specifications which apply over full operating temperature range; other limits typicals 25°C. Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect GND. Note When these voltages taken below (ground unipolar mode) above VCC, they will clamped internal diodes. This product handle input currents greater than 40mA below (ground unipolar mode) above without latch-up. Note When these voltages taken below (ground unipolar mode), they will clamped internal diodes. This product handle input currents greater than 40mA below (ground unipolar mode) without latch-up. These pins clamped VCC. Note fSAMPLE 400kHz, unless otherwise specified.
(Note
CONDITIONS VOUT VOUT VOUT
UNITS
(Note
CONDITIONS (Note fCLK 6.4MHz (Note
UNITS
(Note (Note
(Note (Note Jitter 50ps (Note
Note Recommended operating conditions. Note Guaranteed design, subject test. Note Linearity, offset full-scale specifications apply unipolar bipolar modes. Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from 0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111. Note rising edge CONV starts conversion. CONV returns decision point during conversion, create small errors. best performance ensure that CONV returns either within 120ns after conversion starts (i.e., before first decision) after clock cycle. (Figure Timing Diagram).
LTC1400 TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity Output Code
1.00 1.00 fSAMPLE 400kHz
INTEGRAL NONLINEARITY (LSBs)
DIFFERENTIAL NONLINEARITY (LSBs)
0.50 0.25 -0.25 -0.50 -0.75 -1.00 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
LTC1400 TPC01
0.50 0.25 -0.25 -0.50 -0.75 -1.00 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
LTC1400 TPC02
SIGNAL/(NOISE DISTORTION) (dB)
0.75
Signal-to-Noise Ratio (Without Harmonics) Input Frequency
SPURIOUS-FREE DYNAMIC RANGE (dB)
SIGNAL-TO-NOISE RATIO (dB)
-100 INPUT FREQUENCY (kHz) 1000
LTC1400 TPC08
ACQUISITION TIME (ns)
fSAMPLE 400kHz INPUT FREQUENCY (kHz) 1000
LTC1400 TPC07
AMPLITUDE POWER SUPPLY FEEDTHROUGH (dB)
Reference Voltage Load Current
2.435 2,430
REFERENCE VOLTAGE
2.420 2.415 2.410 2.405 2.400 2.395 2.390 LOAD CURRENT (mA)
-100 RIPPLE FREQUENCY (kHz) (VRIPPLE 1mV) (VRIPPLE 10mV)
SUPPLY CURRENT (mA)
2.425
Integral Nonlinearity Output Code
S/(N Input Frequency Amplitude
fSAMPLE 400kHz INPUT FREQUENCY (kHz) 1000
LTC1400 TPC06
fSAMPLE 400kHz 0.75
-20dB
60dB
Peak Harmonic Spurious Noise Input Frequency
fSAMPLE 400kHz
4500 4000 3500 3000 2500 2000 1500 1000
Acquisition Time Source Impedance
25°C
1000 RSOURCE
10000
LTC1400 TPC05
Power Supply Feedthrough Ripple Frequency
fSAMPLE 400kHz
Supply Current Temperature
fSAMPLE 400kHz
TEMPERATURE (°C)
LTC1400 TPC03
LTC1400 TPC07.5
LTC1400 TPC04
LTC1400
FUNCTIONS
(Pin Positive Supply, Bypass (10µF tantalum parallel with 0.1µF ceramic). (Pin Analog Input. 4.096V (Unipolar), ±2.048V (Bipolar). VREF (Pin 2.42V Reference Output. Bypass (10µF tantalum parallel with 0.1µF ceramic). (Pin Ground. should tied directly analog ground plane. DOUT (Pin conversion result shifted from this pin. (Pin Clock. This clock synchronizes serial data transfer. minimum pulse 50ns will cause wake from Sleep mode. CONV (Pin Conversion Start Signal. This active high signal starts conversion rising edge. Keeping pulsing CONV two/four times will into Nap/Sleep mode. (Pin Negative Supply. bipolar operation. Bypass with 0.1µF ceramic. should tied unipolar operation.
FUNCTIONAL BLOCK DIAGRA
VREF 2.42V
CONV CONTROL LOGIC SUCCESSIVE APPROXIMATION REGISTER/PARALLEL SERIAL CONVERTER
TEST CIRCUITS
DOUT CLOAD DOUT CLOAD
Hi-Z Hi-Z
CSAMPLE
ZEROING SWITCH
12-BIT CAPACITIVE
COMP
DOUT
LTC1400 BD01
Hi-Z Hi-Z
LTC1400 TC01
LTC1400
APPLICATIONS INFORMATION
Conversion Details LTC1400 uses successive approximation algorithm internal sample-and-hold circuit convert analog signal 12-bit serial output based precision internal reference. control logic provides easy interface microprocessors DSPs through 3-wire connections. rising edge CONV input starts conversion. start conversion successive approximation register (SAR) reset. Once conversion cycle begun cannot restarted. During conversion, internal 12-bit capacitive output sequenced from most significant (MSB) least significant (LSB). Referring Figure input connects sample-and-hold capacitor during acquired phase comparator offset nulled feedback switch. this acquire phase, typically takes 200ns sample-and-hold capacitor acquire analog signal. During convert phase, comparator feedback switch opens, putting comparator into compare mode. input switches connect CSAMPLE ground, injecting analog input charge onto summing junction. This input charge successively compared with binary-weighted charges supplied capacitive DAC. decisions made high speed comparator. conversion, output balances input charge. contents 12-bit data word) which represent input voltage, output through serial DOUT.
SAMPLE SAMPLE HOLD CDAC VDAC DOUT
LTC1400
AMPLITUDE (dB)
CSAMPLE
COMP
Figure Input
Dynamic Performance LTC1400 excellent high speed sampling capability. (Fast Fourier Transform) test techniques used test ADC's frequency response, distortion noise rated throughput. applying distortion sine wave analyzing digital output using algorithm, ADC's spectral content examined frequencies outside fundamental. Figure shows typical LTC1400 plot. Signal-to-Noise Ratio signal-to-noise plus distortion ratio [S/(N ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited frequencies from half sampling frequency. Figure shows typical spectral content with 400kHz sampling rate 100kHz input. dynamic performance excellent input frequencies Nyquist limit 200kHz shown Figure
-100 -110 -120 FREQUENCY (kHz)
LTC1400 F02a
fSAMPLE 400kHz 94.824kHz SINAD 72.5dB 82dB
Figure LTC1400 Nonaveraged, 4096 Point Plot with 100kHz Input Frequency Bipolar Mode
Effective Number Bits effective number bits (ENOBs) measurement effective resolution directly related S/(N equation:
1.76 6.02
LTC1400
APPLICATIONS INFORMATION
fSAMPLE 400kHz 199.121kHz SINAD 72.1dB 80dB
AMPLITUDE (dB)
-100 -110 -120 FREQUENCY (kHz)
LTC1400 F02b
AMPLITUDE BELOW FUNDAMENTAL)
Figure LTC1400 Nonaveraged, 4096 Point Plot with 200kHz Input Frequency Bipolar Mode
where effective number bits resolution S/(N expressed maximum sampling rate 400kHz, LTC1400 maintains very good ENOBs Nyquist input frequency 200kHz (refer Figure
fSAMPLE 400kHz 100k INPUT FREQUENCY (Hz) NYQUIST FREQUENCY
EFFECTIVE NUMBER BITS
LTC1400
Figure Effective Bits Signal-to-Noise Distortion Input Frequency Bipolar Mode
Total Harmonic Distortion Total harmonic distortion (THD) ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency band between half sampling frequency. expressed
.Vn2
where amplitude fundamental frequency through amplitudes second through harmonics. input frequency shown Figure LTC1400 good distortion performance Nyquist frequency beyond.
-100 HARMONIC HARMONIC 100k INPUT FREQUENCY (Hz)
LTC1400
fSAMPLE 400kHz
Figure Distortion Input Frequency Bipolar Mode
SIGNAL/(NOISE DISTORTION) (dB)
Intermodulation Distortion input signal consists more than spectral component, transfer function nonlinearity produce intermodulation distortion (IMD) addition THD. change sinusoidal input caused presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products difference frequencies nfb, where etc. example, order terms include while order terms includes (2fa fb), (2fa fb), 2fb) 2fb). input sine waves equal magnitude, value decibels) order products expressed following formula.
IMD( 20log Amplitude Amplitude
LTC1400
APPLICATIONS INFORMATION
fSAMPLE 400kHz 99.512kHz 102.441kHz
AMPLITUDE (dB)
-100 -110 -120 FREQUENCY (kHz)
LTC1400
Figure Intermodulation Distortion Plot Bipolar Mode
Figure shows performance 100kHz input. Peak Harmonic Spurious Noise peak harmonic spurious noise largest spectral component excluding input signal This value expressed decibels relative value fullscale input signal. Full Power Full Linear Bandwidth full power bandwidth input frequency which amplitude reconstructed fundamental reduced full-scale input signal. full linear bandwidth input frequency which S/(N dropped 68dB effective bits). LTC1400 been designed optimize input bandwidth, allowing undersample input signals with frequencies above converter's Nyquist Frequency. noise floor stays very high frequencies; S/(N becomes dominated distortion frequencies beyond Nyquist. Driving Analog Input analog input LTC1400 easy drive. draws only small current spike while charging sampleand-hold capacitor conversion. During conversion, analog input draws only small leakage current. only requirement that amplifier driving analog input must settle after small current spike before next conversion starts. that settles
200ns small load current transient will allow maximum speed operation. slower used, more settling time provided increasing time between conversions. Suitable devices capable driving ADC's input include 1360 LT1363 amps. LTC1400 comes with built-in unipolar/bipolar detection circuit. potential forced below GND, internal circuitry will automatically switch bipolar mode. following list summary amps that suitable driving LTC1400, more detailed information available Linear Technology databooks LinearViewCD-ROM. 1215/LT1216: Dual quad 23MHz, 50V/µs single supply amps. Single ±15V supplies, 6.6mA specifications, 90ns settling 0.5LSB. LT1223: 100MHz video current feedback amplifier. ±15V supplies, supply current. distortion above 400kHz. noise. Good applications. LT1227: 140MHz video current feedback amplifier. ±15V supplies, 10mA supply current. Lowest distortion frequencies above 400kHz. noise. Best applications. LT1229/LT1230: Dual quad 100MHz current feedback amplifiers. ±15V supplies, supply current each amplifier. noise. Good specs. LT1360: 37MHz voltage feedback amplifier. ±15V supplies. 3.8mA supply current. Good specs. 70ns settling 0.5LSB. LT1363: 50MHz, 450V/µs amps. ±15V supplies. 6.3mA supply current. Good specs. 60ns settling 0.5LSB. LT1364/LT1365: Dual quad 50MHz, 450V/µs amps. ±15V supplies, 6.3mA supply current amplifier. 60ns settling 0.5LSB. Internal Reference LTC1400 on-chip, temperature compensated, curvature corrected, bandgap reference, which factory
LTC1400
APPLICATIONS INFORMATION
trimmed 2.42V. internally connected available provide current external load. minimum code transition noise, reference output should decoupled with capacitor filter wideband noise from reference (10µF tantalum parallel with 0.1µF ceramic). VREF driven with other means provide input span adjustment bipolar mode. VREF must driven least 2.45V prevent conflict with internal reference. reference should driven more than Figure shows 1306 driving reference pin. Figure shows typical reference, LT1019A-5 connected LTC1360. This will provide improved drift (equal maximum 5ppm/°C LT1019A-5) ±4.231V full scale. VREF forced lower than 2.42V, REFRDY serial data output will forced low.
INPUT RANGE ±0.846VREF(OUT)
OUTPUT CODE
LT1360
VREF(OUT) 2.45V 10µF
LTC1400 VREF
OUTPUT CODE
Figure Driving VREF with LT1360
INPUT RANGE ±4.231V ±0.846VREF)
LTC1400 VOUT 10µF
LTC1400
VREF
LT1019A-5
Figure Supplying Reference Voltage LTC1400 with LT1019A-5
UNIPOLAR BIPOLAR OPERATION ADJUSTMENT Figure shows ideal input/output characteristics LTC1400. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, 1.5LSB). output code natural binary with 1LSB 4.096/4096 1mV. Figure shows input/output transfer characteristics bipolar mode two's complement format.
111.111 111.110 111.101 111.100 1LSB 4.096 4096 4096
000.011 000.010 000.001 000.000
UNIPOLAR ZERO
INPUT VOLTAGE
1LSB
LTC1400
Figure LTC1400 Unipolar Transfer Characteristics
011.111 011.110 BIPOLAR ZERO
LTC1400
000.001 000.000 111.111 111.110
100.001 100.000 -FS/2 INPUT VOLTAGE FS/2 1LSB
LTC11400
Figure LTC1400 Bipolar Transfer Characteristics
Unipolar Offset Full-Scale Error Adjustments applications where absolute accuracy important, offset full-scale errors adjusted zero. Figure shows extra components required full-scale
LTC1400
APPLICATIONS INFORMATION
LTC1400 FULL-SCALE ADJUST
ADDITIONAL PINS OMITTED CLARITY ±20LSB TRIM RANGE
Figure 10a. LTC1400 Full-Scale Adjust Circuit
ANALOG INPUT 4.096V
100k LTC1400 4.3k FULL-SCALE ADJUST 100k OFFSET ADJUST
100k
Figure 10b. LTC1400 Offset Full-Scale Adjust Circuit
ANALOG INPUT ±2.048V
100k 4.3k FULL-SCALE ADJUST 100k LTC1400
100k
OFFSET ADJUST
LTC1400 F10c
Figure 10c. LTC1400 Bipolar Offset Full-Scale Adjust Circuit
error adjustment. Figure shows offset full-scale adjustment. Offset error must adjusted before fullscale error. Zero offset achieved applying 0.5mV (i.e., 0.5LSB) input adjusting offset trim until LTC1400 output code flickers between 0000 0000 0000 0000 0000 0001. zero full-scale error, apply analog input 4.0945V 1.5LSB last code transition) input adjust until LTC1400 output code flickers between 1111 1111 1110 1111 1111 1111. Bipolar Offset Full-Scale Error Adjustments Bipolar offset full-scale errors adjusted similar fashion unipolar case. Bipolar offset error adjustment achieved applying input voltage 0.5mV 0.5LSB) input Figure adjusting until output code flickers between 0000 0000 0000 1111 1111 1111. full-scale adjustment, input voltage 2.0465V 1.5LSBs) applied input adjusted until output code flickers between 0111 1111 1110 0111 1111 1111. BOARD LAYOUT BYPASSING obtain best performance from LTC1400, printed circuit board required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital track alongside analog signal track underneath ADC. analog input should screened GND. High quality tantalum ceramic bypass capacitors should used VREF pins shown Typical Application first page this data sheet. bipolar mode, 0.1µF ceramic provides adequate bypassing pin. optimum performance, 10µF surface mount capacitor with 0.1µF ceramic recommended VREF pins. capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. unipolar mode operation, should isolated from noise source before shorting pin.
LTC1400 F10a
LTC1400 F10b
LTC1400
APPLICATIONS INFORMATION
Input signal leads signal return leads from (Pin should kept short possible minimize noise coupling. applications where this possible, shielded cable between source recommended. Also, since potential difference grounds between signal source appears error voltage series with input signal, attention should paid reducing ground circuit impedance much possible.
ANALOG SUPPLY DIGITAL SUPPLY
LTC1400
DIGITAL CIRCUITRY
LTC1400
Figure Power Supply Connection
Figure shows recommended system ground connections. analog circuitry grounds should termi-
CONV
SLEEP
VREF
REFRDY
NOTE: SLEEP INTERNAL SIGNALS. REFRDY APPEARS DOUT WORD.
Figure Mode Sleep Mode Waveforms
nated LTC1400 pin. ground return from LTC1400 power supply should impedance noise free operation. Digital circuitry grounds must connected digital supply common. applications where data outputs control signals connected continuously active microprocessor bus, possible errors conversion results. These errors feedthrough from microprocessor successive approximation comparator. problem eliminated forcing microprocessor into Wait state during conversion using three-state buffers isolate data bus. Power-Down Mode Upon power-up, LTC1400 initialized active state ready conversion. However, chip easily placed into Sleep mode exercising right combination CONV signal. mode power except internal reference, which still active provides 2.42V output voltage other circuitry. this mode, draws only power instead 75mW (for minimum power, logic inputs must within 500mV supply rails). wake-up time from mode active mode
LTC1400
LTC1400
APPLICATIONS INFORMATION
350ns. Sleep mode, power consumption reduced minimum cutting supply internal circuitry including reference. Figure shows ways power down LTC1400. chip enter mode keeping signal pulsing CONV signal twice. Sleep mode operation, CONV signal should activated four times while kept low. LTC1400 returned active mode easily. rising edge will wake-up LTC1400. During transition from Sleep mode active mode, VREF voltage ramp-up time function loading conditions. With 10µF bypass capacitor, wake-up time from Sleep mode typically 4ms. REFRDY signal will activated once reference settled ready conversion. This REFRDY output DOUT before rest converted code.
CONV INTERNAL STATUS SAMPLE HOLD tACQ SAMPLE DOUT Hi-Z REFRDY tCONV tSAMPLE
LTC1400
Figure Digital Timing Diagram
Figure DOUT Delay
DIGITAL INTERFACE digital interface requires only three digital lines. CONV both inputs, DOUT output provides conversion result serial form. Figure shows digital timing diagram LTC1400 during conversion. CONV rising edge starts conversion. Once initiated, restarted until conversion completed. time from CONV signal rising edge less than digital output will delayed clock cycle. digital output data updated rising edge line. DOUT data should captured receiving system rising edge. Data remains valid minimum time after rising edge allow capture occur.
HOLD
Hi-Z
REFRDY
LTC1400
LTC1400
TYPICAL APPLICATIONS
Hardware Interface TMS320C50's Serial Port (Frame Sync Generated from TFSX)
TMS320C50 TCLKX TCLKR TFSX TFSR
10µF 0.1µF
Logic Analyzer Waveforms Show 3.2µs Throughput Rate (Input Voltage 3.046V, Output Code 1011 1110 0110 304610)
Data from LTC1400 Loaded into TMS320C50's TRCV Register
Data Stored TMS320C50's Memory Right Justified Format)
UNIPOLAR INPUT
CONV LTC1400 VREF DOUT
10µF 0.1µF
LTC1400 TA04a
LTC1400
TYPICAL APPLICATIONS
TMS320C50 Code Circuit
THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TMS320C50 FRAME SYNC PULSE GENERATED FROM TFSX *Initialization* .mmregs Initialized data memory zero 0F00h DATA0 .word DATA1 .word DATA2 .word DATA3 .word DATA4 .word DATA5 .word vector 080Ah rint RECEIVE xint TRANSMIT trnt TREC txnt TTRANX Setup reset vector 0A00h .entry START: Defines global symbolic names Initialize data zero Begin sample data location Location data sample data location Serial ports interrupts *Start Serial Communication* SACL TDXR Generate frame sync pulse SPLK #040h, Turn TRNT receiver interrupt CLRC Enable interrupt CLRC Unipolar input, right shift with sign extension *AR7 Load auxiliary register pointer with seven AR7, #0F00h Load auxiliary register seven with #0F00h begin address data storage WAIT: Wait receive interrupt SACL TDXR regenerate frame sync pulse WAIT main program *Receiver Interrupt Service Routine* TREC: LAMM TRCV Load data received from LTC1400 Shift right times #1FFFh, ANDed with #1FFFh converting data right justified format SACL Write data memory pointed increase memory address LACC #0F05h,0 Compare sample address #0F05h BCND END_TRCV, sample address exceeded jump END_TRCV SPLK #040h, Else Re-enable TRNT receive interrupt RETE Return main program enable interrupt *After Obtained Data from LTC1400, Program Jump END_TRCV* END_TRCV: SPLK #002h, Enable INT2 program halt CLRC INSUCCESS: SUCCESS *Fill Unused Interrupt with RETE, avoid program "lost"* TTRANX: RETE RECEIVE: RETE TRANSMIT: RETE INT2: halt Halts running
*TMS32C050 Initialization* SETC Temporarily disable interrupts data page pointer zero #0834h, PMST PMST status control register LACC SAMM CWSR software wait state SAMM PDWSR *Configure Serial Port* SPLK #0038h, TSPC Serial Port Stand Alone mode DLB=0 loop back FO=0 Bits FSM=1 Burst Mode MCM=1 CLKX generated internally TXM=1 output serial port into reset (XRST=RRST=0) SPLK #00F8h, TSPC Take Serial Port reset (XRST=RRST=1) SPLK #0FFFFh, Clear pending interrupts
LTC1400
TYPICAL APPLICATIONS
LTC1400 Interface ADSP2181's SPORT0 (Frame Sync Generated from RFS0)
ADSP2181 UNIPOLAR INPUT SCLKO RFSO
10µF 0.1µF
Logic Analyzer Waveforms Show 2.88µs Throughput Rate (Input Voltage 2.240V, Output Code 1000 1100 0000 224010)
Data Stored ADSP2181's Memory (Normal Mode, SLEN
CONV LTC1400 VREF DOUT
10µF 0.1µF
LTC1400 TA05a
Data from LTC1400 (Normal Mode)
LTC1400 TA05c
LTC1400 TA05d
LTC1400
TYPICAL APPLICATIONS
ADSP2181 Code Circuit
THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE ADSP-2181 FRAME SYNC PULSE GENERATED FROM RFS0 /*Section Initialization*/ .module/ram/abs adspltc; /*define program module*/ jump start; /*jump over interrupt vectors*/ nop; nop; nop; rti; rti; rti; rti; /*code vectors here upon IRQ2 int*/ rti; rti; rti; rti; /*code vectors here upon IRQL1 int*/ rti; rti; rti; rti; /*code vectors here upon IRQL0 int*/ rti; rti; rti; rti; /*code vectors here upon SPORT0 int*/ rx0; /*Section (0x2000) ax0; /*begin SPORT0 receive interrupt*/ rti; /*end SPORT0 receive interrupt*/ rti; rti; rti; rti; /*code vectors here upon /IRQE int*/ rti; rti; rti; rti; /*code vectors here upon BDMA interrupt*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 (IRQ1) int*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 (IRQ0) int*/ rti; rti; rti; rti; /*code vectors here upon TIMER int*/ rti; rti; rti; rti; /*code vectors here upon POWER DOWN int*/ /*Section Configure SPORT0*/ start: /*to configure SPORT0 control reg*/ /*SPORT0 address 0X3FF6*/ /*RFS used frame sync generation*/ /*RFS0 internal, use*/ /*bit Slen*/ 1111*/ 1110*/ 1101*/ /*bit data type right justified zero filled MSB*/ /*bit INVRFS /*bit INVTFS /*bit IRFS=1 receive internal frame sync*/ /*bit 9,10,11 (don't care)*/ /*bit TFSW=1 receive Normal mode*/ /*bit RTFS=1 receive framed mode*/ /*bit ISCLK internal /*bit multichannel mode 0x6B0D; /*normal mode, bit12=0*/ /*if alternate mode bit12=1, ax0=0x7F0E*/ (0x3FF6) =ax0; /*Section configure CLKDIV RFSDIV, setup interrupts*/ /*to configure CLKDIV reg*/ ax0= dm(0x3FF5) =ax0; /*set serial clock divide modulus SCLKDIV*/ /*the input clock frequency 16.67MHz*/ /*CLKOUT frequency 33MHz*/ /*SCLK= 1/2*CLKOUT*1/(SCLKDIV+1)*/ /*for SCLKDIV SCLK 33/6 5.5MHz*/ /*to Configure RFSDIV*/ /*set RFSDIV 15*/ /*=> frame sync pulse every SCLK*/ /*if frame sync pulse every SCLK, ax0=14*/ dm(0x3FF4) =ax0; /*to setup interrupt*/ ifc= 0x0066; /*clear extraneous SPORT interrupts*/ icntl= /*IRQXB level sensitivity*/ /*disable nesting interrupt*/ imask= 0x0020; /*bit timer /*bit SPORT1 IRQ0B /*bit SPORT1 IRQ1B /*bit BDMA /*bit IRQEB /*bit SPORT0 receive /*bit SPORT0 transmit /*bit IRQ2B /*enable SPORT0 receive interrupt*/ /*Section Configure System Control Register Start Communication*/ /*to configure system control reg*/ dm(0x3FFF); /*read system control reg*/ 0xFFF0; ay0; /*set wait state zero*/ 0x1000; ay0; /*bit12 enable SPORT0*/ dm(0x3FFF) /*frame sync pulse regenerated automatically*/ cntr 5000; waitloop until nop; nop; nop; nop; nop; nop; waitloop: nop; rts; .endmod;
LTC1400
TYPICAL APPLICATIONS
10µF 0.1µF ANALOG INPUT 4.096V)
2.42V REFERENCE OUTPUT
10µF 0.1µF
Quick Look Circuit Converting Data Parallel Format
CONV LTC1400 CONV DOUT SRCLR
3-WIRE SERIAL INTERFACE LINK
SRCK 74HC595 SRCLR
SRCK 74HC595
REFRDY
LTC1400 TA03
LTC1400
PACKAGE DESCRIPTION
Dimensions inches (millimeters) unless otherwise noted.
Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC 05-08-1610)
0.189 0.197* (4.801 5.004)
0.228 0.244 (5.791 6.197)
0.150 0.157** (3.810 3.988)
0.010 0.020 (0.254 0.508) 0.008 0.010 (0.203 0.254)
0.053 0.069 (1.346 1.752)
0.004 0.010 (0.101 0.254)
0.016 0.050 0.406 1.270 *DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
0.014 0.019 (0.355 0.483)
0.050 (1.270)
0695
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC1400
TYPICAL APPLICATIONS
LTC1400 Interface TMS320C50
TMS320C50 TCLKX TCLKR TFSX TFSR
10µF 0.1µF
10µF 0.1µF
RELATED PARTS
12-Bit Parallel Output ADCs
PART NUMBER LTC1272 LTC1273/LTC1275/LTC1276 LTC1274/LTC1277 LTC1278/LTC1279 LTC1282 LTC1410 SAMPLE RATE 250ksps 300ksps 100ksps 500/600ksps 140ksps 1.25Msps POWER DISSIPATION 75mW 75mW 10mW 75mW 12mW 150mW DESCRIPTION Single 7572 Upgrade With Clock Reference Power ADCs with Shutdown 70dB Nyquist, Power, Single with Clock Reference 71dB Nyquist, Differential Input
12-Bit Serial Output ADCs
PART NUMBER LTC1285/LTC1288 LTC1286/LTC1298 LTC1290 LTC1296 5/±5V 5/±5V SAMPLE RATE 7.5/6.6ksps 12.5/11.1ksps 50ksps 46.5ksps POWER DISSIPATION 0.48mW 1.25mV 30mW 30mW DESCRIPTION Input, Micropower, SO-8 Input, Micropower, SO-8 Input, Full-Duplex Serial Input, Half-Duplex Serial I/O, Power Shutdown Output
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417 (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 www.linear-tech.com
UNIPOLAR INPUT
CONV LTC1400 VREF DOUT
10µF 0.1µF
LTC1400 TA04a
LTC1400 Interface ADSP2181
UNIPOLAR INPUT ADSP2181 SCLKO RFSO
CONV LTC1400 VREF DOUT
10µF 0.1µF
LTC1400 TA05a
1400f LT/TP 0597 PRINTED
LINEAR TECHNOLOGY CORPORATION 1995

®1400 complete 400ksps, 12-bit converter which draws only 75mW from su

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