93-09-10 M.A. Frye 94-01-27 M.A. Frye 95-10-05 96-
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REVISIONS DESCRIPTION Redrawn with changes. Converted drawing part-one part number format. Corrected work packages. Redrawn with changes. Added devices Changes paragraph 4.2.1. Changes table table IIA. Changed lead thickness case outline Added case outlines Made format changes, editorial changes throughout. Changes accordance with 5962-R198-95. Changes accordance with 5962-R005-97. Updated drawing current requirements. Editorial changes throughout. Boilerplate update, part year review. DATE (YR-MO-DA) 92-11-16 APPROVED M.A. Frye
93-09-10
M.A. Frye
94-01-27
M.A. Frye
95-10-05 96-10-04 01-11-09 07-04-27
M.A. Frye Raymond Monnin Raymond Monnin Robert Heber
SHEET SHEET STATUS SHEETS PMIC
SHEET PREPARED Kenneth Rice
STANDARD MICROCIRCUIT DRAWING
THIS DRAWING AVAILABLE DEPARTMENTS AGENCIES DEPARTMENT DEFENSE
CHECKED Rajesh Pithadia
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil
APPROVED Mike Frye DRAWING APPROVAL DATE 91-11-08
MICROCIRCUITS, MEMORY, DIGITAL, CMOS 9000 GATE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON
SIZE SHEET CAGE CODE
AMSC
REVISION LEVEL
67268
5962-89823
DSCC FORM 2233
5962-E313-07
SCOPE Scope. This drawing documents product assurance class levels consisting high reliability (device classes space application (device class choice case outlines lead finishes available reflected Part Identifying Number (PIN). When available, choice Radiation Hardness Assurance (RHA) levels reflected PIN. PIN. shown following example:
5962
89823
Federal stock class designator
designator (see 1.2.1)
Device type (see 1.2.2)
Device class designator (see 1.2.3)
Case outline (see 1.2.4)
Lead finish (see 1.2.5)
Drawing number 1.2.1 designator. Device classes marked devices meet MIL-PRF-38535 specified levels marked with appropriate designator. Device class marked devices meet MIL-PRF-38535, appendix specified levels marked with appropriate designator. dash indicates non-RHA device. 1.2.2 Device type(s). device type(s) identify circuit function follows: Device type Generic number 3090-50 3090-70 3090-100 3090-125 Circuit function 9000 gate programmable array 9000 gate programmable array 9000 gate programmable array 9000 gate programmable array Toggle Speed
1.2.3 Device class designator. device class designator single letter identifying product assurance level follows: Device class Device requirements documentation Vendor self-certification requirements MIL-STD-883 compliant, nonJAN class level microcircuits accordance with MIL-PRF-38535, appendix Certification qualification MIL-PRF-38535
1.2.4 Case outline(s). case outline(s) designated MIL-STD-1835 follows: Outline letter Descriptive designator CMGA8-PN figure figure figure figure Terminals Package style grid array package Quad flat package Quad flat package Quad flat package Quad flat package
1.2.5 Lead finish. lead finish specified MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class
actual number pins used, maximum listed MIL-STD-1835
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Absolute maximum ratings. Supply voltage range ground potential (VCC) input voltage range. Voltage applied three-state output(VTS). Lead temperature (soldering, seconds) Thermal resistance, junction-to-case (JC): Case outline Case outlines Junction temperature (TJ). Storage temperature range
-0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +260°C MIL-STD-1835 20°C/W +150°C -65°C +150°
Recommended operating conditions. Case operating temperature Range(TC) -55°C +125°C Supply voltage relative ground(VCC) +4.5 minimum +5.5 maximum Ground voltage (GND) APPLICABLE DOCUMENTS Government specification, standards, handbooks. following specification, standards, handbooks form part this drawing extent specified herein. Unless otherwise specified, issues these documents those cited solicitation contract. DEPARTMENT DEFENSE SPECIFICATION MIL-PRF-38535 Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines.
DEPARTMENT DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 List Standard Microcircuit Drawings. Standard Microcircuit Drawings.
(Copies these documents available online http://assist.daps.dla.mil from Standardization Document Order Desk, Robbins Avenue, Building Philadelphia, 19111-5094.) Non-Government publications. following document(s) form part this document extent specified herein. Unless otherwise specified, issues documents issues documents cited solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 Latch-Up Test.
(Applications copies should addressed Electronics Industries Association, 2500 Wilson Boulevard, Arlington, 22201; http://www.jedec.org.) (Non-Government standards other publications normally available from organizations that prepare distribute documents. These documents also available through libraries other informational services.) Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. When thermal resistance this case specified MIL-STD-1835 that value shall supersede value indicated herein. Maximum junction temperature shall exceeded except allowable short duration burn-in screening conditions accordance with method 5004 MIL-STD-883. voltage values this drawing with respect VSS.
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Order precedence. event conflict between text this drawing references cited herein, text this drawing takes precedence. Nothing this document, however, supersedes applicable laws regulations unless specific exemption been obtained. REQUIREMENTS Item requirements. individual item requirements device classes shall accordance with MIL-PRF-38535 specified herein modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. individual item requirements device class shall accordance with MIL-PRF-38535, appendix non-JAN class level devices specified herein. Design, construction, physical dimensions. design, construction, physical dimensions shall specified MIL-PRF-38535 herein device classes MIL-PRF-38535, appendix herein device class 3.2.1 Case outlines. case outlines shall accordance with 1.2.4 herein figure 3.2.2 Terminal connections. terminal connections shall specified figure 3.2.3 Logic block diagram. logic block diagram shall specified figure Electrical performance characteristics postirradiation parameter limits. Unless otherwise specified herein, electrical performance characteristics postirradiation parameter limits specified table shall apply over full case operating temperature range. Electrical test requirements. electrical test requirements shall subgroups specified table IIA. electrical tests each subgroup defined table Marking. part shall marked with listed herein. addition, manufacturer's also marked. packages where marking entire number feasible space limitations, manufacturer option marking "5962-" device. product using this option, designator shall still marked. Marking device classes shall accordance with MIL-PRF-38535. Marking device class shall accordance with MIL-PRF-38535, appendix 3.5.1 Certification/compliance mark. certification mark device classes shall "QML" required MIL-PRF-38535. compliance mark device class shall required MIL-PRF-38535, appendix Certificate compliance. device classes certificate compliance shall required from QML-38535 listed manufacturer order supply requirements this drawing (see 6.6.1 herein). device class certificate compliance shall required from manufacturer order listed approved source supply MIL-HDBK-103 (see 6.6.2 herein). certificate compliance submitted DSCC-VA prior listing approved source supply this drawing shall affirm that manufacturer's product meets, device classes requirements MIL-PRF-38535 herein device class requirements MIL-PRF-38535, appendix herein. Certificate conformance. certificate conformance required device classes MIL-PRF-38535 device class MIL-PRF-38535, appendix shall provided with each microcircuits delivered this drawing. Notification change device class device class notification DSCC-VA change product (see herein) involving devices acquired this drawing required change that affects this drawing. Verification review device class device class DSCC, DSCC's agent, acquiring activity retain option review manufacturer's facility applicable required documentation. Offshore documentation shall made available onshore option reviewer. 3.10 Microcircuit group assignment device class Device class devices covered this drawing shall microcircuit group number (see MIL-PRF-38535, appendix 3.11 Operational notes. Additional information shall provided device manufacturer (see herein).
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VERIFICATION Sampling inspection. device classes sampling inspection procedures shall accordance with MIL-PRF-38535 modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. device class sampling inspection procedures shall accordance with MIL-PRF-38535, appendix Screening. device classes screening shall accordance with MIL-PRF-38535, shall conducted devices prior qualification technology conformance inspection. device class screening shall accordance with method 5004 MIL-STD-883, shall conducted devices prior quality conformance inspection. 4.2.1 Additional criteria device class Burn-in test, method 1015 MIL-STD-883. Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1015. +125°C, minimum. Interim final electrical test parameters shall specified table herein. 4.2.2 Additional criteria device classes burn-in test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. burn-in test circuit shall maintained under document revision level control device manufacturer's Technology Review Board (TRB) accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1015 MIL-STD883. Interim final electrical test parameters shall specified table herein. Additional screening device class beyond requirements device class shall specified MIL-PRF-38535, appendix Qualification inspection device classes Qualification inspection device classes shall accordance with MIL-PRF-38535. Inspections performed shall those specified MIL-PRF-38535 herein groups inspections (see 4.4.1 through 4.4.4). Conformance inspection. Technology conformance inspection classes shall accordance with MIL-PRF-38535 including groups inspections specified herein. Quality conformance inspection device class shall accordance with MIL-PRF-38535, appendix specified herein. Inspections performed device class shall those specified method 5005 MIL-STD-883 herein groups inspections (see 4.4.1 through 4.4.4). 4.4.1 Group inspection. Tests shall specified table herein. Subgroups table method 5005 MIL-STD-883 shall omitted. Subgroups tests shall consist verifying functionality device. (latch-up) tests shall measured only initial qualification after design process changes which affect performance device. device class procedures circuits shall maintained under document revision level control manufacturer shall made available preparing activity acquiring activity upon request. device classes procedures circuits shall under control device manufacturer's accordance with MIL-PRF-38535 shall made available preparing activity acquiring activity upon request. Testing shall pins, five devices with zero failures. Latch-up test shall considered destructive. Information contained JESD used reference. Subgroup (CIN COUT measurements) shall measured only initial qualification after process design changes which affect input output capacitance. Capacitance shall measured between designated terminal frequency MHz. Sample size devices with failures, input output terminals tested.
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TABLE Electrical performance characteristics. Test Symbol Conditions +125 unless otherwise specified 0.8V -4.0 3.85 -4.0 4.0V 3.85 Group Subgroups Device type Unit Limits
High Level output voltage
level output voltage
Operating power supply current
Quiescent power supply current Quiescent power supply current Power-down supply current Input leakage current Output leakage current Horizontal long line, pull-up current High level input voltage level input voltage High level input voltage level input voltage Power down voltage footnotes table.
ICCO ICCO ICCPD IRLL VIHT VILT VIHC VILC
CMOS inputs, inputs, inputs inputs CMOS inputs CMOS inputs
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions +125 unless otherwise specified 4.4.1e 4.4.1e 4.4.1e 4.4.1c Measured columns Group Subgroups Device type Unit Limits
Input capacitance except XTL1 XTL2 Input capacitance XTL1 XTL2 Output capacitance Functional test Interconnect tPID 20(tILO)
COUT
tCKO tICK tCKI interconnect
Tested CLB's
tCKO tQLO tILO tDICK interconnect tILO tECCK interconnect
Tested CLB's
Tested CLB's
tOKPO tOPS tOPF tPICK
Tested CLB's
Interconnect tCKO tQLO tPUS tICK Interconnect tCKO tQLO tPUS tICK
long line pull-up
Other long line pull-up
footnotes table
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions +125 unless otherwise specified pull-up, lower long lines Group Subgroups Device type Unit Limits
Interconnect tCKO tQLO tICK Interconnect tCKO tQLO tICK Logic input output (combinational)
pull-up, upper long lines
tILO
figures applicable
Reset input output
tRIO
Reset direct width
tRPW
Master reset output
tMRQ
clock input output
tCKO
Clock outputs when return through function generators drive clock logic-input setup
tQLO
tICK
footnotes table
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions +125 unless otherwise specified figures applicable Group Subgroups Device type 10.0 Unit Limits
clock logic-input hold Logic input setup clock
tCKI tDICK
Logic input hold from clock
tCKDI
Logic input setup enable clock
tECCK
Logic input hold enable clock Clock (high)
tCKEC
Clock (low)
(package pin) input direct
tPID
Fast (CMOS only) input through clock buffer clock input clock input (FF)
tPGC
tIKRI
clock pad-input setup
tPICK
footnotes table
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions +125 unless otherwise specified figures applicable Group Subgroups Device type Unit Limits
clock pad-input hold clock (fast)
tIKPI tOKPO
clock pad-output setup
tOOK
clock pad-output hold clock (high)
tOKO tIOH
clock (low)
tIOL
Output (enabled fast)
tOPF
Output (enabled slow)
tOPS
Three-state begin high impedance (fast)
tTSHZ
Three-state high impedance (fast)
tTSON
Master RESET input
tRRI
footnotes table
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions +125 unless otherwise specified figures applicable Group Subgroups Device type Limits Unit
Master RESET output (FF)
tRPO
Bidirectional buffer delay
tBIDI
TBUF data input output
TBUF three-state output active valid (single pull-up) double pull-up TBUF three-state output inactive (single pull-up) TBUF three-state output inactive (pair pull-ups)
tPUS
tPUF
Tested initially after design process change that affect this parameter guaranteed limits specified table with following conditions: Global clock 16MHz device devices outputs outputs Alternate clock configurable logic blocks (CLB) CLBs horizontal long lines vertical long lines inputs inputs Excessive supply current occur result internal contention during initial phase reconfiguration following short interruption VCC. avoid this excessive current, monitor dropping immediately initiate reconfiguration, hold RESET active. This clears internal configuration register less that millisecond, avoids later contentions. PWRDWN transitions must occur during operational levels. Parameter directly tested. Devices first percent functionally tested. Benchmark patterns (tB1-9) then used determine compliance this parameter. Characterization data taken initially after design process change which affect this parameter. Minimum CLOCK widths auxiliary buffer 1.25 times tCL. These parameters clock pulses internal chip. Externally applied clock, increases value percent.
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Case
FIGURE Case outline.
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Case
FIGURE Case outline Continued.
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Case
FIGURE Case outline Continued.
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Case
Symbol
Inches .125 .145 .100 .120 .060 .070 1.510 1.530 1.060 1.100 1.000 Ref. 1.510 1.530 1.060 1.100 1.000 Ref.
Millimeters 3.18 2.54 1.52 38.35 26.92 25.40 Ref. 38.35 26.92 25.40 Ref. 38.86 27.94 3.68 3.05 1.78 38.86 27.94
Notes
NOTES government preferred system measurement metric system. However, this item originally designed using inch-pound units measurement. event conflict between metric inchpound units, inch-pound units shall take precedence. Datum plane located underside leads, where leads exit package body. Datum determined where center leads exit package body datum -H-. These dimensions determined datum plane -H-. Dimensions define maximum ceramic body dimensions including glass protrusion mismatch ceramic body bottom. identifier location. middle side with center justified. Identifier mark notch, dot, triangle. Packages shipped with unformed leads side mark location, product mark located nonlid side package; i.e., side facing down. When mounted this position, clockwise.
FIGURE Case outline Continued.
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Case
FIGURE Case outline Continued.
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Case
FIGURE Case outline Continued.
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Case
FIGURE Case outline Continued.
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Case
Symbol
Inches .125 .145 .100 .120 .060 .070 1.510 1.530 1.060 1.100 1.000 Ref. 1.510 1.530 1.060 1.100 1.000 Ref.
Millimeters 3.18 3.68 2.54 3.05 1.52 1.78 38.35 38.86 26.92 27.94 25.40 Ref. 38.35 38.86 26.92 27.94 25.40 Ref.
Notes
NOTES government preferred system measurement metric system. However, this item originally designed using inch-pound units measurement. event conflict between metric inch-pound units, inch-pound units shall take precedence. Datum plane located underside leads, where leads exit package body. Datum determined where center leads exit package body datum -H-. These dimensions determined datum plane -H-. Dimensions define maximum ceramic body dimensions including glass protrusion mismatch ceramic body bottom. identifier location. middle side with center justified. Identifier mark notch, dot, triangle. Packages shipped with unformed leads side mark location, product mark located side package; i.e., side facing When mounted this position, counterclockwise.
FIGURE Case outline Continued.
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Cases (See note
FIGURE Case outline Continued.
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Cases (See note
NOTES: Dimensions inches. Metric dimensions reference only. Packages shipped flat depicted Lead dimensions call includes lead finish. leads this package style shall protected from mechanical distortion damage such that dimensions pertaining relative lead/body "true positions" lead "coplanarity" always maintained until next higher level package attachment process complete. Package lead protection mechanisms (tie bars) shown drawing reference only. When microcircuit devices contained this package style shipped Government equipment, shipped directly Government spare parts mechanical qualification samples, lead "true position" "coplanarity" protection shall place. Case represents marking device nonlid side device, i.e., side facing down. When mounted this position, clockwise. Case represents marking device side device i.e., side facing When mounted this position, counterclockwise.
FIGURE Case outline Continued.
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Cases
Inches .0010 .001 .002 .004 .005 .008 .010 .012 .0175 .018 .020 .021 .025 .030 .040
0.025 0.03 0.05 0.10 0.13 0.20 0.25 0.30 0.445 0.46 0.51 0.53 0.64 0.76 1.02
Inches .050 .060 .080 .086 .095 .100 .115 .160 .200 .645 1.000 1.130 1.290 1.500 2.300 2.500
1.27 1.52 2.03 2.18 2.41 2.54 2.92 4.06 5.08 16.38 25.50 28.70 32.77 38.10 58.42 63.50
NOTE: Metric equivalents reference only.
FIGURE Case outline Continued.
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Case outline Device type Terminal number Terminal symbol PWRDN M1-RDATA M0-RTRIG Device type Terminal number Terminal symbol A8-I/O A9-I/O M2-I/O A11-I/O TCLKIN-I/O Device type Terminal number Terminal symbol LDC-I/O A7-I/O A10-I/O HDC-I/O A12-I/O A6-I/O A13-I/O INIT-I/O
connect
FIGURE Terminal connections.
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Case outline Continued.
Device type Terminal number
Terminal symbol A5-I/O A14-I/O A4-I/O A15-I/O A1-CS2-I/O A3-I/O DOUT-I/O
Device type Terminal number
Terminal symbol D7-I/O A2-I/O AO-WS-I/O RDY/BUSY-RCLK-I/O D3-I/O D6-I/O XTAL2(IN)-I/O
Device type Terminal number
Terminal symbol CCLK D0-DIN-I/O D1-I/O D2-I/O CS1-I/O D4-I/O CS0-I/O DONE-PG RESET D5-I/O XTALK1(OUT)BCLKIN-I/O
connect
FIGURE Terminal connections Continued.
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Case outlines Device type Terminal number
Device type Terminal number
Terminal symbol
Device type Terminal number
Terminal symbol M1-RDATA M0-RTRIG M2-I/O HDC-I/O LDC-I/O INIT-I/O
Terminal symbol A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O PWRDWN TCLKIN-I/O
FIGURE Terminal connections Continued.
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Case outlines Continued.
Device type Terminal number
Terminal symbol XTAL2(IN)-I/O RESET DONE-PG D7-I/O XTAL1(OUT)BCLKIN-I/O D6-I/O
Device type Terminal number
Terminal symbol D5-I/O CSO-I/O D4-I/O D3-I/O CS1-I/O D2-I/O D1-I/O RDY/BUSY-RCLK-I/O
Device type Terminal number
Terminal symbol D0-DIN-I/O DOUT-I/O CCLK A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A15-I/O A4-I/O A14-I/O A5-I/O
FIGURE Terminal connections Continued.
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CONFIGURABLE LOGIC BLOCK (CLB)
NOTE:
Each configurable logic block includes combinatorial logic section, flip-flops, program memory controlled multiplexer selection function. has: Five logic variable inputs: direct data input: enable clock: clock (invertible): asynchronous reset: outputs:
FIGURE Logic block diagram.
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BLOCK (10B)
NOTE:
input/output block includes input output storage elements options selected configuration memory cells. choice clocks available each edge. polarity each clock line (not each flip-flop latch) programmable. clock line that triggers flipflop rising edge active latch enable (latch transparent) signal vice versa. Passive pull-up only enable inputs, outputs. user inputs programmed CMOS thresholds.
FIGURE Logic block diagram Continued.
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NOTE:
timings except tTSHZ tTSON measured levels with minimum output load. input signals, rise fall times less than with amplitude high amplitude
FIGURE Timing diagrams switching characteristics.
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FIGURE Timing diagrams switching characteristics Continued.
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NOTE: timings except tTSHZ tTSON measured with minimum load output. input signals, rise fall times 6ns, amplitude high tTSHZ determined when output shifts percent output voltage swing) from level level. figure circuit herein circuit used. tTSON measured level with three-state active high, three-state active low. figure circuit herein circuit used.
FIGURE Timing diagrams switching characteristics Continued.
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FIGURE Load circuit.
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4.4.2 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.2.1 Additional criteria device class Steady-state life test conditions, method 1005 MIL-STD-883: Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1005 MILSTD-883. +125°C, minimum. Test duration: 1,000 hours, except permitted method 1005 MIL-STD-883.
4.4.2.2 Additional criteria device classes steady-state life test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. test circuit shall maintained under document revision level control device manufacturer's accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1005 MILSTD-883. TABLE IIA. Electrical test requirements. Line Test requirements Subgroups accordance with MIL-STD-883, method 5005, table Device class Interim electrical parameters (see 4.2) Static burn-in (method 1015) Same line Dynamic burn-in (method 1015) Final electrical parameters Group test requirements Group end-point electrical parameters Group end-point electrical parameters Group end-point electrical parameters Subgroups accordance with MIL-PRF-38535, table III) Device class Required Device class Required required 4**,
Required
required 10,11 4**,
required 4**,
Blank spaces indicate tests applicable. subgroups combined when using high-speed testers. Subgroups functional tests shall verify truth table. indicates applies subgroup 4.4.1e. indicates delta limit (see table IIB) shall required where specified, delta values shall computed with reference previous interim electrical parameters (see line 4.4.1d.
STANDARD MICROCIRCUIT DRAWING
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TABLE IIB. Delta limits +25°C. Parameter ICCO standby IIL, Device types
above parameter shall recorded before after required burn-in life tests determine delta
4.4.3 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.4 Group inspection. Group inspection required only parts intended marked radiation hardness assured (see herein). End-point electrical parameters shall specified table herein. device classes devices test vehicle shall subjected radiation hardness assured tests specified MIL-PRF-38535 level being tested. device class devices shall subjected radiation hardness assured tests specified MIL-PRF-38535, appendix level being tested. device classes must meet postirradiation end-point electrical parameter limits defined table +25°C ±5°C, after exposure, subgroups specified table herein.
Delta measurements device class Delta measurements, specified table IIA, shall made recorded before after required burn-in screens steady-state life tests determine delta compliance. electrical parameters measured, with associated delta limits listed table IIB. device manufacturer may, option, either perform delta measurements within hours after burn-in perform final electrical parameter tests, subgroups PACKAGING Packaging requirements. requirements packaging shall accordance with MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class NOTES Intended use. Microcircuits conforming this drawing intended Government microcircuit applications (original equipment), design applications, logistics purposes. 6.1.1 Replaceability. Microcircuits covered this drawing will replace same generic device covered contractor prepared specification drawing. 6.1.2 Substitutability. Device class devices will replace device class devices. Configuration control SMD's. proposed changes existing SMD's will coordinated with users record individual documents. This coordination will accomplished using Form 1692, Engineering Change Proposal. Record users. Military industrial users should inform Defense Supply Center Columbus (DSCC) when system application requires configuration control which SMD's applicable that system. DSCC will maintain record users this list will used coordination distribution changes drawings. Users drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. Comments. Comments this drawing should directed DSCC-VA Columbus, Ohio 43218-3990, telephone (614) 692-0547.
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Symbols, definitions, functional descriptions. PWRDWN POWER-DOWN MODE RTRIG READ TRIGGER MODE RDATA READ DATA MODE HDC. HIGH DURING CONFIGURATION DURING CONFIGURATION RESET RESET DONE DONE PROGRAM BCLKIN BCLKIN XTL1. EXTERNAL CRYSTAL XTL2. EXTERNAL CRYSTAL CCLK. CONFIGURATION CLOCK DOUT DATA DATA CHIP SELECT, WRITE CHIP SELECT, WRITE CHIP SELECT, WRITE CHIP SELECT, WRITE RCLK. READ CLOCK RDY/BUSY During peripheral parallel mode configuration, this indicates when chip ready another byte data written into After configuration complete, this becomes user programmed pin. TCLKIN. TCLKIN INIT INIT D0-D7 DATA A0-A15 ADDRESS INPUT/OUTPUT(DEDICATED) +5.0 SUPPLY VOLTAGE GROUND Additional operating data. Power delay cycles from non-master mode. This provides wait time. Power delay cycles master mode. This provides wait time. Clear cycles cycles take long During normal power must rise from minimum less than this does occur, configuration must delayed using RESET. Sources supply. 6.7.1 Sources supply device classes Sources supply device classes listed QML-38535. vendors listed QML-38535 have submitted certificate compliance (see herein) DSCC-VA have agreed this drawing. 6.7.2 Approved sources supply device class Approved sources supply class listed MIL-HDBK-103. vendors listed MIL-HDBK-103 have agreed this drawing certificate compliance (see herein) been submitted accepted DSCC-VA.
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APPENDIX SCOPE 10.1 Scope. This appendix contains substitution information necessary support addition device class designator that occurred revision dated 92-11-16. 5962-89823MXX supersedes 5962-89823XX. designs, after 92-11-16 shall used lieu PIN. existing designs prior 92-11-16 used lieu PIN. This appendix mandatory part specification. information contained herein intended compliance. substitution data shall follows. APPLICABLE DOCUMENTS This section applicable this appendix. SUBSTITUTION DATA 5962-8982301MXX 5962-8982301MYX 5962-8982301MZX 5962-8982301MUX 5962-8982301MTX 5962-8982302MXX 5962-8982302MYX 5962-8982302MZX 5962-8982302MUX 5962-8982302MTX 5962-8982303MXX 5962-8982303MYX 5962-8982303MZX 5962-8982303MUX 5962-8982303MTX 5962-8982304MXX 5962-8982304MYX 5962-8982304MZX 5962-8982304MUX 5962-8982304MTX 5962-8982301XX 5962-8982301YX 5962-8982301ZX originally available originally available 5962-8982302XX 5962-8982302YX 5962-8982302ZX originally available originally available originally available originally available originally available originally available originally available originally available originally available originally available originally available originally available
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
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STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 07-04-27 Approved sources supply 5962-89823 listed below immediate acquisition information only shall added MIL-HDBK-103 QML-38535 during next revision. MIL-HDBK-103 QML-38535 will revised include addition deletion sources. vendors listed below have agreed this drawing certificate compliance been submitted accepted DSCC-VA. This information bulletin superseded next dated revision MIL-HDBK-103 QML-38535. DSCC maintains online database current sources supply
Standard microcircuit drawing 5962-8982301MXC 5962-8982301MYA 5962-8982301MZC 5962-8982301MUA 5962-8982301MTC 5962-8982301QXA 5962-8982301QZA 5962-8982302MXC 5962-8982302MYA 5962-8982302MZC 5962-8982302MUA 5962-8982302MTC 5962-8982302QXA 5962-8982302QZA 5962-8982303MXC 5962-8982303MYA 5962-8982303MZC 5962-8982303MUA 5962-8982303MTC 5962-8982303QXA 5962-8982303QZA 5962-8982304QXA 5962-8982304QZA
Vendor CAGE number 68994 68994 68994
Vendor similar XC3090-50PG175B XC3090-50CQ164B XC3090-50CB164B XC3090-50CQ164B XC3090-50CB164B ATT3090-50R175MQ ATT3090-50N164MQ XC3090-70PG175B XC3090-70CQ164B XC3090-70CB164B XC3090-70CQ164B XC3090-70CB164B ATT3090-70R175MQ ATT3090-70N164MQ XC3090-100PG175B XC3090-100CQ164B XC3090-100CB164B XC3090-100CQ164B XC3090-100CB164B ATT3090-100R175MQ ATT3090-100N164MQ ATT3090-125R175MQ ATT3090-125N164MQ
lead finish shown each representing hermetic package most readily available from manufacturer listed that part. desired lead finish listed contact vendor determine availability. Caution. this number item acquisition. Items acquired this number satisfy performance requirements this drawing. available from approved source supply.
Vendor CAGE number 68994
Vendor name address Xilinx, Incorporated 2100 Logic Drive Jose, 95124
information contained herein disseminated convenience only Government assumes liability whatsoever inaccuracies information bulletin.
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