Features High Capacity Single-Chip ASIC Alternative 3,000 54,000
|
|
|
Top Searches for this datasheet
40MX 42MX FPGA Families
Features High Capacity
Single-Chip ASIC Alternative 3,000 54,000 System Gates kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry User-Programmable Pins
HiRel Features
Commercial, Industrial, Automotive, Military Temperature Plastic Packages Commercial, Military Temperature, MIL-STD-883 Ceramic Packages Certification Ceramic Devices Available DSCC
Ease Integration
Mixed-Voltage Operation (5.0V 3.3V core I/Os), with PCI-Compliant I/Os 100% Resource Utilization 100% Locking Deterministic, User-Controllable Timing Unique In-System Diagnostic Verification Capability with Silicon Explorer Power Consumption IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
High Performance
Clock-to-Out Performance Dual-Port SRAM Access FIFOs 35-Bit Address Decode
Product Profile
Device Capacity System Gates SRAM Bits Logic Modules Sequential Combinatorial Decode Clock-to-Out SRAM Modules (64x4 32x8) Dedicated Flip-Flops Maximum Flip-Flops Clocks User (maximum) Boundary Scan Test (BST) Packages count) PLCC PQFP VQFP TQFP CQFP PBGA A40MX02 3,000 A40MX04 6,000 A42MX09 14,000 100, A42MX16 24,000 100, 160, A42MX24 36,000 1,410 160, A42MX36 54,000 2,560 1,230 1,184 1,230 1,822 208, 208,
January 2004 2004 Actel Corporation
Actel website (www.actel.com) latest version this datasheet.
40MX 42MX FPGA Families
Ordering Information
A42MX16
Application (Temperature Range) Blank Commercial +70°C) Industrial (-40 +85°C) Military (-55 +125°C) MIL-STD-883 Automotive (-40 +125°C) Package Lead Count Package Type Plastic Leaded Chip Carrier Plastic Quad Flat Pack Thin (1.4 Quad Flat Pack Very Thin (1.0 Quad Flat Pack Plastic Ball Grid Array Ceramic Quad Flat Pack Speed Grade Blank Standard Speed Approximately Faster than Standard Approximately Faster than Standard Approximately Faster than Standard Approximately Slower than Standard Part Number A40MX02 3,000 System Gates A40MX04 6,000 System Gates A42MX09 14,000 System Gates A42MX16 24,000 System Gates A42MX24 36,000 System Gates A42MX36 54,000 System Gates
Plastic Device Resources
User I/Os Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 PLCC 44-Pin PLCC 68-Pin PLCC 84-Pin PQFP PQFP PQFP PQFP 100-Pin 160-Pin 208-Pin 240-Pin VQFP 80-Pin VQFP TQFP PBGA 100-Pin 176-Pin 272-Pin
Note: Package Definitions PLCC Plastic Leaded Chip Carrier, PQFP Plastic Quad Flat Pack, TQFP Thin Quad Flat Pack, VQFP Very Thin Quad Flat Pack, PBGA Plastic Ball Grid Array
40MX 42MX FPGA Families
Ceramic Device Resources
User I/Os Device A42MX36 Note: Package Definitions CQFP 208-Pin CQFP 256-Pin
CQFP Ceramic Quad Flat Pack
Temperature Grade Offerings
Package PLCC PLCC PLCC PQFP PQFP PQFP PQFP VQFP VQFP TQFP PBGA CQFP CQFP Note: Commercial Industrial Automotive Military MIL-STD-883 Class A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
Speed Grade Offerings
Note: Refer 40MX 42MX Automotive Family FPGAs datasheet details automotive-grade offerings.
Contact your local Actel representative device availability.
40MX 42MX FPGA Families
Table Contents
40MX 42MX FPGA Families
General Description Architectural Overview Other Architectural Features Power Dissipation Development Tool Support 1-13 Related Documents 1-13 5.0V Operating Conditions 1-14 Electrical Specifications 1-15 3.3V Operating Conditions 1-16 3.3V LVTTL Electrical Specifications 1-17 Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) 1-18 Mixed 5.0V/3.3V Electrical Specifications 1-18 Output Drive Characteristics 5.0V Signaling 1-19 Output Drive Characteristics 3.3V Signaling 1-20 Junction Temperature (TJ) 1-22 Package Thermal Characteristics 1-22 Timing Models 1-23 Parameter Measurement 1-25 Sequential Module Timing Characteristics 1-26 Sequential Timing Characteristics 1-27 Decode Module Timing 1-28 SRAM Timing Characteristics 1-28 Dual-Port SRAM Timing Waveforms 1-28 Predictable Performance: Tight Delay Distributions 1-30 Timing Characteristics 1-30 Temperature Voltage Derating Factors 1-31 System Timing Specification 1-35 Models 1-35 Timing Characteristics 1-36 Descriptions 1-77
Package Assignments
44-Pin PLCC 68-Pin PLCC 84-Pin PLCC
40MX 42MX FPGA Families
Table Contents
100-Pin PQFP Package 160-Pin PQFP Package 208-Pin PQFP Package 2-13 240-Pin PQFP Package 2-17 80-Pin VQFP 2-20 100-Pin VQFP Package 2-22 176-Pin TQFP Package 2-24 208-Pin CQFP 2-28 256-Pin CQFP 2-31 272-Pin Package 2-34
Datasheet Information
List Changes Datasheet Categories
40MX 42MX FPGA Families
40MX 42MX FPGA Families
General Description
Actel's 40MX 42MX families offer cost-effective design solution devices single-chip solutions provide high performance while shortening system design development cycle. devices integrate consolidate logic implemented multiple PALs, CPLDs, FPGAs. Example applications include high-speed controllers address decoding, peripheral interfaces, DSP, coprocessor functions. device architecture based Actel's patented antifuse technology implemented 0.45µm triplemetal CMOS process. With capacities ranging from 3,000 54,000 system gates, devices provide performance MHz, live power-up have one-fifth standby power consumption comparable FPGAs. Actel's FPGAs provide user I/Os available wide variety packages speed grades. Actel's A42MX24 A42MX36 devices also feature MultiPlex I/Os, which support mixed-voltage systems, enable programmable PCI, deliver high-performance operation both 5.0V 3.3V, provide lowpower mode. devices fully compliant with Local Specification (version 2.1). They deliver on-chip operation clock-to-output performance. 42MX24 42MX36 devices include system-level features such IEEE Standard 1149.1 (JTAG) Boundary Scan Testing fast wide-decode modules. addition, A42MX36 device offers dual-port SRAM implementing fast FIFOs, LIFOs, temporary data storage. storage elements efficiently address applications requiring wide datapath manipulation perform transformation functions such those required telecommunications, networking, DSP. devices fully tested over automotive military temperature ranges. addition, largest member family, A42MX36, available both CQ208 CQ256 ceramic packages screened MILSTD-883 levels. easy prototyping conversion from plastic ceramic, CQ208 PQ208 devices pincompatible.
Architectural Overview
devices composed fine-grained building blocks that enable fast, efficient logic designs. devices within these families composed logic modules, modules, routing resources clock networks, which building blocks fast logic designs. addition, A42MX36 device contains embedded dual-port SRAM modules, which optimized high-speed datapath functions such FIFOs, LIFOs scratchpad memory. A42MX24 A42MX36 also contain widedecode modules.
Logic Modules
40MX logic module eight-input, one-output logic circuit designed implement wide range logic functions with efficient interconnect routing resources (Figure 1-1). logic module implement four basic logic functions (NAND, AND, NOR) gates two, three, four inputs. logic module also implement variety D-latches, exclusivity functions, AND-ORs OR-ANDs. dedicated hard-wired latches flip-flops required array; latches flipflops constructed from logic modules whenever required application.
Figure 40MX Logic Module
40MX 42MX FPGA Families
42MX devices contain three types logic modules: combinatorial (C-modules), sequential (S-modules) decode (D-modules). Figure illustrates combinatorial logic module. S-module, shown Figure 1-3, implements same combinatorial logic function C-module while adding sequential element. sequential element configured either D-flip-flop transparent latch. S-module register bypassed that implements purely combinatorial logic.
Figure 42MX C-Module Implementation
GATE
7-Input Function Plus D-Type Flip-Flop with Clear
7-Input Function Plus Latch
GATE
4-Input Function Plus Latch with Clear
8-Input Function (Same C-Module)
Figure 42MX S-Module Implementation
40MX 42MX FPGA Families
A42MX24 A42MX36 devices contain D-modules, which arranged around periphery device. D-modules contain wide-decode circuitry, providing fast, wide-input function similar that found CPLD architectures (Figure 1-4). D-module allows A42MX24 A42MX36 devices perform widedecode functions speeds comparable CPLDs PALs. output D-module programmable inverter active HIGH assertion. D-module output hardwired output pin, also back into array incorporated into other logic.
highest order address bits (RDAD5 WRAD5) used. read write ports SRAM block contain independent clocks (RCLK WCLK) with programmable polarities offering active HIGH implementation. SRAM block contains eight data inputs (WD[7:0]), eight outputs (RD[7:0]), which connected segmented vertical routing tracks. A42MX36 dual-port SRAM blocks provide optimal solution high-speed buffered applications requiring FIFO LIFO queues. ACTgen Macro Builder within Actel's Designer software provides capability quickly design memory functions with SRAM blocks. Unused SRAM blocks used implement registers other user logic within design.
Inputs Hard-Wire Programmable Inverter Feedback Array
Figure A42MX24 A42MX36 D-Module Implementation
Dual-Port SRAM Modules
A42MX36 device contains dual-port SRAM modules that have been optimized synchronous asynchronous applications. SRAM modules arranged 256-bit blocks that configured 32x8 64x4. SRAM modules cascaded together form memory spaces user-definable width depth. block diagram A42MX36 dual-port SRAM block shown Figure 1-5. A42MX36 SRAM modules true dual-port structures containing independent read write ports. Each SRAM module contains bits read write addressing (RDAD[5:0] WRAD[5:0], respectively) 64x4-bit blocks. When configured byte mode,
WD[7:0]
Latches [7:0]
WRAD[5:0]
[5:0] Latches
Write Port Logic
SRAM Module (256 Bits)
[5:0] Read Port Logic
Latches Read Logic
RDAD[5:0]
RCLK
MODE BLKEN WCLK
Write Logic
RD[7:0]
Routing Tracks
Figure A42MX36 Dual-Port SRAM Block
40MX 42MX FPGA Families
Routing Structure
architecture uses vertical horizontal routing tracks interconnect various logic modules. These routing tracks metal interconnects that continuous split into segments. Varying segment lengths allow interconnect over design tracks occur with only antifuse connections. Segments joined together ends using antifuses increase their lengths full length track. interconnects accomplished with maximum four antifuses.
Segmented Horizontal Routing Logic Modules
Antifuses
Vertical Routing Tracks
Horizontal Routing
Horizontal routing tracks span whole length divided into multiple segments located between rows modules. segment that spans more than one-third length considered long horizontal segment. typical channel shown Figure 1-6. Within horizontal routing, dedicated routing tracks used global clock networks power ground tie-off tracks. Non-dedicated tracks used signal nets.
Figure Routing Structure
Clock Networks
40MX devices have global clock distribution network (CLK). signal network being routed through CLKBUF buffer. 42MX devices, there low-skew, high-fanout clock distribution networks, referred CLKA CLKB. Each network clock module (CLKMOD) that select source clock signal from following (Figure page 1-5): Externally from CLKA pad, using CLKBUF buffer Externally from CLKB pad, using CLKBUF buffer Internally from CLKINTA input, using CLKINT buffer Internally from CLKINTB input, using CLKINT buffer
Vertical Routing
Another routing tracks vertically through module. There three types vertical tracks: input, output, long. Long tracks span column length module, divided into multiple segments. Each segment input track dedicated input particular module; each segment output track dedicated output particular module. Long segments uncommitted assigned during routing. Each output segment spans four channels (two above below), except near bottom array, where edge effects occur. Long vertical tracks contain either segments. example vertical routing tracks segments shown Figure 1-6.
clock modules located modules. Clock drivers dedicated horizontal clock track located each horizontal routing channel. Clock input pads both 40MX 42MX devices also used normal I/Os, bypassing clock networks. A42MX36 device four additional register control resources, called quadrant clock networks (Figure page 1-5). Each quadrant clock provides local, highfanout resource contiguous logic modules within quadrant device. Quadrant clock signals originate from specific pins from internal array used secondary register clock, register clear, output enable.
Antifuse Structures
antifuse "normally open" structure. antifuses implement programmable logic device results highly testable structures well efficient programming algorithms. There pre-existing connections; temporary connections made using pass transistors. These temporary connections isolate individual antifuses programmed individual circuit structures tested, which done before after programming. instance, metal tracks tested continuity shorts between adjacent tracks, functionality logic modules verified.
40MX 42MX FPGA Families
CLKB CLKA From Pads
CLKINB CLKINA CLKMOD Internal Signal CLKO(17)
Clock Drivers
CLKO(16) CLKO(15)
CLKO(2) CLKO(1)
Clock Tracks
Figure Clock Networks 42MX Devices
QCLKA Quad Clock Modul QCLK1 QCLK3 Quad Clock Modul
QCLKC QCLKD *QCLK3IN
QCLKB *QCLK1IN
Quad Clock Modul *QCLK2IN
QCLK2
QCLK4
Quad Clock Modul *QCLK4IN
Note: *QCLK1IN, QCLK2IN, QCLK3IN, QCLK4IN internally-generated signals. Figure Quadrant Clock Network A42MX36 Devices
40MX 42MX FPGA Families
MultiPlex Modules
42MX devices feature Multiplex I/Os support 5.0V, 3.3V, mixed 3.3V/5.0V operations. MultiPlex modules provide interface between device pins logic array. Figure block diagram 42MX module. variety user functions, determined library macro selection, implemented module. (Refer Antifuse Macro Library Guide more information.) 42MX modules contain tristate buffers, with input output latches that configured input, output, bidirectional operation. 42MX devices contain flexible structures, where each output dedicated output-enable control (Figure 1-9). module used latch input output data, both, providing fast set-up time. addition, Actel Designer software tools build Dtype flip-flop using C-module combined with module register input output signals. Refer Antifuse Macro Library Guide more details. A42MX24 A42MX36 devices also offer selectable output drives, enabling 100% compliance with version specification. low-power systems, inputs outputs turned reduce current consumption below 500µA. achieve 5.0V 3.3V PCI-compliant output drives A42MX24 A42MX36 devices, chip-wide fuse programmed Device Selection Wizard Designer software (Figure 1-10). When fuse programmed, output drive standard. Actel's Designer software development tools provide design library macro functions that implement configurations supported FPGAs.
Signal Output Drive Enable Fuse
Figure 1-10 Output Structure A42MX24 A42MX36 Devices
Other Architectural Features
Performance
devices operate with internal clock frequencies MHz, enabling fast execution complex logic functions. devices live power-up require auxiliary configuration devices thus optimal platform integrate functionality contained multiple programmable logic devices. addition, designs that previously would have required gate array meet performance integrated into device with improvements cost time-tomarket. Using timing-driven place-and-route (TDPR) tools, designers achieve highly deterministic device performance.
User Security
Actel FuseLock provides robust security against design theft. Special security fuses hidden fabric device prevent unauthorized users from accessing programming and/or probe interfaces. virtually impossible identify bypass these fuses without damaging device, making Actel antifuse FPGAs immune both invasive noninvasive attacks. Special security fuses 40MX devices include Probe Fuse Program Fuse. former disables probing circuitry while latter prohibits further programming fuses, including Probe Fuse. 42MX devices, there Security Fuse which, when programmed, both disables probing circuitry prohibits further programming device. Look this symbol ensure your valuable secure. more information, refer Actel's Implementation Security Actel Antifuse FPGAs application note.
From Array
G/CLK* Array
G/CLK*
Note: *Can configured Latch Flip-Flop (Using C-Module) Figure 42MX Module
40MX 42MX FPGA Families
nonprogrammed), Silicon Sculptor also allows self-test verify hardware extensively. procedure programming device using Silicon Sculptor follows: Load .AFM file Select device programmed Begin programming When design ready production, Actel offers device volume-programming services either through distribution partners In-House Programming from factory. more details programming devices, please refer Programming Antifuse Devices Silicon Sculptor user's guides.
Figure 1-11 Fuselock
Programming
Device programming supported through Silicon Sculptor series programmers. Silicon Sculptor compact, robust, single-site multi-site device programmer With standalone software, Silicon Sculptor designed allow concurrent programming multiple units from same Silicon Sculptor programs devices independently achieve fastest programming times possible. After being programmed, each fuse verified insure that been programmed correctly. Furthermore, programming, there integrity tests that ensure extra fuses have been programmed. only does test fuses (both programmed
Table Device 40MX Voltage Support Devices 5.0V 3.3V 42MX VCCA 5.0V 3.3V 5.0V VCCI 5.0V 3.3V 3.3V
Power Supply
devices designed operate both 5.0V 3.3V environments. particular, 42MX devices operate mixed 5.0V/3.3V systems. Table describes voltage support devices.
Maximum Input Tolerance 5.5V 3.6V 5.5V 3.6V 5.5V
Nominal Output Voltage 5.0V 3.3V 5.0V 3.3V 3.3V
Power-Up/Down Mixed-Voltage Mode
When powering 42MX mixed voltage mode (VCCA 5.0V VCCI 3.3V), VCCA must greater than equal VCCI throughout power-up sequence. VCCI exceeds VCCA during power either I/Os' input protection junction I/Os will forward-biased I/Os will logical HIGH, rises high levels. power-down, sequence with VCCA VCCI implemented.
Power Mode
42MX devices have been designed with Power Mode. This feature, activated with setting special HIGH period longer than particularly useful battery-operated systems where battery life primary concern. this mode, core device turned device consumes minimal power with standby current. addition, input buffers turned off, outputs bidirectional buffers tristated. Since core device turned off, states registers lost. device must re-initialized when exiting Power Mode. driven during mode, clock pins should driven HIGH should float avoid drawing current. exit mode, must pulled over allow charge pumps power device initialization will begin.
40MX 42MX FPGA Families
Power Dissipation
general power consumption devices made static dynamic power expressed with following equation:
power dissipated CMOS circuit expressed equation:
Power (µW) VCCA2 F(1)
where: =Equivalent capacitance expressed picofarads (pF) VCCA =Power supply volts =Switching frequency megahertz (MHz)
General Power Equation
[ICCstandby ICCactive] VCCI IOL* VOL* (VCCI VOH)
where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. Accurate values difficult determine because they depend family type, design details, system I/O. power divided into components: static active.
Equivalent Capacitance
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements have been made over range frequencies fixed value VCC. Equivalent capacitance frequency-independent, results used over wide range operating conditions. Equivalent capacitance values shown below.
Values Actel FPGAs
Modules (CEQM)3.5 Input Buffers (CEQI)6.9 Output Buffers (CEQO)18.2 Routed Array Clock Buffer Loads (CEQCR)1.4 calculate active power dissipated from complete design, switching frequency each part logic must known. equation below shows piece-wise linear summation over components.
Power VCCA2 CEQM fm)Modules CEQI fn)Inputs (CEQO fp)outputs CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2 fq2)routed_Clk2
Static Power Component
static power standby current typically small component overall power consumption. Standby power calculated commercial, worst-case conditions. static power dissipation loads depends number outputs driving, load current. instance, 32-bit sinking 0.33V will generate 42mW with outputs driving LOW, 140mW with outputs driving HIGH. actual dissipation will average somewhere between, I/Os switch states with time.
where: Number frequency Number frequency Number frequency logic input output modules buffers buffers switching switching switching
Active Power Component
Power dissipation CMOS devices usually dominated dynamic power dissipation. Dynamic power consumption frequency-dependent function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitances board traces load device inputs. additional component active power dissipation totem pole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation.
Number clock loads first routed array clock Number clock loads second routed array clock Fixed capacitance first routed array clock Fixed capacitance second routed array clock
40MX 42MX FPGA Families
CEQM Equivalent capacitance logic modules CEQI Equivalent capacitance input buffers CEQO Equivalent capacitance output buffers CEQCR Equivalent capacitance routed array clock Output load capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate routed_Clk1 41.4 68.6 routed_Clk2
resources. Silicon Explorer II's noninvasive method does alter timing loading effects, thus shortening debug cycle providing true representation device under actual functional situations. Silicon Explorer samples data (asynchronous) (synchronous). Silicon Explorer attaches PC's standard port, turning into fully functional 18-channel logic analyzer. Silicon Explorer allows designers complete design verification process their desks reduces verification time from several hours cycle seconds. Silicon Explorer used control MODE, DCLK, pins devices select desired nets debugging. user simply assigns selected internal nets Silicon Explorer software PRA/PRB output pins observation. Probing functionality activated when MODE held HIGH. Figure 1-12 illustrates interconnection between Silicon Explorer 40MX devices, while Figure 1-13 page 1-10 illustrates interconnection between Silicon Explorer 42MX devices allow probing capabilities, security fuses must programmed. (Refer <zBlue>"User Security" section page security fuses 40MX 42MX devices). Table page 1-10 summarizes possible device configurations probing. pins dual-purpose pins. When "Reserve Probe Pin" checked Designer software, pins reserved dedicated outputs probing. pins required user I/Os achieve successful layout "Reserve Probe Pin" checked, layout tool will override option place user I/Os pins.
Fixed Capacitance Values FPGAs (pF) Device Type A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
Test Circuitry Silicon Explorer Probe
devices contain probing circuitry that provides builtin access every node design, Silicon Explorer Silicon Explorer integrated hardware software solution that, conjunction with Designer software, allow users examine internal nets device while operating prototyping production system. user probe into device without changing placement routing design without using additional
Logic Analyzer Channels
Serial Connection Windows
40MX Silicon Explorer MODE DCLK
Figure 1-12 Silicon Explorer Setup with 40MX
40MX 42MX FPGA Families
Logic Analyzer Channels
Serial Connection Windows
42MX Silicon Explorer MODE DCLK
Figure 1-13 Silicon Explorer Setup with 42MX Table Device Configuration Options Probe Capability MODE HIGH PRA, PRB1 User I/Os2 Probe Circuit Outputs Probe Circuit Secured SDI, SDO, DCLK1 User I/Os2 Probe Circuit Inputs Probe Circuit Secured
Security Fuse(s) Programmed Notes:
Avoid using SDI, SDO, DCLK, pins input bidirectional ports. Since these pins active during probing, input signals will pass through these pins cause contention. user signal assigned these pins, they will behave unused I/Os this mode. <zBlue>"Pin Descriptions" section page information unused pins.
Design Consideration
recommended series termination resistor every probe connector (SDI, SDO, MODE, DCLK, PRB). series termination used prevent data transmission corruption during probing reading back checksum.
Each test section accessed through TAP, which four associated pins: (test clock input), (test data input output), (test mode selector). controller four-bit state machine. '1's '0's represent values that must present rising edge given state transition occur. indicate that instruction register data register operating that state. controller receives control inputs (TMS TCK) generates control clock signals rest test logic architecture. power-up, controller enters Test-Logic-Reset state. guarantee reset controller from possible states, must remain high five cycles. 42MX24 42MX36 devices support three types test data registers: bypass, device identification, boundary scan. bypass register selected when other register needs accessed device. This speeds test data transfer other devices test data path. 32-bit device identification register shift register with four fields (lowest significant byte (LSB), number, part number version). boundary-scan register observes controls state each pin.
IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
42MX24 42MX36 devices compatible with IEEE Standard 1149.1 (informally known Joint Testing Action Group Standard JTAG), which defines hardware architecture mechanisms cost-effective board-level testing. basic boundary-scan logic circuit composed (test access port), controller, test data registers instruction register (Figure 1-14 page 1-11). This circuit supports mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/ PRELOAD BYPASS) some optional instructions. Table page 1-11 describes ports that control JTAG testing, while Table page 1-11 describes test instructions supported these devices.
40MX 42MX FPGA Families
Each cell three boundary-scan register cells, each with serial-in, serial-out, parallel-in, parallel-out pin. serial pins used serially connect boundary-scan register cells device into boundaryscan register chain, which starts ends
pin. parallel ports connected internal core logic tile input, output control ports buffer capture load data into register control observe logic state each I/O.
Boundary Scan Register Bypass Register Control Logic JTAG JTAG Instruction Register Controller Instruction Decode
Output
Figure 1-14 42MX IEEE 1149.1 Boundary Scan Circuitry Table Port (Test Select) Test Access Port Descriptions Description Mode Serial input test logic control bits. Data captured rising edge test logic clock (TCK).
(Test Clock Input) Dedicated test logic clock used serially shift test instruction, test data, control inputs rising edge clock, serially shift output data falling edge clock. maximum clock frequency MHz. (Test Data Input) (Test Output) Table Instruction EXTEST Serial input instruction test data. Data captured rising edge test logic clock.
Data Serial output test instruction data from test logic. Inactive Drive state (high impedance) when data scanning progress.
Supported Public Instructions Code (IR2.IR0) Instruction Type Mandatory Description Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Allows snapshot signals device pins captured examined during operation Tristates I/Os allow external signals drive pins. Please refer IEEE Standard 1149.1 specification. Allows state signals driven from component pins determined from Boundary-Scan Register. Please refer IEEE Standard 1149.1 specification details. Enables bypass register between pins. test data passes through selected device adjacent devices test chain.
SAMPLE/PRELOAD HIGH CLAMP
Mandatory Optional Optional
BYPASS
Mandatory
1-11
40MX 42MX FPGA Families
JTAG Mode Activation
JTAG test logic circuit activated Designer software selecting Tools Device Selection. This brings Device Selection dialog shown Figure 1-15. JTAG test logic circuit enabled clicking "Reserve JTAG Pins" check box. Table explains pins' behavior either mode.
Figure 1-15 Device Selection Wizard Table Boundary Scan Configuration Functionality Checked input; must terminated logical HIGH avoid floating input; float tied HIGH output; float connected another device Unchecked User User User
Reserve JTAG TDI,
TRST Controller Reset
active reset (TRST) supported; however, devices contain power-on circuitry that resets boundary scan circuitry upon power-up. Also, equipped with internal pull-up resistor. This allows controller remain return Test-Logic-Reset state when there input when logical pin. reset controller, must HIGH least five cycles.
Boundary Scan Description Language (BSDL) File
Conforming IEEE Standard 1149.1 requires that operation various JTAG components documented. BSDL file provides standard format describe JTAG components that used automatic test equipment software. file includes instructions that supported, instruction pattern, boundary-scan chain order. in-depth discussion BSDL files, please refer Actel BSDL Files Format Description application note. Actel BSDL files grouped into categories generic device-specific. generic files assign user I/Os inouts. Device-specific files assign user I/Os inputs, outputs inouts. Generic files devices available Actel's website
40MX 42MX FPGA Families
Development Tool Support
family FPGAs fully supported both Actel's LiberoIntegrated Design Environment Designer FPGA Development software. Actel Libero design management environment that streamlines design flow. Libero provides integrated design manager that seamlessly integrates design tools while guiding user through design flow, managing design files, passing necessary design data among tools. Additionally, Libero allows users integrate both schematic synthesis into single flow verify entire design single environment. Libero includes Synplify® Actel from Synplicity®, ViewDraw Actel from Mentor Graphics, ModelSimHDL Simulator from Mentor Graphics®, WaveFormer Litefrom SynaptiCADTM, Designer software from Actel. Refer Libero flow (located Actel's website) diagram more information. Actel's Designer software place-and-route tool provides comprehensive suite backend support tools FPGA development. Designer software includes timing-driven place-and-route, world-class integrated static timing analyzer constraints editor. With Designer software, user lock his/her design pins before layout while minimally impacting results place-and-route. Additionally, backannotation flow compatible with major simulators simulation results cross-probed with Silicon Explorer Actel's integrated verification logic analysis tool. Another tool included Designer software ACTgen macro builder, which easily creates popular commonly used logic functions implementation into your schematic design. Actel's Designer software compatible with most popular FPGA design entry verification tools from companies such Mentor Graphics, Synplicity, Synopsys, Cadence Design Systems. Designer software available both Windows UNIX operating systems. Actel's Designer software compatible with most popular FPGA design entry verification tools from companies such Mentor Graphics, Synplicity, Synopsys, Cadence Design Systems. Designer software available both Windows UNIX operating systems.
Related Documents
Application Notes
Actel BSDL Files Format Description Programming Antifuse Devices http://www.actel.com/documents/ AntifuseProgram_AN.pdf Actel's Implementation Security Actel Antifuse FPGAs
User's Guides Manuals
Antifuse Macro Library Guide Silicon Sculptor
Miscellaneous
Libero Flow Diagram
1-13
40MX 42MX FPGA Families
5.0V Operating Conditions
Table Symbol tSTG Supply Voltage Input Voltage Output Voltage Storage Temperature Absolute Maximum Ratings 40MX Devices* Parameter Limits -0.5 +7.0 -0.5 VCC+0.5 -0.5 VCC+0.5 +150 Units
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions. Table Symbol VCCI VCCA tSTG Absolute Maximum Ratings 42MX Devices* Parameter Supply Voltage I/Os Supply Voltage Array Input Voltage Output Voltage Storage Temperature Limits -0.5 +7.0 -0.5 +7.0 -0.5 VCCI+0.5 -0.5 VCCI+0.5 +150 Units
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions. Table Parameter Temperature Range* (40MX) VCCA (42MX) VCCI (42MX) Recommended Operating Conditions Commercial 4.75 5.25 4.75 5.25 4.75 5.25 Industrial Military +125 Units
Note: *Ambient temperature (TA) used commercial industrial grades; case temperature (TC) used military grades.
40MX 42MX FPGA Families
Electrical Specifications
Table Electrical Specifications Commercial Symbol VOH1 VOL1 Parameter -10mA -4mA 10mA (40MX) (42MX) Input Transition Time, Capacitance Standby ICC2 Current, A40MX02, A40MX04 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current 42MX devices only 0.5V 2.7V -0.3 VCC+0.3 VCCI+0.3 -0.3 VCC+0.3 VCCI+0.3 -0.3 VCC+0.3 VCCI+0.3 -0.3 VCC+0.3 VCCI+0.3 Min. Max. Commercial Min. Max. Industrial Min. Max. Military Min. Max. Units
IIO, source sink derived from IBIS model current Notes: Only output tested time. VCC/VCCI min. outputs unloaded. inputs VCC/VCCI GND.
1-15
40MX 42MX FPGA Families
3.3V Operating Conditions
Table Symbol tSTG Absolute Maximum Ratings 40MX Devices* Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Limits -0.5 +7.0 -0.5 VCC+0.5 -0.5 VCC+0.5 +150 Units
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions. Table Symbol VCCI VCCA tSTG Absolute Maximum Ratings 42MX Devices* Parameter Supply Voltage I/Os Supply Voltage Array Input Voltage Output Voltage Storage Temperature Limits -0.5 +7.0 -0.5 +7.0 -0.5 VCCI+0.5 -0.5 VCCI+0.5 +150 Units
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions. Table Parameter Temperature Range* (40MX) VCCA (42MX) VCCI (42MX) Recommended Operating Conditions Commercial Industrial Military +125 Units
Note: *Ambient temperature (TA) used commercial industrial grades; case temperature (TC) used military grades.
40MX 42MX FPGA Families
3.3V LVTTL Electrical Specifications
Table 3.3V LVTTL Electrical Specifications Commercial Symbol VOH1 VOL1 (40MX) (42MX) Input Transition Time, Capacitance Standby Current, ICC2 A40MX02, A40MX04 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current IIO, current Notes: Only output tested time. VCC/VCCI min. outputs unloaded. inputs VCC/VCCI GND. source 42MX devices only Parameter -4mA -0.3 Min. 2.15 VCC+0.3 VCCI+0.3 -0.3 Max. Commercial Min. 2.15 VCC+0.3 VCCI+0.3 -0.3 Max. Industrial Min. 0.48 VCC+0.3 VCCI+0.3 -0.3 Max. Military Min. 0.48 VCC+0.3 VCCI+0.3 Max. Units
sink derived from IBIS model
1-17
40MX 42MX FPGA Families
Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only)
Table Symbol VCCI VCCA tSTG Absolute Maximum Ratings* Parameter Supply Voltage I/Os Supply Voltage Array Input Voltage Output Voltage Storage Temperature Limits -0.5 +7.0 -0.5 +7.0 -0.5 VCCI+0.5 -0.5 VCCI+0.5 +150 Units
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions. Table Parameter Temperature Range* VCCA VCCI Recommended Operating Conditions Commercial 4.75 5.25 3.14 3.47 Industrial Military +125 Units
Note: *Ambient temperature (TA) used commercial industrial grades; case temperature (TC) used military grades.
Mixed 5.0V/3.3V Electrical Specifications
Table Mixed 5.0V/3.3V Electrical Specifications Commercial Symbol VOH1 VOL1 Input Transition Time, Capacitance Standby Current, ICC2 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current source sink current Notes: Only output tested time. VCCI min. outputs unloaded. inputs VCCI GND. 0.5V 2.7V Parameter -10mA -4mA 10mA -0.3 VCCI+0.3 -0.3 VCCI+0.3 -0.3 VCCI+0.3 -0.3 VCCI+0.3 Min. Max. Commercial Min. Max. 'Industrial Min. Max. Military Min. Max. Units
derived from IBIS model
40MX 42MX FPGA Families
Output Drive Characteristics 5.0V Signaling
device drivers were designed specifically high-performance systems. Figure 1-16 page 1-21 shows typical output drive characteristics devices. output drivers compliant with Local Specification.
Table Specification (5.0V Signaling)1 Symbol VCCI CCLK LPIN Notes: Local Specification, Version 2.1, Section 4.2.1.1. Maximum rating VCCI -0.5V 7.0V. Dependent upon chosen package. recommends packaging reduce inductance capacitance. Table Specifications (5.0V Signaling)* Symbol Slew Slew Parameter Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition 0.4V 2.4V load 2.4V 0.4V load Min. (VIN /0.015 Max. Min. Max. Units V/ns V/ns Parameter Supply Voltage I/Os Input High Voltage Input Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Voltage Input Capacitance Capacitance Inductance 2.7V VIN=0.5V IOUT IOUT IOUT 0.55 3.84 0.33 Condition Min. 4.75 -0.5 Max. 5.25 Min. 4.75 -0.3 Max. 5.252 VCCI Units
Note: *PCI Local Specification, Version 2.1, Section 4.2.1.2.
1-19
40MX 42MX FPGA Families
Output Drive Characteristics 3.3V Signaling
Table Specification (3.3V Signaling)1 Symbol VCCI CCLK LPIN Notes: Local Specification, Version 2.1, Section 4.2.2.1. Maximum rating VCCI -0.5V 7.0V. Dependent upon chosen package. recommends packaging reduce inductance capacitance. Table Specifications (3.3V Signaling)* Symbol Slew Slew Parameter Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition 0.2V 0.6V load 0.6V 0.2V load Min. (VIN /0.015 Max. Min. Max. Units V/ns V/ns Parameter Supply Voltage I/Os Input High Voltage Input Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Voltage Input Capacitance Capacitance Inductance IOUT IOUT 2.7V Condition Min. -0.5 Max. VCCI Min. -0.3 Max. VCCI Units
Note: *PCI Local Specification, Version 2.1, Section 4.2.2.2.
40MX 42MX FPGA Families
0.50 0.45 0.40 0.35 0.30 0.25 0.20 Current 0.15 0.10
Maximum
Minimum
0.05 0.00
-0.05 -0.10 -0.15 -0.20
Maximum
Minimum
Voltage
Figure 1-16 Typical Output Drive Characteristics (Based Upon Measured Data)
1-21
40MX 42MX FPGA Families
Junction Temperature (TJ)
temperature variable Designer software refers junction temperature, ambient temperature. This important distinction because heat generated from dynamic power consumption usually hotter than ambient temperature. 1-1, shown below, used calculate junction temperature.
Junction Temperature Ta(1)
Power
Junction ambient package. numbers
located Package Thermal Characteristics table below.
Package Thermal Characteristics
device junction-to-case thermal characteristic junction-to-ambient characteristic thermal characteristics shown with different flow rates. maximum junction temperature 150°C. Maximum power dissipation commercialindustrial-grade devices function
Where: Ambient Temperature Temperature gradient between junction (silicon) ambient P(2)
sample calculation absolute maximum power dissipation allowed TQFP 176-pin package commercial temperature still follow:
Max. junction temp. (°C) Max. ambient temp. (°C) 150°C 70°C Maximum Power Allowed 2.86W 28°C/W (°C/W)
maximum power dissipation military-grade devices function sample calculation absolute maximum power dissipation allowed CQFP 208-pin package military temperature still follows:
Max. junction temp. (°C) Max. ambient temp. (°C) 150°C 125°C Maximum Power Allowed 3.97W (°C/W) 6.3°C/W
Table
Package Thermal Characteristics
Plastic Packages Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Plastic Ball Grid Array Ceramic Packages Ceramic Quad Flat Pack Ceramic Quad Flat Pack 22.0 20.0 19.8 16.5 18.0 15.0 °C/W °C/W Count
12.0 10.0 16.0 13.0 12.0 11.0 12.0 10.0
Still 27.8 26.2 26.1 25.6 20.0 25.0 22.5 24.7 38.2 35.3 18.3
ft/min. ft/min. 23.4 22.8 22.5 22.3 24.5 21.0 18.9 19.9 31.9 29.4 14.9 21.2 21.1 20.8 20.8 22.0 19.4 17.6 18.0 29.4 27.1 13.9
Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W
40MX 42MX FPGA Families
Timing Models
Input Delay Internal Delays Predicted Routing Delays Output Delay
Module Logic Module tIRD1=2.09 tIRD4=3.64 tIRD8=5.73 tPD=1.24 tCO=1.24 tRD1=1.28 tRD2=1.80 tRD4=2.33 tRD8=4.93
Module tINYL=0.62 IRD2=2.59
tDLH=3.32 tENHZ=7.92
Array Clock
tCKH=4.55 FMAX=180
FO=128
Note: Values shown 40MX `-3' speed devices 5.0V worst-case commercial conditions. Figure 1-17 40MX Timing Model*
Input Delays
Module tINYL=0.8 IRD1=2.0 Combinatorial Logic Module PD=1.2 tRD1=0.7 tRD2=1.9 tRD4=1.4 RD8=2.3 Module Sequential Logic Module Combin -atoria Logic include tSUD=0.3 HD=0.00 tCKH=2.70 MAX=296 tLCO=5.2 (light loads, pad-to-pad) tDLH=2.5
Internal Delays
Predicted Routing Delays
Output Delays
Module
DLH=2.5
tINH=0.0 INSU=0.3 tINGL=1.3
tRD1=0.70
ENHZ=4.9
tOUTH=0.00 OUTSU=0.3 tGLH=2.6
Array Clocks
CO=1.3
Notes: *Values shown A42MX09 `-3' 5.0V worst-case commercial conditions. Input module predicted routing delay. Figure 1-18 42MX Timing Model*
1-23
40MX 42MX FPGA Families
Input Delays
Module tINYL=0.8 tIRD1=2.0
Internal Delays
Predicted Routing Delays
Output Delays
Module
Combinatorial Logic Module tPD=1.2 tRD1=0.7 RD2=1.9 tRD4=1.4 tRD8=2.3 Module Sequential Logic Module Combin -atoria Logic include tSUD=0.3 tHD=0.00 CKH=2.70 FMAX=296 LCO=5.2 (light loads, pad-to-pad) tCO=1.3
tDLH=2.5
tINH=0.0 INSU=0.3 tINGL=1.3
tDLH=2.5
tRD1=0.70
ENHZ=4.9
tOUTH=0.00 tOUTSU=0.3 tGLH=2.6
Array Clocks
Notes: Values shown A42MX36 `-3' 5.0V worst-case commercial conditions. Load-dependent Figure 1-19 42MX Timing Model (Logic Functions Using Quadrant Clocks)
Input Delays Module tINPY=1.0ns
tIRD1=2.0ns
tINSU=0.5ns tINH=0.0ns tINGO=1.4ns
Predicted Routing Delays [7:0] WRAD [5:0] BLKEN WCLK tADSU=1.6ns tADH=0.0ns tWENSU=2.7ns tBENS=2.8ns [7:0] RDAD [5:0] RCLK tADSU=1.6ns tADH=0.0ns tRENSU=0.6ns tRCO=3.4ns tRD1=0.9ns
Module tDLH=2.6ns
Array Clocks FMAX =167
tGHL=2.9ns tLSU=0.5ns tLH=0.0ns
Note: *Values shown A42MX36 5.0V worst-case commercial conditions. Figure 1-20 42MX Timing Model (SRAM Functions)
40MX 42MX FPGA Families
Parameter Measurement
TRIBUFF test loads (shown below)
1.5V 1.5V tDHL tDLH
VCCI 1.5V tENZL tENLZ
1.5V tENHZ tENZH
Figure 1-21 Output Buffer Delays
Load (Used measure propagation delay)
Load (Used measure rising/falling edges)
output under test
output under test
VCCI tPLZ/tPZL tPHZ/tPZH R=1k
Figure 1-22 Test Loads
INBUF
1.5V 1.5V VCCI tINYH
tINYL
tPHL
tPLH
Figure 1-23 Input Buffer Delays
Figure 1-24 Module Delays
1-25
40MX 42MX FPGA Families
Sequential Module Timing Characteristics
(Positive Edge-Triggered)
tSUD WCLKA tSUENA tHENA tWCLKI
PRE,
tWASYN
Note: represents data functions involving multiplexed flip-flops. Figure 1-25 Flip-Flops Latches
40MX 42MX FPGA Families
Sequential Timing Characteristics
DATA IBDL
DATA tINH tINSU
Figure 1-26 Input Buffer Latches
OBDLHS
tOUTSU tOUTH
Figure 1-27 Output Buffer Latches
1-27
40MX 42MX FPGA Families
Decode Module Timing
A-G,
tPHL tPLH
Figure 1-28 Decode Module Timing
SRAM Timing Characteristics
Write Port WRAD [5:0] BLKEN WCLK [7:0] Array 64x4 Bits) Read Port RDAD [5:0] RCLK [7:0]
Figure 1-29 SRAM Timing Characteristics
Dual-Port SRAM Timing Waveforms
RCKHL WCLK ADSU WD[7:0] WRAD[5:0] Valid WENSU BENSU BLKEN Valid BENH WENH tADH RCKHL
Note: Identical timing falling edge clock. Figure 1-30 42MX SRAM Write Operation
40MX 42MX FPGA Families
tCKHL RCLK
tRCKHL
tRENSU tADSU RDAD[5:0] Valid
tRENH
tADH
tRCO tDOH RD[7:0] Data Data
Note: Identical timing falling edge clock. Figure 1-31 42MX SRAM Synchronous Read Operation
RDADV
RDAD[5:0]
ADDR1
ADDR2
RD[7:0]
Data
Data
Figure 1-32 42MX SRAM Asynchronous Read Operation-Type (Read Address Controlled)
tWENSU
tWENH
WD[7:0] WRAD[5:0] BLKEN
Valid
tADSU WCLK
tADH tRPD tDOH
RD[7:0]
Data
Data
Figure 1-33 42MX SRAM Asynchronous Read Operation-Type (Write Address Controlled)
1-29
40MX 42MX FPGA Families
Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends resistive capacitive loading routing tracks, interconnect elements, module inputs being driven. Propagation delay increases length routing tracks, number interconnect elements, number inputs increases. From design perspective, propagation delay statistically correlated modeled fanout (number loads) driven module. Higher fanout usually requires some paths have longer routing tracks. FPGAs deliver tight fanout delay distribution, which achieved ways: decreasing delay interconnect elements decreasing number interconnect elements path. Actel's patented antifuse offers very resistive/ capacitive interconnect. antifuses, fabricated 0.45 lithography, offer nominal levels resistance 7.0fF capacitance antifuse. fanout distribution also tight number antifuses required each interconnect path. proprietary architecture limits number antifuses path maximum four, with percent interconnects using only antifuses.
Critical Nets Typical Nets
Propagation delays expressed only typical nets, which used initial design performance evaluation. Critical delays then applied most timing critical paths. Critical nets determined property assignment Actel's Designer software prior placement routing. nets design designated critical.
Long Tracks
Some nets design long tracks, which special routing resources that span multiple rows, columns, modules. Long tracks employ three sometimes four antifuse connections, which increase capacitance resistance, resulting longer delays macros connected long tracks. Typically, percent nets fully utilized device require long tracks. Long tracks approximately delay, which represented statistically higher fanout (FO=8) routing delays data sheet specifications section, shown Table page 1-36.
Timing Derating
devices manufactured with CMOS process. Therefore, device performance varies according temperature, voltage, process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature worst-case processing.
Timing Characteristics
Device timing characteristics fall into three categories: family-dependent, device-dependent, designdependent. input output buffer characteristics common devices. Internal routing delays device-dependent; actual delays determined until after place-and-route user's design complete. Delay values then determined using Designer software utility performing simulation with post-layout delays.
40MX 42MX FPGA Families
Temperature Voltage Derating Factors
Table 42MX Temperature Voltage Derating Factors (Normalized 25°C, VCCA 5.0V) Temperature 42MX Voltage 4.50 4.75 5.00 5.25 5.50 -55°C 0.93 0.88 0.85 0.84 0.83 -40°C 0.95 0.90 0.87 0.86 0.85 1.05 1.00 0.96 0.95 0.94 25°C 1.09 1.03 1.00 0.97 0.96 70°C 1.25 1.18 1.15 1.12 1.10 85°C 1.29 1.22 1.18 1.14 1.13 125°C 1.41 1.34 1.29 1.28 1.26
1.50 1.40 1.30 -55°C 1.20 -40°C 1.10 25°C 70°C 85°C 125°C 4.50 4.75 5.00 Voltage 5.25 5.50 1.00 0.90 0.80 0.70 0.60
Note: This derating factor applies routing propagation delays. Figure 1-34 42MX Junction Temperature Voltage Derating Curves (Normalized 25°C, VCCA 5.0V)
Derating
Factor
1-31
40MX 42MX FPGA Families
Table
40MX Temperature Voltage Derating Factors (Normalized 25°C, 5.0V) Temperature
40MX Voltage 4.50 4.75 5.00 5.25 5.50
-55°C 0.89 0.84 0.82 0.80 0.79
-40°C 0.93 0.88 0.85 0.82 0.82
1.02 0.97 0.94 0.91 0.90
25°C 1.09 1.03 1.00 0.97 0.96
70°C 1.25 1.18 1.15 1.12 1.10
85°C 1.31 1.24 1.20 1.16 1.15
125°C 1.45 1.37 1.33 1.29 1.28
1.50 1.40 1.30
Factor
-55°C 1.20 -40°C 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 Voltage 5.25 5.50 25°C 70°C 85°C 125°C
Note: This derating factor applies routing propagation delays. Figure 1-35 40MX Junction Temperature Voltage Derating Curves (Normalized 25°C, 5.0V)
Derating
40MX 42MX FPGA Families
Table
42MX Temperature Voltage Derating Factors (Normalized 25°C, VCCA 3.3V) Temperature
42MX Voltage 3.00 3.30 3.60
-55°C 0.97 0.84 0.81
-40°C 1.00 0.87 0.84
1.10 0.96 0.92
25°C 1.15 1.00 0.96
70°C 1.32 1.15 1.10
85°C 1.36 1.18 1.13
125°C 1.45 1.26 1.21
1.60 1.50 1.40 1.30 Derating Factor 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 3.00 3.30 Voltage
Note: This derating factor applies routing propagation delays. Figure 1-36 42MX Junction Temperature Voltage Derating Curves (Normalized 25°C, VCCA 3.3V)
55°C 40°C 25°C 70°C 85°C 125°C
3.60
1-33
40MX 42MX FPGA Families
Table
40MX Temperature Voltage Derating Factors (Normalized 25°C, 3.3V) Temperature
40MX Voltage 3.00 3.30 3.60
-55°C 1.08 0.86 0.83
-40°C 1.12 0.89 0.85
1.21 0.96 0.92
25°C 1.26 1.00 0.96
70°C 1.50 1.19 1.14
85°C 1.64 1.30 1.25
125°C 2.00 1.59 1.53
2.20 2.00 1.80
55°C 40°C 25°C 70°C 85°C 125°C
Derating Factor
1.60 1.40 1.20 1.00 0.80 0.60 3.00 3.30 3.60
Voltage
Note: This derating factor applies routing propagation delays. Figure 1-37 40MX Junction Temperature Voltage Derating Curves (Normalized 25°C, 3.3V)
40MX 42MX FPGA Families
System Timing Specification
Table Table list critical timing parameters corresponding timing parameters PCI-compliant devices.
Table Clock Specification
Models
Actel provides synthesizable VHDL Verilog-HDL models Target interface, Target Target+DMA Master interface. Contact your Actel sales representative more details.
Symbol tCYC tHIGH tLOW Table Parameter Cycle Time High Time Time Timing Parameters Symbol tVAL tVAL(PTP) tOFF tSU(PTP) Notes: Parameter Signal Valid-Bused Signals Signal Valid-Point-to-Point Float Active Active Float Input Set-Up Time CLK-Bused Signals Input Set-Up Time CLK-Point-to-Point Input Hold Min.
A42MX24 Max. Min. Max.
A42MX36 Min. Max. Units
Min.
A42MX24 Max. Min. Max. 8.31
A42MX36 Min. Max. 8.31 Units
TOFF system dependent. devices have turn-off time, reflection typically additional REQ# GNT# point-to-point signals have different output valid delay input setup times than bussed signals. GNT# setup REW# setup
1-35
40MX 42MX FPGA Families
Timing Characteristics
Table A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1 10.6 `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing2 tSUD tHD3 tSUENA tHENA tWCLKA tWASYN fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128) 10.4
Input Module Propagation Delays tINYH tINYL Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro. Delays based 35pF loading. Pad-to-Y HIGH Pad-to-Y
40MX 42MX FPGA Families
Table
A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
12.4
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro. Delays based 35pF loading. Input HIGH Input High Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 3.01 10.0 10.4 10.4 10.4
1-37
40MX 42MX FPGA Families
Table
A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
0.02 0.03
0.02 0.03
10.4 0.03 0.03
12.2 0.03 0.04
10.1 17.1 12.6 0.04 0.06
ns/pF ns/pF
Enable HIGH Enable Delta HIGH Delta HIGH
CMOS Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro. Delays based 35pF loading. Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable 0.03 0.02 0.04 0.02 10.4 0.04 0.03 6.05 12.2 0.05 0.03 10.5 17.0 12.6 0.07 0.04 ns/pF ns/pF
Enable HIGH Enable Delta HIGH Delta HIGH
40MX 42MX FPGA Families
Table
A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.9
15.2
Logic Module Sequential Timing tSUD tHD3 tSUENA tHENA tWCLKA tWASYN fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
14.6
Input Module Propagation Delays tINYH tINYL Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro. Delays based loading. Pad-to-Y HIGH Pad-to-Y
1-39
40MX 42MX FPGA Families
Table
A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
9.26
10.5
12.6
11.0 17.3
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period 10.1 10.4 14.1 14.6 10.4 10.4 13.7 13.7 14.5 14.5
Maximum Frequency
Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro. Delays based loading. Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH 11.1 0.03 0.04 12.8 0.03 0.04 14.5 10.7 0.04 0.05 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns/pF ns/pF
40MX 42MX FPGA Families
Table
A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
11.1 0.05 0.03
12.8 0.05 0.03
14.5 10.7 0.06 0.04
10.5 17.1 12.6 0.07 0.04
11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06
ns/pF ns/pF
Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro. Delays based loading.
1-41
40MX 42MX FPGA Families
Table
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.9
Logic Module Sequential Timing tSUD tHD3 tSUENA tHENA tWCLKA tWASYN fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
Input Module Propagation Delays tINYH tINYL Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer utility from Designer software check hold time this macro. Delays based loading. Pad-to-Y HIGH Pad-to-Y
40MX 42MX FPGA Families
Table
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
12.4
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input High Minimum Width HIGH Minimum Width 3.01 10.0 10.4 10.4 10.4
Pulse Pulse
Maximum Skew Minimum Period Maximum Frequency
Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer utility from Designer software check hold time this macro. Delays based loading. Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH 0.02 0.03 0.02 0.03 10.4 0.03 0.03 12.2 0.03 0.04 10.1 17.1 12.6 0.04 0.06 ns/pF ns/pF
1-43
40MX 42MX FPGA Families
Table
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
0.03 0.02
0.04 0.02
10.4 0.04 0.03
6.05 12.2 0.05 0.03
10.5 17.0 12.6 0.07 0.04
ns/pF ns/pF
Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer utility from Designer software check hold time this macro. Delays based loading.
40MX 42MX FPGA Families
Table
A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.9
15.2
Logic Module Sequential Timing tSUD tHD3 tSUENA tHENA tWCLKA tWASYN fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
14.6
Input Module Propagation Delays tINYH tINYL Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro. Delays based loading. Pad-to-Y HIGH Pad-to-Y
1-45
40MX 42MX FPGA Families
Table
A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
10.5
12.4
11.0 17.2
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period 10.1 10.4 14.1 14.6 10.4 10.4 13.8 13.8 14.6 14.6
Maximum Frequency
Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro. Delays based loading. Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH 11.1 0.03 0.04 12.8 0.03 0.04 14.5 10.7 0.04 0.05 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns/pF ns/pF
40MX 42MX FPGA Families
Table
A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
11.1 0.05 0.03
12.8 0.05 0.03
14.5 10.7 0.06 0.04
10.5 17.1 12.6 0.07 0.04
11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06
ns/pF ns/pF
Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro. Delays based loading.
1-47
40MX 42MX FPGA Families
Table
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCCA 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Logic Module Propagation tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing3,
Logic Module Sequential tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Notes:
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
40MX 42MX FPGA Families
Table
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew
Input Latch External Set-Up Input Latch External Hold Minimum Period
Maximum Frequency
1-49
40MX 42MX FPGA Families
Table
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Notes:
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-toPad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
0.03 0.04
0.03 0.04
0.03 0.04
10.9 0.04 0.05
10.2 11.1
10.8 15.3 0.06 0.07
ns/pF ns/pF
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
40MX 42MX FPGA Families
Table
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-toPad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
0.03 0.04
0.03 0.04
0.03 0.04
10.9 0.04 0.05
10.2 11.1
10.8 15.3 0.06 0.07
ns/pF ns/pF
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
1-51
40MX 42MX FPGA Families
Table
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCCA 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Logic Module Propagation tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Notes:
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
12.9
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
40MX 42MX FPGA Families
Table
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2.17
Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 10.8
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Input HIGH Input HIGH Minimum Width HIGH Minimum Width 12.9 14.2 10.2 11.2
Pulse Pulse
Maximum Skew
Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency
1-53
40MX 42MX FPGA Families
Table
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable
10.9
10.2 11.1 12.9
14.2 15.5 12.0 12.0
Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-toOut (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
18.0
tACO
12.2
13.5
15.4
18.1
25.3
dTLH dTHL Notes:
0.00 0.09
0.00 0.10
0.00 0.10
0.10 0.10
0.01 0.10
ns/pF ns/pF
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
40MX 42MX FPGA Families
Table
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-toPad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
12.2 0.04 0.05
13.5 0.04 0.05
10.9 15.4 0.05 0.06
10.2 11.1 12.9 18.1 0.06 0.07
14.2 15.5 12.0 12.0
18.0 25.3 0.08 0.10
ns/pF ns/pF
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
1-55
40MX 42MX FPGA Families
Table
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Logic Module Propagation Delays tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing3,4 10.1 14.1
Logic Module Sequential tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Notes:
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, point position whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
40MX 42MX FPGA Families
Table
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, point position whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Input HIGH Input HIGH Minimum Width HIGH Minimum Width 4.67 10.7
Pulse Pulse
Maximum Skew
Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency
1-57
40MX 42MX FPGA Families
Table
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Timing5
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-toPad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH
0.03 0.04
0.03 0.04
10.1 0.03 0.04
11.9 0.04 0.05
11.2 10.4 11.9 16.7 0.06 0.07
ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH Notes: Data-to-Pad HIGH Data-to-Pad
0.03
0.03
10.1 0.03
11.9 0.04
11.2 10.4 10.5 10.5 11.9 16.7 0.06
ns/pF
Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-toPad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, point position whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
40MX 42MX FPGA Families
Table
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Delays1 Delays2
Parameter Description Logic Module Propagation tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Notes: Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential
Timing3, 10.6 12.0 0.89 14.1 1.01 1.01 12.9 19.8
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
dual-module macros tPD1 tRD1 taped, tRD1 taped, tPD1 tRD1 tusk, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
1-59
40MX 42MX FPGA Families
Table
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Notes: Pad-to-Y HIGH Pad-to-Y HIGH Delays2
Input Module Predicted Routing FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.5
Global Clock Network Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew 10.7 16.2 17.8 11.8 13.7 11.0 12.9 11.0 12.9
Input Latch External Set-Up Input Latch External Hold Minimum Period
Maximum Frequency
dual-module macros tPD1 tRD1 taped, tRD1 taped, tPD1 tRD1 tusk, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
40MX 42MX FPGA Families
Table
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Parameter Description Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Notes: Timing5
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-toPad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH
11.3 0.04 0.05
12.5 0.04 0.05
10.1 14.2 0.05 0.06
11.2 10.4 11.9 16.7 0.06 0.07
15.7 14.5 10.0 10.0 16.7 23.3 0.08 0.10
ns/pF ns/pF
CMOS Output Module Timing5 Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-toPad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 11.3 0.04 0.05 12.5 0.04 0.05 10.1 14.2 0.05 0.06 11.2 10.4 10.5 10.5 11.9 16.7 0.06 0.07 15.7 14.5 14.7 14.7 16.7 23.3 0.08 0.10 ns/pF ns/pF
dual-module macros tPD1 tRD1 taped, tRD1 taped, tPD1 tRD1 tusk, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
1-61
40MX 42MX FPGA Families
Table
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Logic Module Combinatorial tPDD Functions1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Internal Array Module Delay Internal Decode Module Delay
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3, tSUD tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width
40MX 42MX FPGA Families
Table
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 10.9 11.9
Input Latch External FO=32 Set-Up FO=486 Input Latch External FO=32 Hold FO=486 Minimum Period (1/fMAX) FO=32 FO=486
1-63
40MX 42MX FPGA Families
Table
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Notes:
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH
10.6 0.04 0.03
11.8 0.04 0.03
13.4 0.04 0.03
15.7 0.05 0.04
10.7
11.4 22.0 0.07 0.06
ns/pF ns/pF
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
40MX 42MX FPGA Families
Table
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-toPad) Array Latch Clock-to-Out (Padto-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
10.6 0.04 0.03
11.8 0.04 0.03
13.4 0.04 0.03
15.7 0.05 0.04
10.7 10.1 10.1
11.3 22.0 0.07 0.06
ns/pF ns/pF
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
1-65
40MX 42MX FPGA Families
Table
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Logic Module Combinatorial tPDD Functions1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Internal Array Module Delay Internal Decode Module Delay
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3, tSUD tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 12.6
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Input Data Pad-to-Y Input Latch Gate-toOutput Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 13.5
40MX 42MX FPGA Families
Table
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
10.0
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 10.0 10.6 12.4
Input Latch External FO=32 Set-Up FO=486
Output Module Timing5 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up 10.7 14.9 13.9 10.0 10.0
1-67
40MX 42MX FPGA Families
Table
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, 3.0V, 70°C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Output Module Timing (Continued) tLCO tACO dTLH dTHL Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH Timing5
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
14.8 0.05 0.04
16.5 0.05 0.04
18.7 0.06 0.05
11.3 22.0 0.07 0.06
15.9 30.8 0.10 0.08
ns/pF ns/pF
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tHEXT Notes:
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH Input Latch External FO=32 Hold FO=486 Minimum Period (1/fMAX) FO=32 FO=486
14.8 0.05 0.04
16.5 0.05 0.04 10.4
18.7 0.06 0.05 10.8 11.9
10.7 10.1 10.1 11.3 22.0 0.07 0.06 18.2 19.9
14.9 13.9 14.2 14.2
15.9 30.8 0.10 0.08
ns/pF ns/pF
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
40MX 42MX FPGA Families
Table
A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Logic Module Combinatorial tPDD Functions1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Internal Array Module Delay Internal Decode Module Delay Delays2
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Decode-to-Output Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Synchronous SRAM Operations tRCKHL tRCO tADSU Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time 10.0 10.0 14.0 14.0
1-69
40MX 42MX FPGA Families
Table
A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Synchronous SRAM Operations (Continued) tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 11.1 10.2 13.0 12.0 18.2 16.8
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width
40MX 42MX FPGA Families
Table
A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Delays2
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 12.7 13.8 10.1
Input Latch External FO=32 Set-Up FO=635 Input Latch External FO=32 Hold FO=635 Minimum Period (1/fMAX) FO=32 FO=635
Maximum Datapath FO=32 Frequency FO=635
Output Module Timing5 tDLH tDHL tENZH tENZL tENHZ Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH 10.9
1-71
40MX 42MX FPGA Families
Table
A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, 4.75V, 70°C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed
Parameter Description Output Module tENLZ tGLH tGHL tLSU tLCO tACO dTLH
Other recent searches
WMD011-Serial - WMD011-Serial WMD011-Serial Datasheet
TAT7430B - TAT7430B TAT7430B Datasheet
TAT7430B - TAT7430B TAT7430B Datasheet
LMV710 - LMV710 LMV710 Datasheet
LMV711 - LMV711 LMV711 Datasheet
LMV715 - LMV715 LMV715 Datasheet
BY268 - BY268 BY268 Datasheet
BY269 - BY269 BY269 Datasheet
BDY58A - BDY58A BDY58A Datasheet
ACE100 - ACE100 ACE100 Datasheet
ADC100 - ADC100 ADC100 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
