85C501/502/503 Overview SiS85C501 SiS85C502 SiS85C503 PCI/ISA Cac
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Pentium/P54C PCI/ISA Chipset
85C501/502/503 Overview
SiS85C501 SiS85C502 SiS85C503 PCI/ISA Cache Memory Controller (PCMC) Local Data Buffer (PLDB) System (PSIO)
whole SiS85C501, 85C502, 85C503 provides fully integrated support Pentium/P54C PCI/ISA system. chipset developed using very high level function integration system partitioning. With SiS85C501, SiS85C502, SiS85C503 chipset, only TTLs (include DRAM address buffer) required implement cost, high performance, Pentium/P54C PCI/ISA system. Figure shows system block diagram.
SRAM
Pentium P54C
Address Data HOST
PCMC
Address/Data
DRAM
PLDB
PSIO
Local Device
Local Device Device
Device
Address Data
Figure System Block Diagram
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
SiS85C501
Features
Supports Pentium Processor Speed Supports P54C Processor MHz, Speed Supports Pipelined Address Mode Pentium P54C Processor Integrated Second Level Cache Controller Write Through Write Back Cache Modes bits bits with Direct Mapped Organization Supports Standard Burst SRAMs Supports KBytes MBytes Cache Sizes Cache Read/Write Cycle 3-2-2-2 4-2-2-2 Using Standard SRAMs Cache Read/Write Cycle 3-1-1-1 Using Burst SRAMs Integrated DRAM Controller Supports MBytes MBytes Cacheable Main Memory Concurrent Write Back CAS#-before-RAS# Transparent DRAM Refresh 256K/1M/4M/16M 70ns Fast Page Mode DRAM Support Programmable DRAM Speed Programmable CAS# driving Current Programmable Non-Cacheable Regions Option Disable Local Memory Non-Cacheable Regions Shadow Increments KBytes Supports Pentium/P54C Mode Supports Stop Clock Provides High Performance Arbiter Supports Four Masters Supports Rotating Priority Mechanism Hidden Arbitration Scheme Minimizes Arbitration Overhead Integrated Bridge Translates Cycles into Cycles Provides CPU-to-PCI Read Assembly Write Disassembly Mechanism Translates Sequential CPU-to-PCI Memory Write Cycles into Burst Cycles Burst Write Pace X-2-2-2-. Burst Read Cache X-2-2-2-. Burst Read DRAM X-3-2-3-2-. Cache Snoop Filters Ensure Data Coherency Minimize Snoop Frequency 208-Pin PQFP Package 0.6µm CMOS Technology
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset Functional Block Diagram
HA[31:3] HBE[7:0]# ADS# M/IO# W/R# D/C# CACHE# BRDY# CPUHOLD CPUHLDA HITM# A20M# KEN# EADS# CPURST INIT
INTERFACE
INTERFACE
C/BE[3:0]# AD[31:0] FRAME# IRDY# TRDY# DEVSEL# STOP# SERR# REQ[3:0]# GNT[3:0] PLOCK# PCICLKO PCICLKI PCIRST#
TAG[7:0] ALTWE# TAGWE# KA4X KA3/KA4Y KREX#/ COE0# KREY#/ COE1# KWEX# KWEY# CALE ADSC#/
FLUSH#
BUFFER CONTROL
CACHE CONTROL
HCR[1:0] ADLE# ADOE MDLE CMPSH CMPOP CPPSH CPPOP PRDLE HGDW PARITY# SMOUT WAKEUP[1:0] SMI# SMIACT# STPCLK# SIOREQ# SIOGNT# KBRST#/BREAK# TURBO# ACLK PWRGD
ADSV# KCE[7:0]#/ CWE[7:0]# RAS[3:0] CAS[7:0] RAMW# MA[11:0]
MISC.
DRAM CONTROL
SiS85C501 Functional Block Diagram
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
General Description
SiS85C501(PCMC) bridges between host local bus. SiS85C501 (PCMC) monitors each cycle initiated CPU, forwards cycle does target local memory. local memory cycles, built-in Cache DRAM Controller assume control secondary cache, DRAMs, SiS85C502 (PLDB). SiS85C501 (PCMC) also guides SiS85C502 (PLDB) correct data flow. Green functions provided.
Interface
SiS85C501 designed support Pentium/P54C host 66.667/60/50MHz. host data DRAM 64-bit wide. interface
SiS85C501 supports pipelined addressing mode Pentium/P54C issuing next address signal, NA#. only generated cases:a) burst read cache DRAM, single read DRAM. PCMC supports write back(WB) write through(WT) cache PCMC cache. cache snooped assertion EADS# when HOLD state. PCMC issues CPUHOLD Pentium/P54C response assertion master reguests(REQ[3:0]#, SIOREQ#). Upon receiving CPUHLDA from CPU, does immediately assert GNT[3:0]# SIOGNT# until both posted write buffer Memmory write buffer empty. During inquire cycles, CPUHOLD negated temporarily allow write back inquired modified line DRAM.
Cache Controller
built-in Cache Controller uses direct-mapped, scheme, which configured either write through write back mode. Both standard burst SRAMs supported. Table shows cache sizes that supported SiS85C501, with corresponding sizes, data sizes, cacheable memory sizes. Tables summarize performance options when either standard SRAMs Burst SRAMs used.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Table Cache Size 128K 256K 512K 512K
Data 8Kx8x8 8Kx8x16 32Kx8x8 32Kx8x16 64Kx8x8 128Kx8x8 64Kx8x16 128Kx8x16
2Kx8 4Kx8 8Kx8 16Kx8 16Kx8 32Kx8 32Kx8 64Kx8
Alter 2Kx1 4Kx1 8Kx1 16Kx1 16Kx1 32Kx1 32Kx1 64Kx1
Cacheable Size 128M 128M 128M 128M 128M
Interleaved
PCMC also provides alternative save dirty SRAM chip. This accomplished sharing alter with address bits same 8-bit wide RAM. System uses this implementation supports address bits dirty bit. doing cacheable local memory sizes reduced half original sizes indicated Table reality, Cacheable DRAM Size determined Max. Cacheable Size described table Noncacheable Area defined register 57h, 58h, Segment Cachability defined register 53h, 54h, 55h, 56h. But, Cacheable size only determined maximum DRAM size, i.e., bytes. Thus, cycles with address ranging over Cacheable Size within 128M bytes also cacheable behavior KEN# ruled Cacheability. Note that only code segment cacheable L1/L2, data portion segment cacheable L1/L2. Table Standard SRAM Cycle Type 66,60 Burst read 3/4/5-2-2-2 3/4/5-3-3-3 Burst write 3/4/5-2-2-2 3/4/5-3-3-3 Single read 3/4/5 Single write 3/4/5
50MHz 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5 3/4/5
Note standard SRAM speed 66/60MHz 15ns. 50MHz, 20ns. X-Y-Y-Y recommended setting. example, 4-2-2-2 recommended cycle setting 66MHz burst read.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Table Burst SRAM Cycle type 66,60 Burst read 3/4-1-1-1 3/4-2-2-2 Burst write 3/4-1-1-1 3/4-2-2-2 Single read Single write
50MHz 3/4-1-1-1 3/4-2-2-2 3/4-1-1-1 3/4-2-2-2
Note burst SRAM speed 66/60MHz 50MHz, 12ns. X-Y-Y-Y recommended setting. Table Asynchronous SRAM speed setting (apply read write cycle) 66MHz 60MHz 50MHz cache configuration Data Data 3-1-1-1 interleave -15ns 3-1-1-1 non-interleave -3-2-2-2 interleave -20ns 3-2-2-2 non-interleave -20ns 3-3-3-3 interleave -20ns 3-3-3-3 non-interleave -20ns 4-1-1-1 interleave 15ns 12ns 15ns 12ns 20ns 4-1-1-1 non-interleave -4-2-2-2 interleave 15ns 15ns 20ns 20ns 20ns 4-2-2-2 non-interleave 15ns 15ns 20ns 20ns 20ns 4-3-3-3 interleave 15ns 20ns 20ns 20ns 20ns 4-3-3-3 non-interleave 15ns 20ns 20ns 20ns 20ns 5-1-1-1 interleave 20ns 12ns 20ns 12ns 20ns 5-1-1-1 non-interleave -5-2-2-2 interleave 20ns 15ns 20ns 20ns 20ns 5-2-2-2 non-interleave 20ns 15ns 20ns 20ns 20ns 5-3-3-3 interleave 20ns 20ns 20ns 20ns 20ns 5-3-3-3 non-interleave 20ns 20ns 20ns 20ns 20ns
Data 15ns -20ns 20ns 20ns 20ns 15ns -20ns 20ns 20ns 20ns 15ns -20ns 20ns 20ns 20ns
DRAM Controller
SiS85C501 supports 64-bit memory array ranging size from MBytes MBytes. Both single-sided double-sided 9/36-bit wide SIMM modules supported. DRAM controller 85C501 support banks SIMMS) single-sided SIMM module, banks SIMMs) double-sided SIMM module. 12-bit multiplexed row/column Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
address MA[11:0] allows PCMC support 256K, 70ns fast page mode DRAMs. Table shows corresponding request address bits used column address address DRAM. Table Generation Table Body 256K Type MA10 MA11
improve write DRAMs performance, there level built-in CPU-to-Memory posted write buffer with deep (CTMPB). single writes burst writes buffered. read miss/line fill cycle, write-back data from cache also buffered into CTMPB. same time, PCMC starts reading from DRAMs. buffered data written DRAMs when read cycle completes. With this concurrent write back policy, many wait states eliminated. However, other cycle targeting DRAMs will suspended until CTMPB empty. Typically, takes about CPUCLK complete read miss/line fill cycle 60/66 system, about CPUCLK system. Table outlines read write DRAM cycle performance based 70ns DRAMs. Table DRAM Performance Cycle type read (page hit/row miss/page miss)
posted write
write retire rate
66,60 7/11/14-4-4-4 8/12/15-5-5-5 9/13/16-6-6-6 3/4/5-1-1-1 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5
50MHz 7/11/14-4-4-4 8/12/15-5-5-5 9/13/16-6-6-6 3/4/5-1-1-1 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Note: X-Y-Y-Y recommended setting. read cycles, CAS# precharge time Table DRAM speed setting based 70ns DRAM (apply read write cycle) register 66MHz 60MHz 50MHz read pulse width write pulse width precharge time precharge time delay time refresh active time DRAM write push delay
Arbiter
SiS85C501 contains high performance hidden arbitration scheme that allows efficient sharing among five Masters CPU. Note that master reserved PSIO chip. SiS85C501 employs priority rotation scheme that done different layers. first layer shared between PSIO four Masters group. second layer consists four masters with equal priority. Arbitration done both layers. winner arbitration among four masters arbitrates against PSIO. Fair rotation scheme applies only layer level. arbitration scheme assures that master channels (represented PSIO) access with minimal latency. PSIO given high level priority assure compatibility with traditional expansion boards that require short latency. This implementation together with Programmable Bursting Address Counter guarantees device will starved during master long bursting cycle. example, When maximum bursting length bytes, maximum arbitration latency PSIO, master about 12us, 40us respectively. following figures detail rotation arbitration structure corresponding timing diagram.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Rotation Arbitration Scheme:
GRANT PRIORITY
G0123
Notation: SW1: switch path from node G0123 GRANT PRIORITY SW2: switch path from node node G0123 SW3: switch path from node node SW4: switch path from node node G01, G23, G0123: intermediate nodes request from PSIO requests from device device device device respectively. Initial Path Parking: GRANT PRIORITY-G4 G0123-G01 G01-G0 G23-G2 Rule Rotating Priority Arbitration: GRANT PRIORITY will choose path whenever encounters optional path. will granted Daisy Chain Path switches will toggled from GRANT PRIORITY request node (G4, them have been utilized Example: Initial Priority:G4, G01, PSIO(G4) Request SIOGNT# asserted toggled G0123 (since been utilized) Priority change Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
PSIO, REQ3, REQ2, REQ1, REQ0 requesting GNT0# asserted SW1, toggled respectively (since they have been utilized) Priority change REQ3, REQ2, REQ1, REQ0 active GNT2# asserted SW2, toggled respectively (since they have been utilized) Priority change REQ3, REQ2, REQ1, REQ0 active GNT1# asserted SW2, toggled respectively (since they have been utilized) Priority change REQ3, REQ2, REQ1, REQ0 active GNT3# asserted SW2, toggled respectively (since they have been utilized) Priority change During there request comes from PSIO, Arbiter will grant PSIO.
Arbiter Rotation Arbitration scheme CPUCLK PCICLK REQ[3:0]# SIOREQ# GNT[3:0]# SIOGNT# HOLD CPUHOLD CPUHLDA HLDA FRAME# IRDY# 501arbi Note HOLD internal signal
master burst long target source/sink data, other agent requests bus. However, specifies mechanisms that master's tenure presence other requests, that predictable acquisition latency achieved. Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Master Latency Timer(LT) that implemented into PCMC, other Target Initiated Termination. SiS85C501, Programmable Bursting Address Counter(PBAC) implemented disconnect master during long bursting cycle. this way, high throughput maintained, latency still kept reasonably small. Note that bursting length naturally applied master local memory accessing. When master accesses non-local memory target, master target should together have responsibility maintaining reasonable latency, system arbiter does. arbiter asserts only GNT# time. 85C501 also implemented timeout counter prevent faulty device hugging bus. granted device currently idle, clocks limitation that device should assert FRAME# during period time. time-out occurs, arbiter will mask request line, therefore desserts GNT#. When this happens, devices start arbitration again. Note that PSIO free this constraint. 85C501 master will also mask PSIO request arbiter LOCK# asserted keep master channels target latency within specification. 85C501 arbiter also allowed force system back each time after SIOREQ# serviced. This function disabled default, enabled register PCMC Configuration space.
Bridge
2.8.1 Master Controller Master Controller forwards cycles targeting local memory bus. case 64-bit request misaligned 32-bit request, PCMC assumes read assembly write disassembly control. level posted write buffer (CTPPB) implemented improve memory write performance. Except on-board memory write cycles, cycles forwarded will suspended until CTPPB empty. memory write cycles, data pushed into CTPPB full. pushed data are, later time, written bus. consecutive written data incremental sequence, they will transferred burst manner. burst transfer rate always X-2-2-2-. until exhausted. master interface read data from write data utmost speed wait state. This fact that PCMC drives address PLDB drives data. That necessitates turn around cycle between address data phases. PCMC provides mechanism converting standard cycles Configuration cycles bus. Configuration Mechanism Specification page used cycle conversion. PCMC always intercepts first interrupt acknowledge cycle from bus, forwards second interrupt acknowledge cycle onto bus.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
2.8.2 Slave Controller SiS85C501 operates slave whenever master requests access SiS85C501 resource such Cache, DRAM SiS85C501 Internal registers. Note that internal registers only accessed SiS85C501 itself when cycle. SiS85C500 PCI/ISA system, placed HOLD state before granting master. following figure shows behavior CPUHOLD/CPUHLDA response masters requests. Only linear ordered cycles supported PCMC slave interface.
CPUCLK PCICLK REQ# HOLD CPUHOLD CPUHLDA HLDA GNT# FRAME# IRDY# CIP# park Note HOLD,CIP# (current progress) internal signal drives master drives park
501req
master local memory access conducted until snoop cycle completed. snoop cycle used inquire first level cache maintain coherency between first level second level caches main memory. Snoop cycles performed driving master address onto asserting EADS#. Depending status HITM# clocks after assertion EADS#, PCMC conducts master cycles table outlines.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Table Master Read Cycle Miss Unmodified) Miss Unmodified) HitM
Miss (Dirty !Dirty) Miss
HitM
(Dirty !Dirty)
Data Transfer Data transfer from DRAM Data transfer from Data first written back from DRAM. Then, master gets data from DRAM. Data first written back from Then, master gets data from line marked dirty Data Transfer Data transfer from DRAM Data transfer from DRAM Dirty changed. Data first written back from DRAM. Then, master writes data DRAM. Data first written back from Then, master writes data DRAM. Line marked dirty
Master write Cycle Miss Unmodified) Miss Miss Unmodified) (Dirty !Dirty) HitM Miss
HitM
(Dirty !Dirty)
snoop filter implemented prevent need multiple inquires same line line inquired previously. support snoop filter, Snoop Address Latch (SAL) Line Comparator implemented. line comparator used determine Address (NA) same content SAL. not, loaded into SAL, snoop cycle issued. addition, Valid association with used ensure snoop filtering effective only when HLDA asserted. simplified filter algorithm Write Back Mode NA=SAL master write cycle, PCMC only issues EADS#. does wait status HITM#. NA=SAL master read cycle, snoop cycle EADS# issued. NASAL master cycle, PCMC issues snoop cycle EADS#, then monitors status HITM#. During burst transaction, PCMC automatically generates snoop cycle when address advances across line. Write Through Mode following cases, PCMC only generates EADS#. ignores logic HITM#. NA=SAL master write cycle, During burst transaction, address advances across line. Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
SiS85C500, signal P54C should connected W/R# that driven SiS85C501 master cycle. this way, SiS85C501 invalidate line that currently inquired assertion EADS# master write cycles. PCMC slave interface supports burst transfers. burst transfer will disconnected (retry) transfer goes across bytes(or KBytes selected Register 5Dh, address boundary. This fact that address generator, support burst transfer, only address bytes. this way, most cache lines uninterruptedly transferred they state cache. Another reason constraint that page miss occur only once during entire bursting transaction since maximum bursting length always within page size used DRAM master writes buffered deep Memory posted write buffer (PTMPB). PCMC always packs aligned write data into write buffer, then retires into DRAM array cache. master write performance, utmost, X-2-2-2- master reads through read buffer with which burst transfers perform pace X-2-2-2-. (from cache), X-3-2-3-2-. (from DRAMs). Concurrent refresh will still performed when into Hold state. DRAM idle, refresh conducted time. refresh request occurs same time that master wants access DRAM, arbitration scheme employed resolve conflict. refresh request thus service while master accessing suspended until refresh cycle completed. Although refresh DRAM bus, most refresh cycle conducted each individual transaction, i.e. each Frame# initiating. other hand, refresh also deferred until DRAM idle. SiS85C500 system, refresh postponed more than worst case when master reading whole lines through burst transaction. 2.8.3 Speed Setting following settings apply system environment, even though system running 66MHz while running 33MHz.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Table setting latency from ADS# monitor local memory status CAS# pulse width master write cycle latency from disarming "full" assertion BRDY# pending write cycle latency from reading L2/DRAM assertion TRDY# master read cycles latency from packing Qword into PTMPB assertion CAS#(or KWE#) latency from TRDY# BRDY# read/write slave cycles Register Setting Unit CPUCLK PCICLK CPUCLK
PCICLK PCICLK CPUCLK
Green Function
following paragraphs Power Management Unit features description: 2.9.1 Power States provides different power management states, which described following sections. Monitor Standby State Monitor will blanked external devices turned through SMOUT when Monitor standby timer expires. Monitor Standby monitors following events: 1-15 HOLD Each sets mask bits, wake mask, other standby mask. HOLD includes local masters master request. Each event maskable. event happens during monitored period timer expires, generated monitor enters standby state. Once Monitor standby state, event from IRQ1-15, HOLD will cause which brings Monitor back normal state. time slot Monitor standby timer programmable 6.6sec, 0.84sec, 13.3ms, 1.6ms. (ii) System Standby State
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
system standby timer expires, generated system enter system standby state. following events happen: STPCLK# asserted stop clock hard disk drives spindle motors turned serial, parallel ports programmable port turned Once STPCLK# asserted, events from IRQ1-15, NMI, HOLD, INIT will cause STPCLK# de-asserted. Hard disk motors, serial, parallel programmable ports were turned off, they will back normal state only when they accessed. System Standby monitored events (each event maskable) Programmable ports (one 10-bit port, another a16-bit port) 1-15 (each sets mask bits Monitor Standby State) HOLD Hard Disk ports 1F0-1F7h, 3F6-3F7h, 170-17Fh, 320-32Fh) Serial ports 2F8-2FFh, 3F8-3FFh, 2E8-2EFh, 3E8-3EFh) Parallel ports 278-27Fh, 378-37Fh, 3BC-3BEh) A0000-AFFFFh B0000-BFFFFh Address trap (Video RAM) C0000-C7FFFh Address trap (Video BIOS) 3Bx-3Dxh (Video port) time slot System standby timer programmable sec, sec, 70ms, 8.85ms. (iii) Throttling state throttling state, STPCLK# asserted de-asserted periodically. This function maskable. throttling timer (Registers 62h) programmable time slot 35us. 2.9.2 Break Switch break switch pressed, will cause SMI. used wake standby state. Instead, used enter standby state. signal from break switch level trigger signal which lasts more than clocks. 2.9.3 Software software enable written Register 60h, SMI# generated software service routine invoked. Register should cleared handler.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset 2.10 Configuration Registers
PCMC contains sets registers: mapped registers configuration space mapped registers. 2.10.1 Mapped Registers SiS85C501 uses configuration space access mechanism This mechanism defines DWORD registers. first register(CF8h) references read/write register that named CONFIG_ADDRESS. second register (CFCh) references register named CONFIG_DATA. mechanism accessing configuration space write value into CONFIG_ADDRESS that specifies bus, device that bus, configuration register that device being accessed. read write CONFIG_DATA will then cause bridge translate that CONFIG_ADDRESS value requested configuration cycle bus. definition CONFIG_ADDRESS register described below: Register 0CF8h CONFIG_ADDRESS Register Device Function Register Number Reserved Number Number Number Enable ('1' enabled, disabled) Bits 30:24 Bits 23:16 Bits 15:11 Bits 10:8 Bits Bits enable flag determining accesses CONFIG_DATA should translated configuration cycles bus. Reserved, read only, must return when read. Choose specific system. Choose specific device bus. Choose specific function device. Choose DWORD device's configuration space. read only must return when read.
full Dword writes 0CF8h address will load CONFIG_ADDRESS register Also, full DWord Read 0CF8h gets data from CONFIG_ADDRESS register Writes Reads other length other than DWORD passed cycles. When SiS85C501 sees access that falls inside Dword beginning CONFIG_DATA address, checks enable CONFIG_ADDRESS register. cycle passed unchanged. cycle translated into configuration cycle.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Number field CONFIG_ADDRESS register zero, cycle translated into Type configuration cycle; Number field non-zero, cycle translated into Type configuration cycle. PCMC considered device Thus, configuration cycle device translated configuration cycle that responded PCMC assertion DEVSEL#. type configuration cycle indicated driving AD[1:0]=00 during address phase cycle. device number CONFIG_ADDRESS decoded ensures AD[31:11] driven high during address phase configuration cycle. instance, AD11 high when device number AD[31:12] lines used IDSEL signal target service. Never AD11 IDSEL line other target device since reserved PCMC. CONFIG_ADDRESS copied directly AD[10:2]. type configuration cycle translated driving AD[1:0]=01 during address phase cycle. CONFIG_ADDRESS bits copied directly AD[31:2] during address phase cycle. byte-enables data phase either types configuration cycle copied from HBE[7:4]#. following programming sequences example writing register PCMC reading register 5Ch, 5Dh, PCMC. write 51h: EAX, 80000050h 0CF8h, DATA 0CFDh, read 5Ch, 5Dh, 5Fh: EAX, 8000005Ch 0CF8h, 0CFCh Register 0CF9h Turbo Reset Control Register Bits Reserved INIT Enable When this ,the PCMC drives INIT during software reset. When this cleared PCMC drives CPURST during software reset, INIT inactive. BIST Enable. When this well enabled, subsequent initiation hard reset through this register enables Built
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Self Test(BIST) mode CPU. PCMC also drives INIT during hard reset. Reset CPU. There types resets CPU: hard reset using CPURST signal soft reset using INIT signal. this register transitions from PCMC initiates hard reset. hard reset through this register thus requires write operations this register: first write operation writes second write operation writes When this register transitions from PCMC initiates soft reset. sequence initiate soft reset through this register identical that hard reset except written first write operation. Enable System Hard Reset. When this transitions from PCMC initiates hard reset When this transitions from PCMC initiates soft reset CPU. Select Turbo /DeTurbo Mode. There ways enter Deturbo mode. through software; another hardware. Software Deturbo: Reg. Reg. 1,then Reg. CF9h Hardware Deturbo: Reg. Reg. then press deturbo switch. Vendor byte Vendor high byte Device byte Device high byte Command byte Reserved Respond parity. This always since PCMC does support parity checking
2.10.2 Configuration Space Mapped Registers Register Bits Register Bits Register Bits Register Bits Register
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Bits Reserved Enable special cycle. This always since PCMC does issue special cycle. Enable master. This always allowing PCMC serve master. Enable response memory access. Disables master's accesses local memory Enables master's accesses local memory Enable response access. This always since PCMC does respond cycles. PCMC only responds initiated cycles. Register Bits Register Bits Register Command high byte Reserved Status byte Reserved Status high byte Detected parity error. This always since PCMC does support parity checking bus. Signaled system error. This when PCMC asserts SERR#. This cleared writing Received master abort. This PCMC whenever terminates transaction with master abort. This cleared writing Received target abort. This when transaction terminated with target abort. This cleared writing Signaled target abort. This always since PCMC will terminate transaction with target abort.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Bits DEVSEL# Timing DEVT. bits define timing assert DEVSEL#. PCMC asserts DEVSEL# signal within three clocks after assertion FRAME#. default value DEVT=10. fact, PCMC always asserts DEVSEL# medium timing except writes port 60h. Reserved Revision Identification. 00h.
Register Bits
Register 0B~09h Class Code Bits 23:0 060000h Register Bits DRAM Read Pulse Width Reserved DRAM Write Pulse Width DRAM configuration
SIMM 256K-S 256K-S 256K-S 512K-D 256K-S 256K-S 512K-D 512K-D 512K-D 512K-D 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S SIMM 256K-S 256K-S 256K-S 512K-D 256K-S 256K-S 512K-D 512K-D 512K-D 512K-D 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S SIMM3 256K-S 256K-S 1M-S 256K-S 256K-S 512K-D 2M-D 4M-S 1M-S 1M-S 2M-D 1M-S 1M-S 2M-D 4M-S 1M-S 4M-S SIMM 256K-S 256K-S 1M-S 256K-S 256K-S 512K-D 2M-D 4M-S 1M-S 1M-S 2M-D 1M-S 1M-S 2M-D 4M-S 1M-S 4M-S SIMM SIMM SIMM SIMM Total 12MB 12MB 20MB 36MB 20MB 36MB 16MB 24MB 24MB 32MB
Bits
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100
1M-S 1M-S 4M-S
1M-S 1M-S 4M-S 1M-S 1M-S
1M-S 1M-S 2M-D 1M-S 4M-S 4M-S
1M-S 1M-S 2M-D 1M-S 4M-S 4M-S 1M-S 1M-S
01101 01110 01111
40MB 48MB 72MB
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 1M-S 1M-S 1M-S 2M-D 2M-D 2M-D 2M-D 2M-D 4M-S 4M-S 4M-S 4M-S 4M-S 8M-D 8M-D 16M-S 1M-S 1M-S 1M-S 2M-D 2M-D 2M-D 2M-D 2M-D 4M-S 4M-S 4M-S 4M-S 4M-S 8M-D 8M-D 16M-S 8M-D 1M-S 1M-S 2M-D 4M-S 4M-S 8M-D 4M-S 4M-S 8M-D 4M-S 8M-D 8M-D 1M-S 1M-S 2M-D 4M-S 4M-S 8M-D 4M-S 4M-S 8M-D 4M-S 8M-D 4M-S 2M-D 4M-S 8M-D 4M-S 4M-S 72MB 80MB 16MB 32MB 48MB 80MB 80MB 32MB 64MB 96MB 96MB 128MB 64MB 128MB 128MB
4M-S
4M-S
4M-S 4M-S
4M-S 4M-S 4M-S 4M-S
Register Cache Exist Exist Exist Cache Enable Disable Enable SRAM type Standard Burst Standard SRAM Burst SRAM Cache WT/WB Policy Write-Through mode Write-Back mode Bits Cache Size 64KB 128KB 256KB 512KB Reserved
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Cache Write-Back Enable Disable Enable Register Bits Standard SRAM Cache speed (Read/Write) 5-x-x-x Slower 4-x-x-x Faster 3-x-x-x Fastest Reserved Bits Standard/Burst SRAM Setting (Burst Read/Write cycle Cache Interleave Enable Disable Enable Burst SRAM Cache Burst Cycle 4-x-x-x 3-x-x-x Cache Sizing Enable Normal Operation Always Cache enable Cache Sizing BIOS Refresh Active time Register DRAM precharge time Shadow Read Enable Disable
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Enable When this enabled, segment shadowed default. Before shadowing, BIOS should turn that reading segment always forwarded bus. Shadow Write Protection Enable Disable Enable After porting shadowed segment into DRAM, this that corresponding shadowed segment writable. Under such circumstances, cycle which intends write segment treated non-local memory cycle, forwarded bus. Shadow Enable Master Accesses Disable Enable F0000h FFFFFh Shadow Cacheable Non-Cacheable Cacheable Note that only code cacheable L2/L1 when this set. delay time precharge time Enable host CTMPB push rate X-1-1-1 Enable Disable. When this disabled, push rate defined [5:4] register 52h. Register Segment Setting E0000h E3FFFh Shadow Enable E4000h E7FFFh Shadow Enable E8000h EBFFFh Shadow Enable EC000h EFFFFh Shadow Enable Silicon Integrated Systems Corporation
Preliminary V2.0 January 1995
Pentium/P54C PCI/ISA Chipset
Register Register Register Allocation Non-cacheable Area Local DRAM Bus. local DRAM disabled. Non-cacheable Area Enable Disable Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation E0000h E3FFFh Shadow Cacheable E4000h E7FFFh Shadow Cacheable E8000h EBFFFh Shadow Cacheable EC000h EFFFFh Shadow Cacheable Segment Setting D0000h D3FFFh Shadow Enable D4000h D7FFFh Shadow Enable D8000h DBFFFh Shadow Enable DC000h DFFFFh Shadow Enable D0000h D3FFFh Shadow Cacheable D4000h D7FFFh Shadow Cacheable D8000h DBFFFh Shadow Cacheable DC000h DFFFFh Shadow Cacheable Segment Setting C0000h C3FFFh Shadow Enable C4000h C7FFFh Shadow Enable C8000h CBFFFh Shadow Enable CC000h CFFFFh Shadow Enable C0000h C3FFFh Shadow Cacheable C4000h C7FFFh Shadow Cacheable C8000h CBFFFh Shadow Cacheable CC000h CFFFFh Shadow Cacheable
Pentium/P54C PCI/ISA Chipset
Enable Bits Size Non-Cacheable Area (within MBytes) 64KB 128KB 256KB 512KB Bits Register Bits Register Allocation Non-cacheable Area Local DRAM Bus. local DRAM disabled. Non-cacheable Area Enable Disable Enable Bits Size Non-Cacheable Area (within 128MBytes) 64KB 128KB 256KB 512KB Bits Non-Cacheable Area (within 128MBytes) Non-Cacheable Area (within 128MBytes) Non-Cacheable Area (within 128MBytes)
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Register Bits Register Fast Gate Emulation Enable Disable Enable sequence generate A20M# write port followed write port with data 00h. When this enabled, SiS85C501 responds cycle asserting DEVSEL# slowest timing. Otherwise, cycle subtractively decoded 85C503, then passed 8042 bus. Fast Reset Emulation Enable Disable Enable Fast reset command write port with data 1111XXX0b. After command issued, assertion INIT CPURST delayed which programmed held CPUCLK. Fast Reset Latency Control Slow Refresh Enable (1:4) Normal Refresh Slow Refresh DRAM Write Push delay De-turbo Hold time Hold Hold (Every De-turbo Switch Enable Always turbo, ignore status De-turbo Switch De-turbo Switch Enable Driving Current Control Please refer Reg. details) Silicon Integrated Systems Corporation Non-Cacheable Area (within 128MBytes)
Preliminary V2.0 January 1995
Pentium/P54C PCI/ISA Chipset
Register Latency from ADS# Monitor Local Memory Status Depending setting this bit, master bridge SiS85C501 monitor local memory status from inside local memory decoder either initiates cycle, determined converted side from this point. Specifically, BRDY# always returned CPUCLK later CTPPB full, post memory write cycles. Thus, this also affects Post write speed. When Post write rate each double word. When rate double word. Qword memory write, post write rate 7T(bit7=1), 8T(bit7=0). Enable Refresh Cycle when hold Disable Enable Enable Snoop Filter Disable Enable CAS# Pulse Width master write cycle Latency from disarming "Full" assertion BRDY# pending write cycle Selection KWE# synchronization KWE# synchronized with ACLK (Recommended) KWE# synchronized with CPUCLK Length bits bits Memory Parity Enable/Disable Enable parity error detection (default value) Disable parity error detection Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Register Control Register Bits Clock Frequency Selection PCICLK=CPUCLK/2 PCICLK=CPUCLK/1.5 Reserved PCICLK=14MHz Maximum Burstable Address Range master cycles Bytes KBytes This defines maximum bursting length each FRAME# asserting. Latency from Reading L2/DRAM assertion TRDY# master read cycles Latency from Packing Qword into PTMPB assertion CAS#(or KWE#) This latency reserved Post write data propagating onto bus, also parity generation that minimum time data CAS# will violated. Latency from TRDY# BRDY# read/write slave cycles CPUCLKs CPUCLKs CPU-to-PCI burst memory write Enable Disable Enable CPU-to-PCI post memory write Enable Disable Enable
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Register This register mainly defines enable bits events monitored System Standby timer. monitored event occurs during programmed time, System standby timer will reloaded starts count down again. Programmable 10-bit port When set, access address will cause timer reloaded. address defined Registers 67h. Programmable 16-bit port When set, access address will cause timer reloaded. address defined Registers 6Eh. Hard Disk port When set, access Hard Disk ports 1F0-1F7h 3F6h) will cause timer reloaded. Serial port When set, access Serial Ports 2F8-2FFh, 3F8-3FFh, 2E8-2EFh 3E8-3EFh) will cause timer reloaded. Parallel port When set, access Parallel ports 278-27Fh, 378-37Fh 3BC3BEh) will cause timer reloaded. HOLD When set, event from master Local Master will cause timer reloaded. IRQ1-15, When set, event from IRQ1-15 will cause timer reloaded. Driving Current Control Register used control driving current. Register Register Minimum Current (default) 12mA Define events monitored Monitor standby timer Define events break Monitor System standby state. 1-15, Silicon Integrated Systems Corporation
Register Bits Bits
Preliminary V2.0 January 1995
Pentium/P54C PCI/ISA Chipset
When set, event from IRQ1-15 will cause Monitor standby timer reloaded. HOLD When set, event from master local master will cause Monitor standby timer reloaded. 1-15, When enabled, event from IRQ1-15 will bring Monitor back Normal state from Standby state. HOLD When enabled, event from master local master will bring Monitor back Normal state from Standby state. 1-15, When enabled, event from IRQ1-15 will de-assert STPCLK#. HOLD When enabled, event from master local master will deassert STPCLK#. INIT When enabled, event from INIT will de-assert STPCLK#. Register Reserved. should written with Reserved. should written with STPCLK# Enable When set, writing Register will cause STPCLK# become active. This cleared. Throttling Enable When set, writing Register will cause STPCLK# throttling state become active. throttling function disabled clearing this bit. STPCLK# Control When this set, STPCLK# will asserted Throttling function will enabled depending bits both bits enabled, system will throttling function. Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation Reserved (must '0')
Pentium/P54C PCI/ISA Chipset
Break Switch Enable When set, break switch used force system enter Standby state. When Register enabled, written this bit, generated. used software controlled function like APM. This should cleared handler. Register Bits Bits define period STPCLK# assertion time when STPCLK# enable set. timer will start count until Stop Grant Special Cycle received. timer slot Reserved. STPCLK# Assertion Timer
Register Bits
STPCLK# De-assertion Timer
Bits define period STPCLK# de-assertion time when STPCLK# enable set. timer starts count when STPCLK# assertion timer expires. When these registers read, current values returned.
Register Bits
System Standby Timer register defines duration System Standby Timer. When System Standby Timer expires, system enters System Standby State. non-masked event occurs before timer expires, timer reloaded with programmed number timer starts counting down again.
Register Bits
SMRAM mapping address. Correspond Host address A[27:20]. This register together with register define SMRAM location. SMRAM location either non-shadow, non-cacheable location selecting segment defined register implemented through logical address remap scheme. Logical address remap done through comparing upper bits access address with address bits defined register 65h. addresses compared equal SRAM area selection been either
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
segment, then access remapped into segment access. SMRAM mapping address should BIOS during POST process service routine also moved into SMRAM area during this process. When system mode SMRAM access control enabled, access SMRAM area will redirected defined these registers. Note: SMRAM mapping address defines granularity logical address must first memory area. Register Bits SMRAM area selection E0000h-E7FFFh A0000h-A7FFFh A0000h-AFFFFh B0000h-B7FFFh B0000h-BFFFFh others reserved SMRAM area non-cacheable, non-shadowed. E0000h-E7FFFh physical logical address space. other selections used relocate SMRAM from pre-defined area defined registers 65h) during SMM. SMRAM access control When set, SMRAM area used. This whenever necessary access SMRAM area. cleared after access finished. SMRAM area only accessed during handler. FLUSH# (De-turbo mode), ADSC# selection (pin ADSC# FLUSH# (De-turbo mode) Bits Register Bits Reserved (must '0') Define time slot Monitor Standby timer seconds 0.84 seconds 13.3 milli-seconds milli-seconds Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation Bits correspond Host Address A[30:28].
Pentium/P54C PCI/ISA Chipset
Bits Programmable 10-bit port address mask bits mask masked A1-A0 masked A2-A0 masked A3-A0 masked A4-A0 masked A5-A0 masked A6-A0 masked Bits Programmable 10-bit port address bits Bits correspond address bits Register Bits Bits define programmable 10-bit port address bits A[9:2]. Register This register defines enable status devices SMM. bits when devices standby state cleared when respective devices normal state. System Standby enable When non-masked event occurs during programmed duration system standby timer, timer expires. this enabled, SMI# generated system enters System Standby state. Programmable 10-bit port wake enable When set, access this port will monitored generate SMI# wake this port from standby state Normal state. This enabled only when port Standby state. Programmable 16-bit port wake enable When set, access this port will monitored generate SMI# wake this port from standby state Normal state. This enabled only when port Standby state.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Serial ports wake enable When set, access serial ports will monitored generate SMI# wake serial ports from standby state Normal state. This enabled only when serial ports Standby state. Parallel ports wake enable When set, access parallel ports will monitored generate SMI# wake parallel ports from standby state Normal state. This enabled only when parallel ports Standby state. Hard Disk port enable When set, access hard disk port will monitored generate SMI# wake hard disk from standby state Normal state. This enabled only when hard disk port Standby state. Break Switch enable When set, break switch pressed generate SMI# system enter Standby state. Software enable When set, write register will generate SMI. Register This register defines request status. respective enable set, each specific event will cause respective set. asserted should cleared handler. System standby request This when system standby timer expires. Programmable 10-bit port wake request This when there access port. Programmable 16-bit port wake request This when there access port. Serial ports wake request This when serial ports accessed. Parallel ports wake request This when parallel ports accessed. Hard Disk port wake request This when hard disk port accessed. Break Switch request Silicon Integrated Systems Corporation
Preliminary V2.0 January 1995
Pentium/P54C PCI/ISA Chipset
This when break switch pressed. Software request This when write register 60h. Register Monitor Standby enable Disable Enable When there access from IRQ1-15, HOLD during programmed time Monitor Standby Timer, timer expires. this set, generated bring Monitor standby state. Monitor Standby request This when Monitor Standby Timer expires. This should cleared handler. Monitor wake enable When set, event from IRQ1-15, HOLD will monitored generate SMI# wake monitor from standby state normal state. Monitor wake request This when there event from IRQ1-15, HOLD NMI, Monitor standby state. Throttling wake request This when there unmasked event from NMI, INIT, IRQ1-15, HOLD when system throttling state. Throttling wake enable When set, unmasked event from NMI, INIT, IRQ1-15, HOLD will cause generated bring system back Normal state from throttling state. System wake enable When set, unmasked event from NMI, INIT, IRQ1-15, HOLD will cause generated bring system back Normal state from standby state.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
System wake request This when there unmasked event from NMI, INIT, IRQ1-15, HOLD when system standby state. Register Monitor Standby timer byte Bits Bits define byte Monitor standby timer. count-down timer time slot programmable 6.6s, 0.84s, 13.3 1.6ms. value programmed this register loaded when timer enabled timer starts counting down. timer reloaded when event from IRQ1-15, HOLD occurs before timer expires. When this register read, current value returned. Register Monitor Standby timer High byte Bits Bits define high byte Monitor standby timer.
Register Programmable 16-bit port byte Bits Bits define byte Programmable 16-bit port.
Register Programmable 16-bit port High byte Bits Register This register except mainly defines events monitored System Standby timer. unmasked event occurs before timer expires, System Standby Timer will reloaded timer starts count down again. Return after SIOREQ# Serviced Disable Enable SMOUT reserved application circuit. A0000h AFFFFh B0000 BFFFFh Address trap When set, memory access address range will cause timer reloaded. C0000h C7FFFh Address trap When set, memory access address range will cause timer reloaded. Bits define high byte Programmable 16-bit port.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
3B0-3BFh, 3C0-3CFh, 3D0-3DFh Address trap When set, access addresses will cause timer reloaded. Secondary Drive port When set, access secondary drive port (170-17Fh, 320-32Fh, 3F7h) will reload system standby timer. Bits System Standby Timer Slot 8.85 milli seconds milli seconds seconds seconds
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset 2.11 Assignment Description
2.11.1 Assignment
CALE KA3/KA4Y KA4X KWY1# KWY0# KWX1# KWX0# KREY#/COE1# KREX#/COE0# ADSV# ADSC#/FLUSH# VDD3 ALTWE# TAGWE# CAS0# CAS1# CAS2# CAS3# CPUCLK CAS4# CAS5# CAS6# CAS7# ACLK RAS0# RAS1# RAS2# RAS3# RAMW#
85C501
HA30 HA29 HA31 HA28 HA25 HA26 HA27 HA22 HA24 HA21 HA23 SMI# INIT STPCLK# VDD3 KBRST#/BREAK# TURBO AKEUP0 AKEUP1 SMOUT PCIRST# SIOREQ# SIOGNT# PCICLKI SERR# PLCOK# FRAME# IRDY# TRDY# DEVSEL# STOP# GNT3# GNT2# GNT1# GNT0# REQ3# REQ2# REQ1# REQ0# C/BE3# C/BE2# C/BE1# C/BE0# AD31 AD30
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
2.11.2 Listing means active low)
1=CALE 2=KA3/KA4Y 3=KA4X 4=KWY1# 5=KWY0# 6=VSS 7=KWX1# 8=KWX0# 9=KREY#/COE1# 10=KREX#/COE0# 11=VSS 12=ADSV# 13=ADSC#/FLUSH# 14=VDD3 15=TA0 16=TA1 17=TA2 18=TA3 19=TA4 20=TA5 21=TA6 22=TA7 23=ALTWE# 24=ALT 25=TAGWE# 26=CAS0# 27=CAS1# 28=CAS2# 29=CAS3# 30=CPUCLK 31=VSS 32=CAS4# 33=CAS5# 34=CAS6# 35=CAS7# 36=ACLK 37=VSS 38=RAS0# 39=RAS1# 40=VDD 41=RAS2# 42=RAS3# 43=VSS 44=RAMW# 45=MA0 46=MA1 47=MA2 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 48=MA3 49=MA4 50=MA5 51=MA6 52=MA7 53=MA8 54=MA9 55=MA10 56=MA11 57=HGDW 58=ADLE# 59=CPPOP 60=CPPSH 61=CMPOP 62=CMPSH 63=MDLE 64=PRDLE 65=ADOE 66=PARITY# 67=HCR0 68=VSS 69=HCR1 70=HLDA 71=PCICLKO 72=AD0 73=AD1 74=AD2 75=AD3 76=AD4 77=AD5 78=AD6 79=AD7 80=VDD 81=AD8 82=AD9 83=PWRGD 84=VSS 85=AD10 86=AD11 87=AD12 88=AD13 89=AD14 90=AD15 91=AD16 92=AD17 93=AD18 94=AD19 95=AD20 96=AD21 97=AD22 98=AD23 99=AD24 100=AD25 101=AD26 102=AD27 103=AD28 104=AD29 105=AD30 106=AD31 107=C/BE0# 108=C/BE1# 109=VSS 110=C/BE2# 111=C/BE3# 112=REQ0# 113=REQ1# 114=REQ2# 115=REQ3# 116=GNT0# 117=GNT1# 118=GNT2# 119=GNT3# 120=STOP# 121=DEVSEL# 122=TRDY# 123=IRDY# 124=FRAME# 125=PLOCK# 126=PAR 127=SERR# 128=VSS 129=PCICLKI 130=SIOGNT# 131=SIOREQ# 132=PCIRST# 133=SMOUT 134=WAKEUP1 135=WAKEUP0 136=VDD 137=TURBO 138=KBRST#/BREAK# 139=VSS 140=OSC 141=VDD3 5V/3.3V
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
142=STPCLK# 143=INIT 144=SMI# 145=HA23 146=HA21 147=HA24 148=HA22 149=HA27 150=HA26 151=HA25 152=HA28 153=HA31 154=HA29 155=HA30 156=HA3 157=HA4 158=HA6 159=HA7 160=HA8 161=HA10 162=HA5 163=HA11 164=HA9 165=HA12 166=HA13 167=HA14 168=HA15 169=HA16 170=HA17 171=HA18 172=HA19 173=HA20 174=CPURST 175=HBE7# 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 176=HBE6# 177=HBE5# 178=HBE4# 179=HBE3# 180=HBE2# 181=HBE1# 182=HBE0# 183=VSS 184=A20M# 185=W/R# 186=HITM# 187=EADS# 188=D/C# 189=ADS# 190=CPUHLDA 191=SMIACT# 192=CPUHOLD 193=NA# 194=BRDY# 195=VSS 196=KEN# 197=CACHE# 198=M/IO# 199=VDD3 200=KCE0#/CWE0# 201=KCE1#/CWE1# 202=KCE2#/CWE2# 203=KCE3#/CWE3# 204=VSS 205=KCE4#/CWE4# 206=KCE5#/CWE5# 207=KCE6#/CWE6# 208=KCE7#/CWE7# 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
2.11.3 Description Host Interface 145-173 Symbol HA[31:3] Type Function Address driven during cycles. 85C501 forwards either DRAM depending address range. address driven 85C501 during master cycles. Byte Enables indicate which byte lanes data carry valid data during current cycle. HBE7# indicates that most significant byte data valid while HBE0# indicates that least significant byte data valid. Address Status driven indicate start cycle. Memory definition input indicate cycle when low, memory cycle when high. Write/Read from indicates whether current cycle write read access. output during master cycles. Data/Code used indicate whether current cycle data code access. Burst Ready indicates that data presented valid during burst cycle. Hold Request used request control bus. CPUHLDA will asserted after completing current cycle. Hold Acknowledge comes from response CPUHOLD request. active high remains driven during hold period. CPUHLDA indicates that given another master. Modified indicates snoop cycle hits modified line cache CPU. Mask fast A20GATE output CPU. remains high during power reset period. forces when active.
175-182
HBE[7:0]#
ADS# M/IO#
W/R#
D/C# BRDY# CPUHOLD
CPUHLDA
HITM# A20M#
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
KEN# Cache Enable used when current cycle cacheable cache CPU. active signal asserted 85C501 during cacheable cycles. Cache indicates internally cacheable read cycle burst write-back cycle. this driven inactive during read cycle, will cache returned data, regardless state KEN# pin. EADS# driven indicate that valid external address been driven address pins used inquire cycle. Next Address driven clock indicate that memory system ready accept cycle. Although data transfer current cycle completed, drive internally pending cycle address clocks after asserted. Reset active high output reset CPU. Initialization output forces begin execution known state. state after INIT same state after CPURST except that internal caches, model specific registers, floating point registers retain values they prior INIT. System Management Interrupt used indicate occurrence system management events. connected directly SMI# input. SMIACT# used acknowledgment input from indicate that being acknowledged processor operating System Management Mode(SMM). Stop Clock indicates stop clock request CPU.
CACHE#
EADS#
CPURST INIT
SMI#
SMIACT#
STPCLK#
Cache DRAM Interface Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
22-15 Symbol TA[7:0] KA4X KA3/KA4Y KREX#/COE0# Type Function data lines. indicates particular line level cache contains modified data. Cache address even bank interleaved cache configuration. Cache address bank, Cache address non-interleaved mode. Cache Read Enable even bank standard SRAM, Cache Output Enable burst SRAM. Cache Read Enable bank standard SRAM, Cache Output Enable burst SRAM. When used COE1#, copy COE0# loading consideration. Cache Write Enable standard SRAM, even bank. Cache Write Enable standard SRAM, bank. ALTWE# write strobe RAM. This signal active when cache read miss cache write occurs. used update bit. write enable output. Cache Enable pins standard SRAM indicate that corresponding byte accessed. Cache Write Enable pins burst SRAM allow cache data update byte-by-byte basis. CALE controls external latch between host address lines cache address lines. When high, allows address lines propagate through external latches onto cache address lines. When low, used latch cache address lines. This that used ADSC#, FLUSH# depends BIOS programming. Cache Address Strobe Control causes burst SRAM latch cache address. FLUSH# asserted during deturbo mode. used force writeback modified lines data cache invalidate internal cache.
KREY#/COE1#
KWX0/1# KWY0/1# ALTWE#
208-205 203-200
TAGWE# KCE[7:0]# CWE[7:0]#
CALE
ADSC#/FLUSH#
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
ADSV# Cache Advance driven burst SRAM advance internal two-bit address counter next address burst sequence. RAS[3:0]# used latch address bus. Each RAS[3:0]# corresponds DRAM row. CAS[7:0]# used latch column address bus. Each CAS[7:0]# corresponds byte eight-byte wide array. Write active output signal enable local DRAM writes. MA[11:0] provide column address DRAM.
42,41 39,38 35-32 29-26
RAS[3:0]#
CAS[7:0]#
56-45 Interface 111,110 108,107
RAMW# MA[11:0]
Symbol C/BE[3:0]#
Type
106-85 82,81 79-72
AD[31:0]
Function Command Byte Enables define command during address phase cycle, byte enables during data phases. C/BE[3:0]# outputs when 85C501 master inputs when slave. Address /Data address phase: When 85C501 master, AD[31:0] output signals. When 85C501 target, AD[31:0] input signals. data phase: When 85C501 master memory read/write cycle, AD[31:0] floating. When 85C501 master configuration cycle, AD[31:0] input signals read cycle, output signals write cycle. When 85C501 target memory read/write cycle, AD[31:0] floating. When 85C501 target configuration cycle, AD[31:0] output signals read cycle, input signals write cycle.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
FRAME# FRAME# output when 85C501 master. 85C501 drives FRAME# indicate beginning duration access. When 85C501 slave, FRAME# input signal. IRDY# output when 85C501 master. assertion IRDY# indicates current master's ability complete current data phase transaction. read cycle, IRDY# indicates that master prepared accept read data following rising edge clock. write cycle, IRDY# indicates that master driven valid data bus. When 85C501 slave, IRDY# input. TRDY# output when 85C501 slave. assertion TRDY# indicates target agent's ability complete current data phase transaction. read cycle, TRDY# indicates that target driven valid data onto bus. write cycle, TRDY# indicates that target prepared accept data from bus. When 85C501 master, input. 85C501 drives DEVSEL# based DRAM address range being accessed master current configuration cycle 85C501. input indicates device responded current cycle initiated 85C501. STOP# indicates that master must start terminating current cycle next clock edge release control bus. STOP# used disconnect, retry, targetabort sequences bus. Parity even parity generated across AD[31:0] C/BE[3:0]#. System error open drain output reporting errors. Request used indicate arbiter that agent requires bus. Grant indicates agent that access been granted.
IRDY#
TRDY#
DEVSEL#
STOP#
115-112
SERR# REQ[3:0]#
119-116
GNT[3:0]#
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
PLOCK# Lock indicates exclusive operation that require multiple transactions complete. When PLOCK# sampled asserted beginning cycle, 85C501 considers itself locked resource remains locked state until PLOCK# sampled negated cycle. PCICLKO provides clock 85C501/502/503 devices system. PCICLKI input provides fundamental timing internal operating frequency 85C501. runs same frequency skew local bus. should generated from PCICLKO signal through clock distribution buffer. Reset forces devices known state.
PCICLKO PCICLKI
PCIRST#
Data Buffer Control Interface 69,67 Symbol HCR[1:0] Type Function Host Data Controls. These signals driven 85C501 used control 85C502 HD[63:0] bus. They defined floats drives FFFFFFFF drives data from drives data from Data Latch Enable. This signal following functions: Latch data into read buffer (PRMB) Latch data into read buffer rising edge PCICLKI. Latch data into posted write buffer (PTMPB) rising edge PCICLKI. Output Enable. This signal used enable 85C502 drive bus. asserted writes master reads local memory cycles. Memory Data Read Latch Enable. This signal latches data when negated.
ADLE#
ADOE
MDLE
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
CPPSH Push Posted Write Data into 85C502. data latched into 85C502 Posted Write Buffer CPPSH rising edge. edge also increases write pointer next available loading entry buffer. rising edge CPPOP, read pointer changed address next available reading location. When this signal asserted, data written into memory posted write buffer (CTMPB) rising edge CPUCLK, write pointer also changed address next available location. Memory Posted Write Buffer Data. When this signal asserted, read pointer Memory Posted Write Buffer increased rising edge CPUCLK. This signal latches current output entry Posted Write Buffer into prelatch 85C502. output prelatch driven onto bus. master cycle, PRDLE asserted when master reading data from secondary cache, when master writing data local memory. High Double Word Indicator. signal driven high when: high from written into Posted Write Buffer, reads high from bus, master writes high local memory, master reads high from local memory. Parity Bit, from 85C502.
CPPOP
CMPSH
CMPOP
PRDLE
HGDW
Others
PARITY#
Symbol HLDA SMOUT SIOREQ#
Type
Function Hold Acknowledge. System Management Output control pin. used control peripheral's power, clock.etc. Request from 85C503 request bus.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
SIOGNT# Grant. When asserted, SIOGNT# indicates that arbiter granted 85C503. When break switch enable set, KBRST# will disabled. signal from break switch will cause system enters standby state. pulse width BREAK# must greater than CPUCLK. Turbo input pin. system De-turbo mode when this low. When this input activated, 85C501 will reload system standby timer. inactive system standby timer expires, system will enter system standby state. During system standby state, this input becomes active, system will wake from standby state return back normal state. When this input activated, 85C501 will reload monitor standby timer. inactive monitor standby timer expires, system will enter monitor standby state. During monitor standby state, this input becomes active, system will wake from standby state return back normal state. clock input timer controller. 14.318MHz generated external oscillator. Advanced clock should lead CPUCLK provide clock 85C501 internal cache control logic. clock input runs frequency skew equal those clock. Power Good power reset push button reset input. power +3.3V power system power system Ground
KBRST#/BREA
TURBO WAKEUP1
WAKEUP0
ACLK
CPUCLK PWRGD
40,80,136 14,141 VDD3 6,11,31,37 43,68,84 109,128 139,183 195,204
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset 2.12 Timing Diagram
Cache Burst Read Cycle 3-1-1-1 CPUCLK ADS# BRDY# KA4X KA4Y KREX# KREY# 501cbr1 Cache Burst Read Cycle 4-2-2-2 CPUCLK ADS# BRDY# KA4X KA4Y KREX# KREY# 501cbr2 Cache Burst Read Cycle 5-3-3-3 CPUCLK ADS# BRDY# KA4X KA4Y KREX# KREY# 501cbr3
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Cache Burst Write Cycle 3-1-1-1 CPUCLK ADS# BRDY# KA4X KA4Y KWEX# KWEY# 501cbw1 Cache Burst Write Cycle 4-2-2-2 CPUCLK ADS# BRDY# KA4X KA4Y KWEX# KWEY# 501cbw2 Cache Burst Write Cycle 5-3-3-3 CPUCLK ADS# BRDY# KA4X KA4Y KWEX# KWEY# 501cbw3
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Cache Miss Update Cycle Only Dirty=0,Cache:4-2-2-2 DRAM:7-4-4-4 CPUCLK ADS# CAS# RAS# BRDY# MA[11:0] CALE KWEX# KWEY# KA4X KA4Y 501cmu1
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Cache Miss,Concurrent Write Back Cycle Cache:4-2-2-2 DRAM:7-4-4-4 CPUCLK ADS# CAS# RAS# BRDY# CMPSH MA[11:0] CMPOP CALE KWEX# KWEY# KA4X KA4Y RAMW# KREX# KREY# 501cmwb1
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
DRAM Burst Read Page Start 7-4-4-4 CPUCLK ADS# CAS# RAS# BRDY# MDLE MA[11:0] CALE KWEX# KA4X 501dbr1 DRAM Burst Read Page Start 8-5-5-5 CPUCLK ADS# CAS# RAS# BRDY# MDLE MA[11:0] CALE KWEX# KA4X 501DBR2
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
DRAM Burst Write CPUCLK ADS# CAS# RAS# BRDY# CMPSH MA[11:0] CMPOP KWEX# KA4X 501dbw1 85C501 Configuration Register Read Cycle CPUCLK HA[31:3] HBE[7:0]# ADS# BRDY# HGDW PCICLK FRAME# IRDY# DEVSEL# TRDY# PRDLE ADOE ADLE# 0CF8 0CFC
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
85C501 Configuration Register Write Cycle CPUCLK HA[31:3] HBE[7:0]# ADS# BRDY# HGDW PCICLK FRAME# IRDY# DEVSEL# TRDY# PRDLE ADOE ADLE# 501crw 0CF8 0CFC
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Read Slave CPUCLK HA[31:3] HBE[7:0]# ADS# BRDY# HGDW PCICLK AD[31:0] C/BE[3:0]# FRAME# IRDY# DEVSEL# TRDY# PRDLE ADLE# HCR[1:0] 501crp addr. data addr. data read read high
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Psoted Write Cycle CPUCLK HA[31:3] HBE[7:0]# ADS# BRDY# HGDW PCICLK AD[31:0] C/BE[3:0]# FRAME# IRDY# DEVSEL# TRDY# ADOE CPPSH CPPOP PRDLE 501ctpp master Reads High from L2,NA=SAL PCICLK FRAME# IRDY# DEVSEL# KRE# TRDY# HGDW ADOE ADLE# 501prl2 wait state XXX800 DATA XXXXX800 XXXXX808
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
master Writes L2/DRAM, NA=SAL, Page CPUCLK PCICLK FRAME# IRDY# DEVSEL# EADS# KWE#/CAS# TRDY# HGDW HCR[1:0] ADLE# CALE PRDLE RAMW# 501prl2d
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Snoop Modified line miss Master Writes Last Line Boundary, Disconnect CPUCLK PCICLK FRAME# IRDY# DEVSEL# TRDY# STOP# EADS# HITM# CPUHOLD CPUHLDA ADS# BRDY# RAS# CAS# RAMW# PRDLE ADLE# HGDW CALE
501snp2 address column addr
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Snoop Modified line Master Read Line from CPUCLK PCICLK FRAME# IRDY# DEVSEL# TRDY# EADS# HITM# CPUHOLD CPUHLDA HA[31:3] ADS# BRDY# KWE# KRE# ADOE PRDLE ADLE# HGDW
501snp1 00100000 drive 00100000 00100000 00100008 00100010 00100018
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset 2.13 Electrical Characteristics
2.13.1 Absolute Maximum Ratings Parameter Ambient operating temperature Storage temperature Input voltage Output voltage Power Dissipation -0.3 -0.5 Unit
Note: Stress above these listed cause permanent damage device. Functional operation this device should restricted conditions described under operating conditions. 2.13.2 Characteristics VDD=5V+5%, VDD3=3.3V+5% Symbol VIL1 VIH1 VIL2 VIH2 VT1VT1+ VOL1 VOH1 VOL2 VOH2 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 IOL5 Parameter Input voltage Input High Voltage Input voltage Input high voltage Schmitt Trigger Threshod Voltage Falling Edge Schmitt Trigger Threshold Voltage Rising Edge Hysteresis Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Current Output High Current Output Current Output High Current Output Current Output High Current Output Current Output High Current Output Current -0.3 -0.3 VDD3+0.3V VDD+0.3 Unit Condition Note VDD3=3.3V Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note
4,8,12 4,8,12 VDD3 0.45
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
IOH5 COUT CI/O ICC3 Output High Current Input Leakage Current Input Leakage Current Input Capacitance Output Capacitance Capacitance Power Supply Current VDD3 Note Note
Fc=1 Fc=1 Fc=1 3.3V, 66MHz
Note: VIL1 VIH1 apply following signals: HA[31:3], W/R#, HBE[7:0]#, HITM#, D/C#, ADS#, CPUHLDA, SMIACT#, CACHE#, M/IO# VIL2 VIH2 apply following signals: TA[7:0], ALT, CPUCLK, ACLK, PARITY#, AD[31:0], C/BE[3:0]#, REQ[3:0]#, STOP#, DEVSEL#, TRDY#, IRDY#, FRAME#, LOCK#, PCICLKI, SIOGNT#, SIOREQ#, WAKEUP[1:0], TURBO, KBRST#, VT1-,VT1+ apply PWRGD VOL1 VOH1 apply following signals: TA[7:0], ALTWE#, ALT, TAGWE#, CAS[7:0]#, RAS[3:0]#, RAMW#, MA[11:0], HGDW, ADLE#, CPPOP, CPPSH, CMPOP, CMPSH, MDLE, PRDLE, ADOE, HCR[1:0], HLDA, PCICLKO, AD[31:0], GNT[3:0]#, STOP#, DEVSEL#, TRDY#, FRAME#, PAR, SERR#, PCIRST#, SMOUT VOL2 VOH2 apply following signals: CALE, KA4Y, KA4X, KWY[1:0]#, KWX[1:0]#, KREX#, KREY#, ADSC#/FLUSH#, ADSV#, STPCLK#, INIT, SMI#, HA[31:3], CPURST, W/R#, A20M#, EADS#, CPUHOLD, NA#, BRDY#, KEN#, KCE[7:0]# IOL1 IOH1 apply following signals: TA[7:0], ALTWE#, ALT, TAGWE#, RAMW#, MA[11:0], HGDW, ADLE#, CPPOP, CPPSH, CMPOP, CMPSH, MDLE, PRDLE, ADOE, HCR[1:0], HLDA, PCICLKO, AD[31:0], C/BE[3:0]#, GNT[3:0]#, PAR, SERR#, PCIRST#, SMOUT, WAKEUP[1:0] IOL2 IOH2 apply following signals: FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#. IOL3 IOH3 apply following signals: CAS[7:0]# IOL4 IOH4 apply following signals: KA4X, KA4Y, KWY[1:0]#, KWX[1:0]#, ADSV#, ADSC#, RAS[3:0]# IOL5 IOH5 apply following signals: CALE, KREY#, KREX#, STPCLK#, INIT, SMI#, HA[31:3], W/R#, EADS#, CPUHOLD, NA#, BRDY#, KEN#, KCE[7:0]#, CPURST, A20M# IOH5 system, when system, IOH4 4mA. Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
2.13.3 Characteristics
Symbol Parameter BRDY# Active delay from CPUCLK BRDY# Inactive delay from CPUCLK KEN# Active delay from CPUCLK KEN# Inactive delay from CPUCLK Active delay from CPUCLK Inactive delay from CPUCLK EADS# Active delay from CPUCLK EADS# Inactive delay from CPUCLK CPUHOLD Active delay from CPUCLK CPUHOLD Inactive delay from CPUCLK CPURST Inactive delay from CPUCLK CPURST High Pulse Width KREX#,KREY# Active delay from ACLK KREX#,KREY# Inactive delay from ACLK KWX[0:1]#,KWY[0:1]# Active delay from ACLK KWX[0:1]#,KWY[0:1]# Inactive delay from ACLK KWX[0:1]#,KWY[0:1]# Active delay from CPUCLK KWX[0:1]#,KWY[0:1]# Inactive delay from CPUCLK KCE[7:0]# Active delay from ADS# falling edge KCE[7:0]# Inactive delay from CPUCLK MDLE High Active delay from CPUCLK MDLE High Inactive delay from CPUCLK KA4X,KA4Y Valid delay from ACLK KA4X,KA4Y High Valid delay from ACLK KA4X,KA4Y Valid delay from CPUCLK Update Cycle Write cycle KA4X,KA4Y High Valid delay from CPUCLK Update Cycle Write cycle Output Valid delay from CPUCLK Update Cycle RAS[3:0]# Active delay from CPUCLK RAS[3:0]# Inactive delay from CPUCLK CAS[7:0]# Active delay from CPUCLK CAS[7:0]# Inactive delay from CPUCLK MA[11:0] Valid delay from CPUCLK MA[11:0] High Valid delay from CPUCLK MA[11:0] Propagation delay from A[27:3] Output Valid delay from CPUCLK ALTWE#,TAGWE# Active delay from CPUCLK ALTWE#,TAGWE# Inactive delay from CPUCLK A20M# Active delay from CPUCLK A20M# Inactive delay from CPUCLK AD[31:0],C/BE[3:0]# Output valid delay from PCICLKI PRDLE Active delay from PCICLKI Active delay from PCICLKI Unit cpuclk 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 100pf 100pf 100pf 100pf 100pf 100pf 35pf 35pf 35pf 35pf 100pf 100pf 100pf 100pf 35pf 250pf 250pf 120pf 120pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 50pf 35pf 50pf
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Inactive delay from PCICLKI Active delay from PCICLKI Inactive delay from PCICLKI HA[31:3] Drive Output Valid delay from PCICLKI HCR[1:0],HGDW Active delay from CPUCLK HLDA Active delay from CPUCLK HLDA Inactive delay from CPUCLK INIT# Active delay from CPUCLK INIT# Inactive delay from CPUCLK MDLE Active delay from CPUCLK MDLE Inactive delay from CPUCLK PCICLKO,PCIRST Active delay from CPUCLK RAMW# Active delay from CPUCLK RAMW# Inactive delay from CPUCLK SMOUT Active delay from CPUCLK ADSC# Active delay from CPUCLK ADSC# Inactive delay from CPUCLK ADSV# Active delay from CPUCLK ADSV# Inactive delay from CPUCLK CPPSH Active delay from CPUCLK CPPOP Active delay from PCICLK CPPSH Inactive delay from CPUCLK CPPOP Inactive delay from PCICLK ADOE Active delay from PCICLK ADOE Inactive delay from PCICLK ADLE# Active delay from PCICLK ADLE# Inactive delay from PCICLK PCICLKO high time (Divided PCICLKO time (Divided PCICLKO high time (Divided 1.5) PCICLKO time (Divided 1.5) PCICLKO rise time (Divided PCICLKO fall time (Divided PCICLKO rise time (Divided 1.5) PCICLKO fall time (Divided 1.5) HCR[1:0] fall time CPUCLK rising HCR[1:0] rise time CPUCLK rising CALE# Active delay from CPUCLK CALE# Inactive delay from CPUCLK SMI# rise time CPUCLK rising SMI# fall time CPUCLK rising 15.2 12.6 12.5 15.8 1.16 0.66 1.06 50pf 50pf 50pf 50pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 50pf 35pf 35pf 50pf 90pf 90pf 150pf 150pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 50pf 50pf 50pf 50pf 50pf 50pf 50pf 50pf 35pf 35pf 35pf 35pf 35pf 35pf
CPUCLK SIGNAL1
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
T10, T11, T17, T22, T23, T25, T27, T28, T30, T32, T36, T38, T49, T50, T53, T55, T58, T60, T64, T78, T80, T18, T20, T21, T24, T26, T27, T29, T31, T33, T35, T37, T39, T47, T48, T51, T52, T54, T56, T57, T59, T61, T62, T79, T81, SIGNAL1 BRDY#, KEN#, NA#, EADS#, CPUHOLD, CPURST, KWX[0:1]#, KWY[0:1]#, KCE[7:0]#, MDLE, CALE, KA4X, KA4Y, TA[7:0], RAS[3:0]#, CAS[7:0]#, MA[11:0], ALT, ALTWE#, TAGWE#, A20M#, HLDA, INIT#, PCICLKO, PCIRST, RAMW#, SMOUT, ADSC#, ADSV#, GNT[3:0]#, PAR, SERR#, SIOGNT#, STPCLK#, CPPSH
ACLK SIGNAL2
T13, T15, T14, T16, SIGNAL2 KREX#, KREY#, KWX[0:1]#, KWY[0:1]#, KA4X, KA4Y
PCICLKI SIGNAL3
T40, T41,T42, T46, T44, T65, T67, T40, T41, T43, T46, T45, T63, T66, SIGNAL3 AD[31:0], C/BE[3:0], ADLE#, ADOE, PRDLE, DEVSEL#, FRAME#, IRDY#,STOP#, TRDY#, HA[31:3], CPPOP, ADOE, ADLE ADS# KCE[7:0]#
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
CPURST
HA[27:3]
MA[11:0]
PCICLKO
T70,T72 T71, T74, T75,
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
SiS85C502
Features
Supports Full 64-bit Pentium Processor Data Provides 64-Bit Interface DRAM Memory Provides 32-bit Interface Three Integrated Posted Write Buffers Read Buffers Increase System
Performance level CPU-to-Memory Posted Write Buffer (CTMPB) with QuadWords (QWs) Deep level CPU-to-PCI Posted Write Buffer (CTPPB) with DoubleWords (DWs) Deep level PCI-to-Memory Posted Write Buffer (PTMPB) with Deep level Memory-to-CPU Read Buffer (CRMB) with Deep level Memory-to-PCI Read Buffer (PRMB) with Deep Near Zero Wait State Performance CPU-to-Memory CPU-to-PCI writes Operates Synchronously 66.7 33.3 Clocks Provides Parity Generation Memory Writes 208-Pin PQFP CMOS Technology
General Description
SiS85C502 Local Data Buffer(PLDB) provides bi-directional data buffering among 64-bit Host Data Bus, 64-bit Memory Data Bus, 32-bit Address/Data Bus. PLDB incorporates three Posted Write Buffers Read Buffers along bridges CPU, Memory buses. This buffering scheme smoothes differences access latencies bandwidths among three buses, therefore improves overall system performance. four level/4DWs deep write buffer (CTPPB) provides buffering write bus. level/4QWs deep write buffer (CTMPB) used buffering write data from Memory. level/1QW deep write buffer (PTMPB) used buffer write Memory data. Read Buffer (CRMB) used latch read Memory data Read Buffer (PRMB) used latch data master read from Cache DRAM cycle. During operation between Host, Memory, PLDB receives control signals from PCMC, performs functions such latching data, forwarding data destination bus, data assemble disassemble. Figure shows PLDB block diagram.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
MDLE
MD[63:0]
CTMPB QWS)
PRDLE
PARITY# P.CK.
HD[63:0] PD[7:0]
P.G.
LATCH PTMPB
HCR[1:0]
LATCH DISASSEMBLE AD[31:0]
PRDLE
ADLE#
HGDW
DISASSEMBLE
CTPPB DWS)
HGDW PRDLE
(1DW)
Figure PLDB Block Diagram
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset Functional Description
3.3.1 Data Flow Between Data flows from when writes local memory PCMC writes back dirty line from cache local memory read miss/line fill cycle. data written memory first pushed into CPMPB. data then popped from buffer written Memory.
During read local memory cycle, data read first latched 64-bit read buffer (CRMB) order provide enough hold time cache. PLDB also checks parity read data.
3.3.2 Data Flow Between
This path used following cases. first case writes slave cycle. second case master read cycle that hits modified data local cache which implemented using write-back policy. data sent memory slave first pushed into CTPPB. data then popped onto later time when busy. further write suspended CTPPB full. writes posted, still exploit CTPPB write buffer.
path master read from cache implemented through PRMB, built-in 64-bit read memory buffer. Since read each time, PCMC always sustains wait state reading second This path exercised cases. first case during reads slave second case during master write cycles. reads cycle stalled until CTPPB empty. When reads slave, data latched assembled PTMPB before they transmitted bus. During master writes local memory, data first posted PTMPB. They then transferred local memory host master write also hits cacahe. 3.3.3 Data Flow Between
Write data from master buffered PTMPB before transferred local memory. Parity generated memory write data. masters receive data from local memory through this path. PRMB, 64-bit read Memory buffer implemented this path. read parity ignored inside PLDB.
Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
3.3.4 Address Flow Data Flow Basic Cycles Cycles CPU/R/PCI CPU/W/PCI CPU/R/ISA Address Flow HA501AD HA501AD HA501AD503 LA,SA CPU/W/ISA HA501AD503 LA,SA CPU/R/DRAM HA501MA CPU/W/DRAM HA501MA CPU/R/L2 Independent CPU/W/L2 Independent CPU/R/PCI(master abort) HA501AD PCI/R/L2 AD501HA PCI/W/L2 AD501HA PCI/R/DRAM AD501HA PCI/W/DRAM AD501HA ISA/R/L2 LA,SA503AD501 ISA/W/L2 LA,SA503AD501 DMA/R/L2 503AD501HA, LA,SA DMA/W/L2 503AD501HA, LA,SA ISA/R/DRAM LA,SA503AD501 ISA/W/DRAM LA,SA503AD501 DMA/R/DRAM 503AD501MA, LA,SA DMA/W/DRAM 503AD501MA, LA,SA Refresh 503SA Data Flow AD502HD HD502AD SD503AD502HD HD502AD503SD MD502HD HD502MD Independent Independent 502HD HD502AD AD502HD MD502AD AD502MD HD502AD503SD SD503AD502HD HD502AD503SD SD503AD502HD MD502AD503SD SD503AD502MD MD502AD503SD SD503AD502MD
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Assignment Description
3.4.1 Assignment
VDD3 MD63 MD62 MD61 MD60 MD59 MD58 MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32
85C502
HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 VDD3 CPURST RAMW# HGDW ADLE# CPPOP CPPSH CMPOP CMPSH MDLE PRDLE ADOE PARITY# HCR0 HCR1 HLDA CPUCLK AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
3.4.2 Listing means active low)
1=HD9 2=HD8 3=HD7 4=HD6 5=HD5 6=HD4 7=HD3 8=HD2 9=VSS 10=HD1 11=HD0 12=VDD3 13=MD63 14=MD62 15=MD61 16=MD60 17=MD59 18=MD58 19=MD57 20=MD56 21=MD55 22=VSS 23=MD54 24=MD53 25=MD52 26=VDD 27=MD51 28=VSS 29=MD50 30=MD49 31=MD48 32=MD47 33=MD46 34=MD45 35=MD44 36=MD43 37=MD42 38=MD41 39=MD40 40=MD39 41=MD38 42=MD37 43=MD36 44=MD35 45=VSS 46=MD34 47=MD33 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 48=MD32 49=PD7 50=PD6 51=PD5 52=PD4 53=MD31 54=MD30 55=MD29 56=MD28 57=MD27 58=MD26 59=VDD 60=MD25 61=MD24 62=MD23 63=VSS 64=MD22 65=MD21 66=MD20 67=MD19 68=MD18 69=MD17 70=MD16 71=MD15 72=MD14 73=MD13 74=MD12 75=MD11 76=MD10 77=MD9 78=MD8 79=MD7 80=VSS 81=MD6 82=MD5 83=MD4 84=MD3 85=MD2 86=MD1 87=MD0 88=PD3 89=PD2 90=VDD 91=PD1 92=PD0 93=AD31 94=AD30
95=AD29 96=AD28 97=AD27 98=PCICLK 99=VSS 100=AD26 101=AD25 102=AD24 103=AD23 104=AD22 105=AD21 106=AD21 107=AD19 108=AD18 109=AD17 110=AD16 111=AD15 112=AD14 113=AD13 114=AD12 115=AD11 116=VSS 117=AD10 118=AD9 119=AD8 120=AD7 121=AD6 122=AD5 123=AD4 124=VDD 125=AD3 126=AD2 127=AD1 128=AD0 129=VSS 130=CPUCLK 131=HLDA 132=HCR1 133=HCR0 134=PARITY# 135=ADOE 136=PRDLE 137=MDLE 138=CMPSH 139=CMPOP 140=CPPSH 141=CPPOP
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
142=ADLE# 143=HGDW 144=RAMW# 145=CPURST 146=VDD3 147=HD63 148=HD62 149=VSS 150=HD61 151=HD60 152=HD59 153=HD58 154=HD57 155=HD56 156=HD55 157=HD54 158=HD53 159=HD52 160=VSS 161=HD51 162=HD50 163=HD49 164=HD48 165=HD47 166=HD46 167=HD45 168=HD44 169=VDD3 170=HD43 171=HD42 172=VSS 173=HD41 174=HD40 175=HD39
5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V
176=HD38 177=HD37 178=HD36 179=HD35 180=HD34 181=HD33 182=HD32 183=VSS 184=HD31 185=HD30 186=HD29 187=HD28 188=HD27 189=HD26 190=HD25 191=HD24 192=HD23 193=HD22 194=VSS 195=HD21 196=HD20 197=HD19 198=VDD3 199=HD18 200=HD17 201=HD16 202=HD15 203=HD14 204=HD13 205=HD12 206=VSS 207=HD11 208=HD10
5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
3.4.3 Description 147,148 150-159 161-168 170,171 173-182 184-193 195-197 199-205 207,208 1-8,10,11 13-21,2325, 27,2944,46-48, 53-58 60-62,6479, 81-87 93-97, 100-115, 117-123 125-128 91,92,4952, 88,89 Symbol HD[63:0] Type Function data bus.
MD[63:0]
Memory data bus.
AD[31:0]
address/data bus.
PD[7:0] PARITY# ADOE
Parity bus. Parity Error signal. Drive bus. This signal used enable 85C502 drive bus. asserted writes master reads local memory cycles. Hold Acknowledge asserted response assertion CPUHLDA. Memory data Read Latch Enable. This signal latches data when negated. Data Latch Enable. This signal following functions: Latch data into read buffer (PRMB) Latch data into read buffer rising edge PCICLKI. Latch data into posted write buffer (PTMPB) rising edge PCICLKI.
HLDA MDLE ADLE#
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
CPPSH Push Post Write Data into CTPPB 85C502. data latched into CTPPB CPPSH rising edge. edge also increases write pointer next available loading entry buffer. rising edge CPPOP, read pointer changed address next available reading location. When this signal asserted, data written into memory posted write buffer (CTMPB) rising edge CPUCLK, write pointer also changed address next available location. When this signal asserted, read pointer CTMPB increased rising edge CPUCLK. This signal latches current output entry CTPPB, post write buffer, into prelatch 85C502. output prelatch driven bus. master cycles, PRDLE also asserted when master reading data from secondary cache, when master writing data local memory. High Double Word Indicator. signal driven high 85C501 when high from written into Posted Write Buffer, reads high from bus, master writes high local memory, master reads high from local memory. Host Data Control. These signals driven 85C501 they used control 85C502 HD[63:0] bus. They defined floats drives FFFFFFFF drives data from drives data from DRAM Write Enable. Reset. Clock. Clock. power
CPPOP
CMPSH
CMPOP
PRDLE
HGDW
132,133
HCR[1:0]
26,59,90,
RAMW# CPURST CPUCLK PCICLK
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
146, VDD3 169, 9,22,28,45 ,63,80,99, 116,129, 149,160 172,183, 194,206 +3.3V power system power system Ground
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset Electrical Characteristics
3.5.1 Absolute Maximum Ratings Parameter Ambient operating temperature Storage temperature Input voltage Output voltage Power Dissipation -0.3 -0.5 Unit
Note: Stress above these listed cause permanent damage device. Functional operation this device should restricted conditions described under operating conditions. 3.5.2 Characteristics VDD=5V+5%, VDD3=3.3V+5% Symbol VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 IOL1 IOH1 COUT CI/O ICC3 Parameter Input Voltage Input High Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Current Output High Current Input Leakage Current Input Leakage Current Input Capacitance Output Capacitance Capacitance Power Supply Current VDD3 -0.3 -0.3 VDD3 VDD3+0.3V VDD+0.3 0.45 Unit Condition Note VDD3=3.3V Note Note Note Note Note Note Note Note Note
Fc=1 Fc=1 Fc=1 3.3V, 66MHz
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Note: VIL1 VIH1 apply following signals: HD[63:0]. VIL2 VIH2 apply following signals: MD[63:0], AD[31:0], CPURST, PD[7:0], CPUCLK, ADOE, HLDA, HCR[1:0], PRDLE, MDLE, CMPSH, CMPOP, CPPSH, CPPOP, ADLE#, HGDW, RAMW#. VOL1 VOH1 apply following signals: MD[63:0], AD[31:0], PD[7:0], PARITY#. VOL2 VOH2 apply following signals: HD[31:0]. IOL1 IOH1 apply following signals: HD[63:0], MD[63:0], AD[31:0], PD[7:0], PARITY#. 3.5.3 Characteristics Symbol Parameter Data Setup Time MDLE falling Data Hold Time MDLE falling Data Valid Delay from data valid ADLE# Setup Time PCICLK rising ADLE# Hold Time PCICLK rising HGDW Setup Time PCICLK rising HGDW Hold Time PCICLK rising Data Setup Time PCICLK rising Data Hold Time PCICLK rising Data Valid Delay from PCICLK rising CMPSH Setup Time CPUCLK rising CMPSH Hold Time CPUCLK rising CMPOP Setup Time CPUCLK rising CMPOP Hold Time CPUCLK rising Data Setup Time CPPSH rising Data Hold Time CPPSH rising Data Valid Delay from CPUCLK rising Data Valid Delay from CPUCLK rising RAMW# Setup Time MDLE rising RAMW# Hold Time MDLE falling PARITY# Active Delay from MDLE falling Data Valid from PRDLE rising Data Valid from data valid HGDW Setup Time CPPSH rising HGDW Hold Time CPPSH rising Data Valid Delay from PCICLK rising Data Valid Delay from PCICLK rising Data Setup Time ADLE# falling Data Hold Time ADLE# falling 3.2, 3.2, 3.3,3.8 3.3,3.8 3.3,3.8 3.3,3.8 3.3,3.8 3.3,3.8 3.3,3.8 3.4,3.5 3.4,3.5 3.10
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Data Valid Delay from data valid Output Delay from RAMW# asserted Output Float Delay from RAMW# inactive Output Delay from ADOE asserted Output Float Delay from ADOE inactive Output Delay from asserted Output Float Delay from inactive 3.11 3.11 3.12 3.12 3.13 3.13 Unit
3.5.4 Timing Diagram MDLE
Figure Read DRAM Cycle PCICLK ADLE# HGDW
T5,T7 T4,T6
Figure Read Slave Cycle CPUCLK CMPSH CMPOP
T11,T13 T12,T14
Figure Write DRAM Cycle CPPSH HGDW
Figure Write Post Write Buffer
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
PRDLE
Figure Write Posted Data onto MDLE RAMW# PARITY#
Figure PARITY# Generation Reading DRAM Cycle PCICLK ADLE# HGDW
T5,T7 T4,T6
Figure Read Slave Cycle ADLE#
Figure Master Read Secondary Cache MDLE ADLE#
Figure 3.10 Master Read DRAM
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
RAMW#
Figure 3.11 Write DRAM Cycle
ADOE
Figure 3.12 Write Posted Data onto
Figure 3.13 Read DRAM Cycle
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
SiS85C503
Features
Integrated Bridge Between Translates Cycles into Cycles Translates Master Cycles into Cycles Provides PCI-to-ISA Memory DoubleWord Posted Write Buffer Integrated Compatible Logic Controller Arbiter Master, Devices, Refresh Built-in 8237 Compatible Controllers Built-in 8259A Compatible Interrupt Controllers Built-in 8254 Timer Supports Reroutibilty four Interrupts Unused Interrupt Supports Flash 160-Pin PQFP CMOS Technology
Functional Description
SiS85C503 highly integrated PCI/ISA system (PSIO) device that integrates necessary system control logic used PCI/ISA specific applications. SiS85C503 consists bridge that translates cycles onto bus, master/DMA device cycles onto bus; seven-channel programmable Controller, sixteen-level programmable interrupt controller, programmable timer with three counters. 4.2.1. Bridge SiS85C503 interface provides interface between PSIO bus. contains both master slave bridge bus. When SIOGNT# asserted, master bridge translates master cycles onto based decoding status from address decoder. When SIOGNT# negated, slave bridge accepts these cycles initiated targeted PSIO internal registers then forwards cycles Interface that further translates them onto Bus. address decoder provides information which slave bridge depends respond process cycle initiated Masters. Slave Bridge slave, PSIO responds both memory transfers. PSIO always targetterminates after first data phase bursting cycle.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
SiS85C503 always converts single interrupt acknowledge cycle (from 501) into cycles that internal 8259 pair respond PSIO assigned subtractive decoder PCI/ISA system accepting accesses positively decoded some other agent. reality, PSIO only subtractively responds memory accesses. PSIO also positively decodes addresses internal registers, BIOS memory space asserting DEVSEL# medium timing. Master Bridge long SIOGNT# asserted, master bridge behalf devices Masters starts drive bus, C/BE[3:0]# signal. When MRDC# MWTC# asserted, PSIO will generate FRAME#, IRDY# targeted memory side. valid address command driven during address phase, asserted clock after that phase. PSIO always activated FRAME# PCLKs because does conduct bursting cycle. address decoder used determine destination master devices. This decoder provides following options they defined configuration registers Memory: 0-512K Memory: 512K-640K Memory: 640K-768K(video buffer) Memory: 768K-896K eight sections(Expansion ROM) Memory: 896K-960K(lower BIOS area) Memory: 1M-XM-16M within which hole opened. Access hole forwarded bus. Memory:>16Mb automatically forwards PCI. 4.2.2 Controller SiS85C503 Interface accepts those cycles from interface then translates them onto bus. also requests master bridge generate cycle behalf master. interface thus contains standard Controller Data Buffering logic. provides control, such command generation, recovery control, wait-state insertion, data buffer steering. to/from address data bufferings also integrated SiS85C503. SiS85C503 directly support slots without external data address buffering. Standard refresh requested Counter then performed IBC. generates pertinent command refreshes address bus. Since refresh transparent cycle, arbiter employed resolve possible conflicts among cycles, refresh cycles, cycles. Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
4.2.3 Controller SiS85C503 contains seven-channel controller. channel 8-bit devices while channel 16-bit devices. channels also programmed four transfer modes, which include single, demand, block, cascade. Except cascade mode, each three active transfer modes perform three different types transfers, which include read, write, verify. address generation circuitry SiS85C503 only support 24-bit address devices. 4.2.4 Interrupt Controller SiS85C503 provides compatible interrupt controller that incorporates functionality 82C59 interrupt controllers. controllers cascaded that external internal interrupts supported. master interrupt controller provides IRQ<7:0> slave provides IRQ<15:8>. internal interrupt used internal functions only available externally. IRQ2 used cascade controllers together IRQ0 used system timer interrupt tied interval Counter remaining interrupt lines available external system interrupts. Priority 3-10 Label IRQ0 IRQ1 IRQ2 IRQ8# IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Controller Typical Interrupt Source Timer/Counter Keyboard Interrupt from Controller Real Time Clock Expansion Expansion Expansion Expansion Coprocessor Error Ferr# Fixed Disk Drive Controller Expansion Expansion Serial port Expansion Serial port Expansion Parallel Port Expansion Diskette Controller, Expansion Parallel Port, Expansion
addition features, ability interrupt sharing included. registers(ECLR) located 4D0h 4D1h defined allow edge level sense selection made individual channel channel basis instead complete bank channels. Note that default IRQ0, IRQ1, IRQ2, IRQ8# IRQ13 edge sensitive, programmed. Also, each Interrupt(INTx#) programmed independently route eleven compatible interrupts(IRQ<7:3>, IRQ<15:14>, IRQ<12:9>) through configuration registers 44h. Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
4.2.5 Timer/Counter SiS85C503 contains channel counter/timer that equivalent those found 82C54 programmable interval timer. counters division 14.31818MHz input clock source. outputs timers directed system functions. Counter connected interrupt controller IRQ0 provides system timer interrupt timeof-day, diskette time-out, other system timing function. Counter generates refreshrequest signal Counter generates tone speaker.
Functional Block Diagram
SD[15:8] SA[16:0] LA[23:17] IO16# M16# SBE# MR16# MRDC# MWTC# CHRDY IOCHK# BCLK BALE IORC# IOWC# SMRDC# SMWTC# ZWS# RTCALE RTCRD RTCWR REF# ROMKBCS# SDIR IGNNE# XD[7:0]
PCICLK PCIRST# AD[31:0] C/BE[3:0] FRAME# TRDY# IRDY# STOP# LOCK# DEVSEL# SERR# IDSEL A-D# SIOREQ# SIOGNT#
DATA
INTERFACE
BUFFER
DECODER
DECODER
INTERFACE
IRQ(15,14, 12:9,7:3,1) FERR# IRQ8# WAKEUP0 WAPEUP1
INTERRUPT
CONTROLLER
SPKR
TIMERs/COUNTERs
CONTROLLER
DRQ[7:5,3:0] DAK[2:0] DACKEN
Figure SiS85C503 Functional Block Diagram
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset Configuration Registers
Registers 00h, Vendor
Bits 15:0 1039h (Read Only) Registers 02h, Device
Bits 15:0 0008h (Read Only) Registers 04h, Bits 15:4 Command
Reserved. Read Monitor Special Cycle Enable Behave Master Enable Respond Memory Space Accesses Respond Space Accesses
Registers 06h, Status Bits 15:14 Reserved. Read Received Master-Abort When 85C503 generates master-abort, this This cleared writing this bit. Received Target-Abort When 85C503 receives target-abort, this Software clears this writing this location. Bits 10:9 Reserved. Read DEVSEL# Timing 85C503 always generates DEVSEL# with medium timing, these bits always Reserved. Read 0's.
Bits
Register Revision Bits (Read Only) Register 0B-09h Class Code Bits 23:0 060100h (Read Only) Register BIOS Control Register Reserved. Read
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
When MASTER retries, Arbiter deasserts SIOGNT#. This defaults Posted Write Buffer Enable default value (disabled). Bits [3:0] determine 85C503 responds segment, segment, extended segment (FFF80000-FFFDFFFF) accesses. 85C503 will positively respond extended segment access when set. combining with bits [3:2], enables 85C503 respond segment access. bits [3:2] Positive Decode Upper BYTE BIOS Enable. BIOS Subtractive Decode Enable. segment segment positively responds segment access. subtractively responds segment access. positively responds segment access. positively responds segment access. comment Reserved. Read
enabled set. Lower BIOS Enable. Register
Extended BIOS Enable. (FFF80000~FFFDFFFF) INTA# Remapping Control Register Remapping Control When enabled, INTA#, remapped compatible interrupt signal specified remapping table. This after reset. Enable Disable
Bits Bits
Reserved. Read 0's. IRQx Remapping table. Bits 0000 0001 0010 0011 IRQx# reserved reserved reserved IRQ3 Bits 0101 0110 0111 1000 IRQx# IRQ5 IRQ6 IRQ7 reserved Bits 1010 1011 1100 1101 IRQx# IRQ10 IRQ11 IRQ12 reserved Bits 1111 IRQx# IRQ15
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
0100 Register Bits Bits Register Bits Bits Register Bits Bits IRQ4 1001 IRQ9 1110 IRQ14
INTB# Remapping Control Register Remapping Control Reserved. Read 0's. Remapping table. INTC# Remapping Control Register Remapping Control Reserved. Read 0's. Remapping table. INTD# Remapping Control Register Remapping Control Reserved. Read 0's. Remapping table. Note: difference INT[A:D]# remapped same signal, this signal should level sensitive.
Register
Master/DMA Memory Cycle Control Register master memory access cycles will forwarded when address fall within programmable region defined bits[7:4]. base address programmable region 1Mbyte, addresses programmed 1MByte increments from 1MByte 16MByte. memory cycles will forwarded besides cycle fall within memory hole defined register 4Bh.
Bits Bits Memory MByte MByte MByte MByte MByte MByte MByte MByte Silicon Integrated Systems Corporation
Preliminary V2.0 January 1995
Pentium/P54C PCI/ISA Chipset
MByte MByte MByte MByte MByte MByte MByte MByte
master memory cycles following memory regions will forwarded they enabled. 896-960KByte Memory Region Disable Enable, cycle forwarded bus. 640-768KByte memory Region Disable Enable, cycle forwarded bus. 512-640KByte Memory Region Disable Enable cycle forwarded bus. 0-512KByte Memory Region Disable Enable cycle forwarded bus.
Register
Master/DMA Memory Cycle Control Register master memory cycles following memory regions will forwarded they enabled.
880-896K (DC000h-DFFFFh) Memory region Disable Enable
864-880K (D8000h-DBFFFh) Memory Region Disable
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Enable 848-864K (D4000h-D7FFFh) Memory Region Disable Enable 832-848K (D0000h-D3FFFh) Memory Region Disable Enable 816-832K (CC000h-CFFFFh) Memory Region Disable Enable 800-816K (C8000h-CBFFFh) Memory Region Disable Enable 784-800K (C4000h-C7FFFh) Memory Region Disable Enable 768-784K (C0000h-C3FFFh) Memory Region Disable Enable Register Master/DMA Memory Cycle Control Register Register register used define address hole. address hole located between 1Mbyte 16MByte, sized 64KByte increments. master memory cycles fall within this hole will forwarded bus. Register used define bottom address hole respectively. hole located between bottom address, bottom address must above 1MByte. bottom address greater than address, address hole disabled. Silicon Integrated Systems Corporation
Preliminary V2.0 January 1995
Pentium/P54C PCI/ISA Chipset
Register Master/DMA Memory Cycle Control Register This register used define address Address hole.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset Non-Configuration Registers
Registers These register accessed from bus. Address Attribute Register Name 0000h DMA1 Base Current Address Register 0001h DMA1 Base Current Count Register 0002h DMA1 Base Current Address Register 0003h DMA1 Base Current Count Register 0004h DMA1 Base Current Address Register 0005h DMA1 Base Current Count Register 0006h DMA1 Base Current Address Register 0007h DMA1 Base Current Count Register 0008h DMA1 Status(r) Command(w) Register 0009h DMA1 Request Register 000Ah DMA1 Write Single Mask 000Bh DMA1 Mode Register 000Ch DMA1 Clear Byte Pointer 000Dh DMA1 Master Clear 000Eh DMA1 Clear Mask Register 000Fh DMA1 Write Mask Bits(w) Mask Status Register(r) 00C0h DMA2 Base Current Address Register 00C2h DMA2 Base Current Count Register 00C4h DMA2 Base Current Address Register 00C6h DMA2 Base Current Count Register 00C8h DMA2 Base Current Address Register 00CAh DMA2 Base Current Count Register 00CCh DMA2 Base Current Address Register 00CEh DMA2 Base Current Count Register 00D0h DMA2 Status(r) Command(w) Register 00D2h DMA2 Request Register 00D4h DMA2 Write Single Mask Register 00D6h DMA2 Mode Register 00D8h DMA2 Clear Byte Pointer 00DAh DMA2 Master Clear 00DCh DMA2 Clear Mask Register 00DEh DMA2 Write Mask Bits(w) Mask Status Register(r) These registers accessed from bus. Address Attribute Register Name 0080h Reserved 0081h Channel Page Register 0082h Channel Page Register
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh Channel Page Register Reserved Reserved Reserved Channel Page Register Reserved Channel Page Register Channel Page Register Channel Page Register Reserved Reserved Reserved Refresh Page Register
Interrupt Controller Registers (These registers accessed from bus.) Address Attribute Register Name 0020h Base Address Register 0021h Mask Register 00A0h Base Address Register 00A1h Mask Register Timer Registers (These registers accessed from bus.) Address Attribute Register Name 0040h Interval Timer Counter 0041h Interval Timer Counter 0042h Interval Timer Counter 0043h Interval Timer Control Word Register Other Registers (These registers accessed from bus.) Address Attribute Register Name 0061h Status Register 0070h CMOS Address Mask Register 00F0h Coprocessor Error Register Register 4D0h Edge/Level Control Register IRQ7 edge sensitive level sensitive IRQ6 edge sensitive level sensitive IRQ5
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
edge sensitive level sensitive IRQ4 edge sensitive level sensitive IRQ3 edge sensitive level sensitive IRQ2 This must Raed IRQ1 This must Raed IRQ0 This must Raed After reset this register 00h. Register 4D1h Edge/Level Control Register IRQ15 edge sensitive level sensitive IRQ14 edge sensitive level sensitive IRQ13 This must Read IRQ12 edge sensitive level sensitive IRQ11 edge sensitive level sensitive IRQ10 edge sensitive Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
level sensitive IRQ9 edge sensitive level sensitive IRQ8 This must Raed zero. After reset this register 00h.
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset Internal Register
internal registers accessed through address/data registers pair. Address register located port written with index internal register. Then internal register content read written through data register port 23h. port read last written-in value. Register Bits clock selection 7.159MHz PCICLK/4 Bits PCICLK/3 Flash EPROM Control (Please refer Register details.) Reserved Flash EPROM Control Previous implementation flash EPROM support limits that EPROM flashed upon power till register added feature will allow EPROM flashed anytime. register added setting both will control EPROM flash operation. Register Register Operation EPROM flashed EPROM can't flashed again EPROM flashed whenever Relocatable Configuration Registers Control configuration registers relocatable through configuration register 80h. Upon power configuration registers located between index default. These index relocated programming register Slew Rate Control default value following signals 8mA(min), including SA[160], LA[23-17], SBHE#, MRDC#, MWTC#, SMRDC#, SMWTC#, IORC#, IOWC#. Besides, configuration register used program currents above signals 12mA(min) when 16-bit cycle command recovery time BUSCLK BUSCLK BUSCLK BUSCLK Bits 8-bit cycle command recovery time Silicon Integrated Systems Corporation
Register Bits
Preliminary V2.0 January 1995
Pentium/P54C PCI/ISA Chipset
BUSCLK BUSCLK BUSCLK BUSCLK Reserved 16-bit memory, wait state selection wait state wait state Reserved BIOS Register BIOS this register store data.
Bits Register Bits Register Bits Register Bits
same value port 70h.
corresponds mask bits IRQ7-1. When disabled, event from corresponding will cause system exit system standby state.
mask NMI. When disabled, event from will cause system exit system standby state.
Register Bits
corresponds mask bits IRQ8-15. When disabled, event from corresponding will cause system exit system standby state.
Register Bits corresponds mask bits IRQ7-1. When disabled, event from corresponding will cause system exit monitor standby state. mask NMI. When disabled, event from will cause system exit monitor standby state. Register Bits corresponds mask bits IRQ8-15. When disabled, event from corresponding will cause system exit monitor standby state.
Assignment Description
Preliminary V2.0 January 1995 Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
4.7.1 Assignment
SMWTC# SMRDC# MWTC# MRDC# MR16# SBHE# M16# IO16# ROMKBCS# IRQ8# RTCWR RTCRD RTCALE IGNEE# FERR# WAKEUP0 WAKEUP1 PCIRST# SIOREQ# SIOGNT# SERR# PLOCK# FRAME# IRDY# TRDY# DEVSEL# STOP# C/BE3# C/BE2# C/BE1# C/BE0#
85C503
SDIR# LA19 LA18 LA17 SD15 SD14 SD13 SD12 SD11 SD10 LA23 LA22 LA21 LA20 SA16 SA15 SA14 SA13 SA12 SA11 SA10
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
4.7.2 Listing means active low) 1=SMWTC# 2=SMRDC# 3=MWTC# 4=MRDC# 5=MR16# 6=SBHE# 7=M16# 8=IO16# 9=ROMKBCS# 10=IRQ8# 11=RTCWR 12=RTCRD 13=RTCALE 14=VDD 15=INT 16=IGNEE# 17=NMI 18=FERR# 19=VSS 20=WAKEUP0 21=WAKEUP1 22=OSC 23=VSS 24=PCIRST# 25=SIOREQ# 26=SIOGNT# 27=SERR# 28=PAR 29=PLOCK# 30=FRAME# 31=IRDY# 32=TRDY# 33=DEVSEL# 34=STOP# 35=C/BE3# 36=C/BE2# 37=C/BE1# 38=C/BE0# 39=AD0 40=AD1 41=AD2 42=AD3 43=VDD 44=AD4 45=AD5 46=AD6 47=AD7 48=AD8 49=AD9 50=AD10 51=AD11 52=AD12 53=AD13 54=AD14 55=AD15 56=AD16 57=AD17 58=AD18 59=AD19 60=AD20 61=AD21 62=AD22 63=AD23 64=AD24 65=AD25 66=AD26 67=AD27 68=VSS 69=PCICLK 70=AD28 71=AD29 72=AD30 73=AD31 74=INTD# 75=INTC# 76=INTB# 77=INTA# 78=IDSEL 79=SA0 80=SA1 81=SA2 82=SA3 83=SA4 84=SA5 85=VDD 86=SA6 87=SA7 88=SA8 89=SA9 90=SA10 91=SA11 92=SA12 93=SA13 94=VSS 95=SA14 96=SA15 97=SA16 98=LA20 99=LA21 100=LA22 101=LA23 102=VDD 103=SD8 104=SD9 105=VSS 106=SD10 107=SD11 108=SD12 109=SD13 110=SD14 111=SD15 112=LA17 113=LA18 114=LA19 115=VSS 116=SDIR# 117=XD0 118=XD1 119=XD2 120=XD3 121=XD4 122=XD5 123=XD6 124=XD7 125=EOP 126=SPKR 127=RFH# 128=ZWS# 129=BALE 130=IOCHK# 131=CHRDY 132=AEN 133=IOWC# 134=IORC# 135=VDD 136=BCLK 137=IRQ1 138=IRQ3 139=IRQ4 140=IRQ5 141=VSS 142=IRQ6 143=IRQ7 144=IRQ9 145=IRQ10 146=IRQ11 147=IRQ12 148=IRQ14 149=IRQ15 150=DACKEN 151=DAK2 152=DAK1 153=DAK0 154=DRQ0 155=DRQ1 156=DRQ2 157=DRQ3 158=DRQ5 159=DRQ6 160=DRQ7
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
4.7.3 Description Interface 35-38 Symbol C/BE[3:0]# Type Function Command Byte Enables define command during address phase cycle, byte enables during data phases. C/BE[3:0]# outputs when 85C503 master inputs when slave. Address data multiplexed AD[31:0]. During address phase transaction, AD[31:0] contains physical address. During data phase, AD[31:0] contains data. When 85C503 master, drives address AD[31:2] drives AD[1:0] during address phase. During data phase, drives data latches data AD[31:0] write read cycle respectively.When 85C503 target, AD[31:0] inputs during address phase. During data phases, 85C503 drives data AD[31:0] read cycle, latches data write cycle. FRAME# asserted indicate beginning transaction asserted until last data phase. When master ready complete final data phase, deasserts FRAME#. When 85C503 target, FRAME# input 85C503. 85C503 drives FRAME# when master. FRAME# tri-state during reset. When 85C503 master, drives IRDY# complete current data phase transaction. During write cycles, assertion IRDY# indicates 85C503 driven valid data AD[31:0]. During read cycles, indicates 85C503 ready latch data. IRDY# input 85C503 when 85C503 target output when 85C503 master.
73-70 67-44 42-39
AD[31:0]
FRAME#
IRDY#
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
TRDY# TRDY# output when 85C503 slave. assertion TRDY# indicates target agent's ability complete current data phase transaction. read cycle, TRDY# indicates that target driven valid data onto bus. write cycle, TRDY# indicates that target prepared accept data from bus. When 85C503 master, input. 85C503 asserts DEVSEL# when 85C503's configuration registers internal registers addressed. DEVSEL# also asserted when 85C503 subtractively decodes cycle. When 85C503 master, DEVSEL# input indicate target responded 85C503 initiated transaction. transactions, 85C503 also samples DEVSEL# decide subtractively decode cycle. When 85C503 target asserts STOP# request master stop current transaction. When 85C503 master, inputted STOP# causes 85C503 stop current transaction. even parity across AD[31:0] C/BE[3:0]# regardless whether lines carry meaningful information. Both address data phases generated. driven clock after corresponding address data. driven 85C503 during address phase 85C503 initiated transactions. During data phase, 85C503 also drives when 85C503 master write transaction. 85C503 target read transaction. System Error. SERR# pulsed active device that detects system error condition. Upon sampling SERR# active, 85C503 generates non-maskable interrupt CPU. Initialization Device Select. 85C503 samples IDSEL during address phase transaction. IDSEL sampled active, command configuration read write, 85C503 responds asserting DEVSEL# next clock.
DEVSEL#
STOP#
SERR#
IDSEL
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
PLOCK# PLOCK# always input 85C503. When 85C503 target transaction samples PLCOK# negated during address phase transaction, 85C503 considers itself locked resource until samples PLOCK# FRAME# negated. When other masters attempt accesses while 85C503 locked, 85C503 responds with target initiated retry termination. Clock. PCICLK provides timing transactions bus. other signals sampled rising edge PCICLK, timing parameters defined with respect this edge. Frequencies supported 85C503 include MHz. Reset. PCIRST# forces 85C503 known state. sustained tri-state signals forced high impedance state. registers their default values. PCIRST# asynchronous PCICLK when asserted negated. Although asynchronous, negation must clean, bounce-free edge. Note that PCIRST# must asserted more than 1us. Interrupt Interrupt
PCICLK
PCIRST#
77-74
INT[A:D]#
Preliminary V2.0 January 1995
Silicon Integrated Systems Corporation
Pentium/P54C PCI/ISA Chipset
Interface 97-95 93-86 84-79 101-98 114-112 124-117 111-106 104,103 SA[16:0] System address. They inputs when external master control outputs other times. Latched system address. They inputs when external master control outputs other times. Peripheral Data lines. System Data directly connected slots. 16-bit chip select indicates that cycle 16-bit transfer when asserted 8-bit transfer when negated. 16-bit memory chip select indicates 16-bit memory transfer when asserted 8-bit memory transfer when negated. Byte high enable signal indicates that high byte valid data 16-bit data bus. This signal output except during master cycles. Master* active signal from bus. When active, indicates that master control system. address control signals driv
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