Advanced Programmable Logic Device High Gate Utilization Flexible Inte

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Advanced Programmable Logic Device High Gate Utilization Flexible Inte

Datasheet Thumbnail

Top Searches for this datasheet

ATV5000/L
Advanced Programmable Logic Device High Gate Utilization Flexible Interconnect Architecture Universal Routing Flexible Logic Cells Flip-Flops Latches Multiple Flip-Flop Types Synchronous Asynchronous Registers High Speed Operation Complete Third Party Software Support Placement, Routing Layout Software Required Proven Reliable High Speed CMOS EPROM Process 2000 Protection Latchup Immunity Reprogrammable Tested 100% Programmability Commercial, Industrial Military Temperature Grades
Block Diagram
INPUT LATCHES
High Density Erasable Programmable Logic Device
INPUT PINS
UNIVERSAL REGIONAL INTERCONNECT
LOGIC CELLS (104 FLIP-FLOPS)
PINS
BURIED CELLS FLIP-FLOPS)
Description
Atmel V5000 easy use, high density programmable logic device. simple, regular architecture translates into increased utilization high performance. ATV5000 programmable combinatorial logic array. This guarantees easy interconnection uniform performance from nodes. "Sum terms", which easy groupings AND-OR gates, provide combinatorial logic blocks. terms wireOR'd together integrate larger logic blocks. expand levels logic, buried terms feed back into logic array. pins each driven register term. Each individually enabled input latch. registers configurable T-types without using extra logic gates. Individual terms, asynchronous presets, resets clocks give each flip-flop added flexibility. direct "clock from pin" option guarantees synchronization fast clock output performance. Standard, off-the-shelf third-party software tools programmers support ATV5000. This minimizes start-up investment improves product support.
JLCC
Chip Carrier Configuration
Name Pins 2,32,36,66 Pins 1,34,35,68 Function Logic Clock Inputs Input/Register Clocks Input/Latch Clocks Bidirectional Buffers Supply
I/Os I/Os I/Os
I/Os
I/Os
I/Os
I/Os
I/Os
I/Os I/Os
0065B
1-193
Absolute Maximum Ratings*
Temperature Under Bias.-55oC +125oC Storage Temperature.-65oC +150oC Voltage with Respect Ground.-2.0 +7.0 Voltage Input Pins with Respect Ground During Programming.-2.0 +14.0 Programming Voltage with Respect Ground.-2.0 +14.0 Integrated Erase Dose 7258 sec/cm2
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Note: Minimum voltage -0.6 which undershoot -2.0 pulses less than Maximum output voltage VCC+0.75 which overshoot +7.0 pulses less than
Functional Logic Diagram Description
There identical input/ouput logic cells identical buried logic cells ATV5000. Each cell flipflops, three terms, individual clock, reset, preset terms flip-flop, output enable term. Independent output configuration, flip-flops always usable, have least four product term inputs each. Each total) signal latched version drives logic array. There latch clock quadrant. ATV5000 four identical quadrants (see Figure universal routes true false signals from each pins four quadrants. Regional buses route each quadrant's flip-flop locally. eight input-only pins available four regional buses. Each logic cell number "regional" "universal" product terms (see Figure logic cells contain three terms, flip-flops, buffer. buried logic cells each contain flip-flop. addition, each buried logic cell term drive regional bus. This allows logic expansion. Serial register preload observability simplify testing. registers automatically clear power
Quadrant Functional Logic Diagram ATV5000
UNIVERSAL INPUTS UNIVERSAL PRODUCT TERMS REGIONAL PRODUCT TERMS REGIONAL INPUTS REGISTERCLOCKS INPUT PINS REGISTERCLOCKS UNIVERSAL PRODUCT TERMS REGIONAL PRODUCT TERMS REGIONAL INPUTS UNIVERSAL QUADRANTS BURIED LOGIC CELLS TOTAL PERQUADRANT)
INPUT/OUTPUT LOGIC CELLS TOTAL PERQUADRANT)
PINS
REGIONAL
Figure
D.C. A.C. Operating Range
ATV5000-25 Operating Temperature (Case) Power Supply Commercial
ATV5000/L-30 Industrial
ATV5000/L-35 Military 125oC
1-194
ATV5000/L
ATV5000/L
ATV5000 Block Diagram
REGISTER CLOCK LATCH CLOCK PINS 4-15,17 QUADRANT CELLS REGIONAL REGIONAL QUADRANT CELLS REGISTER CLOCK LATCH CLOCK PINS 52,53,55-65
REGISTER CLOCK LATCH CLOCK PINS 18,19,21-31
BURIED LOGIC CELLS
UNIVERSAL
BURIED LOGIC CELLS
REGISTER CLOCK LATCH CLOCK
CELLS
CELLS
PINS 38-49,51
BURIED LOGIC CELLS QUADRANT
BURIED LOGIC CELLS QUADRANT
REGIONAL
INPUT PINS 1,2,32,34,35, 36,66,68
REGIONAL
Figure
Quadrant Logic Diagram Description
ATV5000 has: four identical quadrants, identical input/ output logic cells, identical buried logic cells. universal routes true false signals from each pins four quadrants. Regional buses route each quadrant's flip-flop locally. eight input-only pins available every regional bus. Each logic cell number "regional" "universal" product terms (see Figure logic cells (Figures contain three terms, flip-flops, buffer. term five product terms universal three regional. terms each have four product terms universal three regional. Flip-flop global asynchronous preset, reset, clock product terms. Flip-flop universal asynchronous reset clock terms regional asynchronous preset term. There universal product term output enable. buried logic cells (Figure each contain flip-flop. term universal product term four regional product terms total five. flip-flop universal asynchronous preset, reset, clock terms. addition, each buried logic cell term back into regional instead flip-flop. This allows logic expansion. Regional product terms have inputs quadrant flip-flop outputs buried flip-flop inputs) eight dedicated input pins. Universal product terms have same inputs plus pins their complements.
Quadrant Clock Assignments
Quadrant Number Register Clock Latch Clock
Quadrant Structure
UNIVERSAL PRODUCT TERMS REGIONAL PRODUCT TERMS UNIVERSAL INPUTS REGIONAL INPUTS IN/LIN REGISTER CLOCK LATCH CLOCK
INPUT/ OUTPUT LOGIC CELLS TOTAL)
PINS
Q1/D1 BURIED LOGIC CELLS TOTAL) REGISTER CLOCK
UNIVERSAL QUADRANTS
REGIONAL
INPUT ONLY PINS
Figure 1-195
Logic Cell Options
ATV5000 logic cells contain most chip's logic options. standard logic cell contains flip-flops, three terms three array inputs. three terms combined provide term options four, five, nine, product terms. combinatorial signal output sent cell. ATV5000 retains ATV2500's ability bury both registers cell still output combinatorial signal (see Figure feature, unique ATV5000, ability output feedback combinatorial term directly (see Figure This high speed logic expansion term increases devices flexibility gate utilization.
Logic Cell with Buried Term Register Cell
D2/T2 CLOCK OPTION D1/T1 CELL
Buried Logic Cells
Each quadrant buried logic cells (see Figure Each cell contains term with five product terms, flip-flop, individual preset, clear, clock terms. configuration selects either output input feedback into regional bus.
Buried Logic Cells
SELECT CLOCK OPTION D1/T1
CLOCK OPTION
Figure
Flip-Flop Clock Options
Each register connected regional clock provide fast clock-to-output timing (see Figure this "synchronous" mode, clock four input pins, unique clock each chip quadrant. product term defines each flip-flop's clock "asynchronous" mode. "synchronous" mode, regional clock ANDed with product term. This provides fast timing synchronous clock with local control product term.
Figure
Clock Option
RCKn LOGIC CELL SELECT
CLOCK PRODUCT TERM
Figure
Logic
LOGIC CELL
Latches
Each ATV5000 input latch which individually enabled disabled (see Figure Each chip quadrant unique latch clock. When latch inactive, input flows directly into array. When activated, latch flow-through when clock signal low, data captured clock's rising edge.
SELECT
LCKn
FROM LOGIC CELL
Flip-Flop Types
Each flip-flop ATV5000 configured either D-type flip-flop. T-type flip-flop also easily configured into flip-flop.
Figure 1-196
ATV5000/L
ATV5000/L
Logic Cell, Buried Registers, Combinatorial Cell
CLOCK OPTION D2/T2 CELL CLOCK OPTION D1/T1 FROM CELL
Logic Cell with Combinable Terms, Register Cell
CLOCK OPTION D2/T2 D1/T1 CLOCK OPTION D1/T1 CELL FROM CELL
Figure
Figure
D.C. Characteristics
Symbol Parameter Input Load Current Output Leakage Current Power Supply Current ATV5000 Power Supply Current ATV5000L Clocked Power Supply Current, ATV5000L Only Output Short Circuit Current Input Voltage Input High Voltage Output Voltage Output High Voltage VIL, Com,Ind; Mil. -100 -4.0 VCC-0.3 Condition -0.1 VCC+1 VOUT -0.1 VCC+0.1 MAX, Outputs Open MAX, Outputs Open MHz, Outputs Open VOUT -0.6 Com. Ind.,Mil. Com. Ind.,Mil. Com. Ind.,Mil.
Units
ICC2
-120 VCC+0.75
Notes: more than output time should shorted. Duration short circuit test should exceed seconds. Frequency curve.
1-197
A.C. Waveforms Input Clock
INPUTS PINS
A.C. Waveforms Product Term Clock
INPUTS PINS
tSIS REGISTER CLOCK
tSIA REGISTER CLOCK TERM ASYNCHRONOUS RESET/PRESET
tARS ASYNCHRONOUS RESET/PRESET tCOS REGISTERED OUTPUTS tSFS INTERNAL FEEDBACKS tCFS VALID OUTPUT VALID OUTPUT VALID tAPF VALID
tARA tCOA OUTPUT VALID tSFA tCFA VALID OUTPUT VALID tAPF VALID
REGISTERED OUTPUTS
INTERNAL FEEDBACKS
Notes: Timing measurement reference Input driving levels unless otherwise specified.
Register A.C. Characteristics, Input Clock
ATV5000-25 Symbol Parameter tCOS tCFS tSIS tSFS FMAXS tARS
Note:
ATV5000/L-30
ATV5000/L-35
Units
Clock Output Clock Feedback Input Setup Time
Feedback Setup Time Hold Time Clock Width Clock Period
Maximum Frequency (1/tPS) Asynchronous Reset/Preset Recovery Time
Universal Product Terms.
Register A.C. Characteristics, Product Term Clock
ATV5000-25 Symbol tCOA tCFA tSIA tSFA FMAXA tARA
Note:
ATV5000/L-30
ATV5000/L-35
Parameter Clock Output Clock Feedback Input Setup Time
Units
Feedback Setup Time Hold Time Clock Width Clock Period
Maximum Frequency (1/tPA) Asynchronous Reset/Preset Recovery Time
Universal Product Terms.
1-198
ATV5000/L
ATV5000/L
A.C. Waveforms
INPUTS PINS INPUT LATCH CLOCK tER1 COMBINATORIAL OUTPUTS tPD1 REGISTERED tPD3 INTERNAL FEEDBACKS tPD2 VALID tPD4 tER2 VALID HIGH OUTPUT VALID OUTPUT VALID OUTPUT VALID tEA1 HIGH OUTPUT VALID
tEA2
Notes: Timing measurement reference Input driving levels unless otherwise specified.
A.C. Characteristics
ATV5000-25 Symbol tPD1 tPD2 tPD3 tPD4 tEA1 tER1 tEA2 tER2 FMAX tAPF
Note:
ATV5000/L-30
ATV5000/L-35
Parameter Input Non-Registered Output
Units
Feedback Non-Registered Output Input Non-Registered Feedback
Feedback Non-Registered Feedback Input Output Enable Input Output Disable Feedback Output Enable Feedback Output Disable Input Latch Setup Time Input Latch Hold Time Clock Width Clock Period Maximum Frequency (1/tP) Asynchronous Reset/Preset Width Asynchronous Reset/ Preset Registered Output Asynchronous Reset/ Preset Registered Feedback
Universal Product Terms.
Input Test Waveforms Measurement Levels
3.0V DRIVING LEVELS 0.0V 1.5V MEASUREMENT LEVEL
Output Test Load
5.0V (580 MIL.) (280 MIL.) OUTPUT 35pF
(10% 90%)
1-199
Preload Observability Registers
ATV5000's registers include circuity load unload them serially. This feature simplifies testing. state forced into registers control test sequencing, registers observed, independent being buried. level Data will force appropriate register high; will force low, independent polarity other configuration settings. preload/observe state entered placing 11-V 14-V signal JLCC. When clock (pin pulsed high, data (pin clocked serially through registers device, following table. register contents also clocked device FIFO fashion. observability only required, data should connected back data preload only required, (pin held high data (pin will remain high impedance. user contemplating register preload/obervability encouraged contact Atmel's applications department. Note: register clock terms pins must prior entering preload/observe state, prior leaving preload/observe state. must prior entering preload/observe state.
PRELOAD CLOCK Clock tWPP tWPP
Clock
Clock #128
DATA
tERP tEAP DATA tCOP
tDMIN tSPMIN tHPMIN tWPPMIN tPRMIN 1000 tERPMAX tEAPMAX tCOPMAX
Preload Observe Register Scan Order
Quadrant
Quadrant
DOUT (Quadrant (Quadrant (Quadrant
Quadrant (Quadrant Quadrant (Quadrant Quadrant (Quadrant
1-200
ATV5000/L
ATV5000/L
Power Reset
registers ATV5000 designed reset during power point delayed slightly from crossing registers will reset state. output state will depend polarity output buffer. This feature critical state machine initialization. However, asynchronous nature reset uncertainty actually rises system, following conditions required: rise must monotonic, After reset occurs, input feedback setup times must before driving clock term high, signals from which clock derived must remain stable during tPR. Parameter Description Power-Up Reset Time Units 1000
Design Flow Diagram
Using ATV5000
ATV5000's simple, regular architecture means that only simple logic compilers required configure device. layout route place required. These software tools readily available from companies such Data Corporation (ABEL), Logical Devices (CUPL), MINC Inc. (PLDesigner-XLTM), ISDATA (LOGiC). first step designing device complex ATV5000 partition your design into manageable blocks. These blocks then allocated proportionally each four quadrants ATV5000. Random gates described either with boolean equations behavioral description) with schematic editor. Truth table logic state machines best described behaviorially entered with text editor. design then combined into ASCII file, which then submitted logic compiler. Compilation, logic reduction, simulation, JEDEC file creation documentation then completed popular compilers. Assignment signals pins buried nodes well selecting various options ATV5000 (such register clocks input latches) done manually design data base file, automatic fitter used. logic fitter assigns pins nodes make best features ATV5000, frees designer from being required learn features complex device such ATV5000. further information fitters ATV5000, contact Atmel's applications department. After correcting syntax logic errors discovered compiler, JEDEC file ready download programmer. These available from number manufacturers. Programmed devices usually first tested programmer with your supplied test vectors. next step check your "custom chip" target system. When this hardware debug step complete, your system ready matter hours.
ABEL, CUPL, PLDesigner-XLand LOGiCmay trademarks others.
RANDOM
MACHINES
TRUTH
TEXT
(ASCII FILE)
TRANSFER JEDEC FILE PROGRAM
SHIP
1-201
ATV5000 PLCC/PGA Assignments
PLCC Name PLCC Name PLCC Name PLCC Name
Capacitance MHz, 25°C)
COUT
Note:
Units
Conditions VOUT
Typical values nominal supply voltage. This parameter only sampled 100% tested.
Security Fuse Usage
single fuse provided prevent unauthorized copying ATV5000 fuse patterns. Once programmed, outputs appear programmed during verify. security fuse should programmed last (after verifying other programmed bits), effect immediate. security fuse also inhibits preload observability.
Erasure Characteristics
entire memory array ATV5000 erased after exposure ultraviolet light wavelength 2537 Complete erasure assured after minimum minutes exposure using 12,000 µW/cm2 intensity lamps spaced inch away from chip. Minimum erase time lamps other intensity ratings calculated from minimum integrated erasure dose sec/cm2. prevent unintentional erasure, opaque label recommended cover clear window erasable which will subjected continuous fluorescent indoor lighting sunlight.
1-202
ATV5000/L
ATV5000/L
SUPPLY CURRENT INPUT FREQUENCY
ATV5000 25C,
INPUT FREQUENCY (MHz)
SUPPLY CURRENT INPUT FREQUENCY
ATV5000L 25C,
INPUT FREQUENCY (MHz)
1-203
Ordering Information
(ns) tCOS (ns) fMAX (MHz) Ordering Code ATV5000-25JC ATV5000-25KC ATV5000-25UC ATV5000-30JC ATV5000-30KC ATV5000-30UC ATV5000-30KI ATV5000-30UI ATV5000-30KM ATV5000-30UM ATV5000-30KM/883 ATV5000-30UM/883 ATV5000-35JC ATV5000-35KC ATV5000-35UC ATV5000-35KI ATV5000-35UI ATV5000-35KM ATV5000-35UM ATV5000-35KM/883 ATV5000-35UM/883 ATV5962-93248 ATV5962-93248 Package 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW Operation Range Commercial (0°C 70°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Military (-55°C 125°C) Military/883C Class Fully Compliant (-55°C 125°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Military (-55°C 125°C) Military/883C Class Fully Compliant (-55°C 125°C) Military/883C Class Fully Compliant (-55°C 125°C)
(ns)
tCOS (ns)
fMAX (MHz)
Ordering Code ATV5000L-30JC ATV5000L-30KC ATV5000L-30UC ATV5000L-35JC ATV5000L-35KC ATV5000L-35UC ATV5000L-35KI ATV5000L-35UI ATV5000L-35KM ATV5000L-35UM ATV5000L-35KM/883 ATV5000L-35UM/883
Package 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UK
Operation Range Commercial (0°C 70°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Military (-55°C 125°C) Military/883C Class Fully Compliant (-55°C 125°C) Military/883C Class Fully Compliant (-55°C 125°C)
ATV5962-93248 ATV5962-93248
1-204
ATV5000/L
ATV5000/L
Ordering Information
Package Type
68KW 68UW
Lead, Plastic J-Leaded Chip Carrier (PLCC) Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) Pin, Windowed, Ceramic Grid Array (PGA)
1-205

Advanced Programmable Logic Device High Gate Utilization Flexible Inte

Top Searches for this datasheet

Other recent searches