Synchronous Buck Linear Controller with 0.8V Reference Voltage Re

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Synchronous Buck Linear Controller with 0.8V Reference Voltage Re

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APW7068
Synchronous Buck Linear Controller with 0.8V Reference Voltage
Regulated Voltages REF_OUT Synchronous Buck Converter Linear Regulator REF_OUT 0.8V±1% with source current
General Description
APW7068 integrates synchronous buck PWM, linear controller, 0.8V Reference Voltage, well monitoring protection functions into single package. fixed 300KHz switching frequency synchronous controller drives dual N-channel MOSFETs, which provides controlled power output with over-voltage over-current protections. Linear controller drives external N-channel MOSFET with under-voltage protection. APW7068 provides excellent regulation output load variation. internal 0.8V temperaturecompensated reference voltage designed meet requirement output voltage applications. APW7068 with excellent protection functions: POR, OCP, UVP. Power-On Reset (POR) circuit monitor VCC12 supply voltage exceeds threshold voltage while controller running, built-in digital soft-start provides both outputs with controlled rising voltage. Over-Current Protection (OCP) monitors output current using voltage drop across lower MOSFET' RDS(ON), comparing with voltage OCSET pin. When output current reaches trip point, controller will
Single Power Supply Required Excellent Both Output Voltage Regulation 0.8V Internal Reference Over Line Voltage Temperature
Integrated Soft-Start Linear Outputs 300KHz Fixed Switching Frequency Voltage Mode Control Design 89%(Typ.) Duty Cycle Under-Voltage Protection Monitoring Linear Output Over-Voltage Protection Monitoring Output Over-Current Protection Output Sense Low-side MOSFET' RDS(ON) SOP-14, QSOP-16 QFN-16 packages Lead Free Available (RoHS Compliant)
Applications
Graphic Cards
shutdown directly, latch converter' output. Under-Voltage Protection (UVP) monitors voltage short-circuit protection. When VFBL less than VREF, controller will shutdown directly. Over-Voltage Protection (OVP) monitors voltage When over 135% REF, controller will make Lowside gate signal fully turn until fault events removed.
ANPEC reserves right make changes improve reliability manufacturability without notice, advise customers obtain latest version relevant information verify before placing orders. Copyright ANPEC Electronics Corp. Rev. Jun., 2006 www.anpec.com.tw
APW7068
Pinouts
FS_DIS UGATE PHASE Metal (Bottom) AGND DGND VCC12 VCC12 BOOT
BOOT FS_DIS COMP DRIVE UGATE PHASE PGND LGATE OCSET REF_OUT VCC12 BOOT FS_DIS COMP DRIVE SOP-14 VIEW UGATE PHASE PGND LGATE OCSET REF_OUT VCC12 VCC12 DRIVE COMP
PGND LGATE OCSET REF_OUT
QSOP-16 VIEW
QFN-16 VIEW
Ordering Marking Information
APW7068 Lead Free Code Handling Code Temp. Range Package Code APW7068 APW7068 APW7068 XXXXX APW7068 XXXXX APW7068 XXXXX Package Code QSOP Temp. Range Handling Code Tube Tape Reel Tray (for only) Lead Free Code Lead Free Device Blank Original Device XXXXX Date Code XXXXX Date Code
APW7068
XXXXX Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials 100% matte plate termination finish; which fully compliant with RoHS compatible with both SnPb lead-free soldering operations. ANPEC lead-free products meet exceed lead-free requirements IPC/JEDEC STD-020C classification lead-free peak reflow temperature.
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
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APW7068
Block Diagram
VCC12 OCSET IOCSET 40uA REF_OUT Reference Buffer Regulator Power-On Reset BOOT
VREF (0.8V) 135%VREF X1.35 Soft Start Fault Logic
O.C.P Comparator
UGATE
O.V.P Comparator
PHASE
Sense Side
Gate Control
LGATE
Error
PGND Comparator U.V.P Comparator 50%VREF
VREF Oscillator Sawtooth Wave (300KHz) VREF Error
DRIVE
COMP
FS_DIS
Absolute Maximum Ratings
Symbol VCC12 BOOT UGATE LGATE PHASE DRIVE VCC12 BOOT PHASE UGATE PHASE LGATE PGND PHASE DRIVE <400ns pulse width >400ns pulse width <400ns pulse width >400ns pulse width <400ns pulse width >400ns pulse width Parameter Rating -0.3 -0.3 BOOT+5 -0.3 BOOT+0.3 VCC12+5 -0.3 VCC12+0.3 -0.3 -0.3 Unit
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FBL, COMP, FBL, COMP, FS_DIS FS_DIS
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
APW7068
Absolute Maximum Ratings (Cont.)
Symbol PGND TSTG TSDR VESD PGND Junction Temperature Range Storage Temperature Soldering Temperature Seconds) Minimum Rating Parameter Rating -0.3 +0.3 +150 Unit
NOTE1: Absolute Maximum Ratings those values beyond which life device impaired. Exposure absolute maximum rating conditions extended periods affect device reliability. NOTE2: device sensitive. Handling precautions recommended.
Recommended Operating Conditions
Symbol VCC12 VIN1 VOUT1 IOUT1 IOUT2 Supply Voltage Converter Input Voltage Converter Output Voltage Converter Output Current Linear Output Current Ambient Temperature Range Junction Temperature Range Parameter Rating 10.8 13.2 13.2 Unit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC12=12V, =-20~70°C. Typical values TA=25°C.
Symbol
Parameter
Test Conditions
APW7068
Unit
INPUT SUPPLY CURRENT VCC12 Supply Current (Shutdown mode) VCC12 Supply Current POWER-ON RESET Rising VCC12 Threshold Falling VCC12 Threshold OSCILLATOR Accuracy FOSC VOSC Duty Oscillator Frequency Ramp Amplitude Maximum Duty Cycle
ICC12
UGATE, LGATE DRIVE open; FS_DIS=GND UGATE, LGATE DRIVE open
(nominal 1.2V 2.7V) (NOTE3)
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
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APW7068
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12=12V, =-20~70°C. Typical values TA=25°C.
Symbol REFERENCE VREF
Parameter
Test Conditions
APW7068
Unit
Reference Voltage Reference Voltage Tolerance Load Regulation Linear Load Regulation
Error Amp1 Amp2 IOUT1=0 IOUT2=0 RL=10k, CL=10pF (NOTE3) RL=10k, CL=10pF (NOTE3) RL=10k, CL=10pF (NOTE3) VFB=0.8V
0.792 0.80 0.808
V/us V/us
ERROR AMPLIFIER Gain GBWP VCOMP VCOMP ICOMP ICOMP Open Loop Gain Open Loop Bandwidth Slew Rate Input Current COMP High Voltage COMP Voltage COMP Source Current COMP Sink Current COMP=2V COMP=2V BOOT=12V, UGATE-PHASE VCC12=12V, LGATE=2V
2.25 3.375 1.05 2.25 3.375
GATE DRIVERS IUGATE Upper Gate Source Current IUGATE ILGATE ILGATE RUGATE RUGATE RLGATE RLGATE Gain GBWP VDRIVE VDRIVE IDRIVE IDRIVE Upper Gate Sink Current Lower Gate Source Current Lower Gate Sink Current Upper Gate Sink Impedance Lower Gate Sink Impedance Dead Time Open Loop Gain Open Loop Bandwidth Slew Rate Input Current DRIVE High Voltage DRIVE Voltage DRIVE Source Current DRIVE Sink Current
Upper Gate Source Impedance BOOT=12V, IUGATE=0.1A BOOT=12V, IUGATE=0.1A VCC12=12V, ILGATE=0.1A Lower Gate Source Impedance VCC12=12V, ILGATE=0.1A
LINEAR REGULATOR RL=10k, CL=10pF (NOTE3) RL=10k, CL=10pF (NOTE3) RL=10k, CL=10pF (NOTE3) VFBL=0.8V DRIVE=5V DRIVE=5V
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
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APW7068
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12=12V, =-20~70°C. Typical values TA=25°C.
Symbol PROTECTION
Parameter
Test Conditions
APW7068 0.792 0.800 0.808 0.25
Unit
VFB-OV Over Voltage Protection Trip Point IOCSET OCSET Current Source Internal Soft-Start Interval (NOTE3)
Percent VREF
VFBL-UV Under Voltage Protection Trip Point Percent VREF SOFT START FOSC=300kHz REF_OUT VREF_OUT Output Voltage Offset Voltage IREF_OUT Source Current Sink Current Output Capacitance
NOTE3: Guaranteed design.
Typical Application Circuit
2.2nF
3.9K 2N7002
ON/OFF
APM2509
CIN1
470uFx2
VIN1
0.01uF
0.1uF 1.5K
VOUT1 1.2V
VOUT1
22nF
BOOT FS_DIS COMP DRIVE
UGATE PHASE
2.2nF
VIN2
3.3V
RGND1
COUT1
470uFx2
PGND LGATE OCSET REF_OUT VCC12
APM2506
CIN2
470uF
APM3055
VOUT2
2.5V 2.5K
APW7068
RGND2
1.17K
COUT2
470uF
specific application
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
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APW7068
Function Descriptions
VCC12 Power supply input pin. Connect nominal power supply this pin. power-on reset function monitors input voltage this pin. recommended that decoupling capacitor 10µF) connected noise decoupling. BOOT This provides bootstrap voltage upper gate driver driving N-channel MOSFET. external capacitor from PHASE BOOT, internal diode, power supply valtage VCC12, generates bootstrap voltage upper gate diver (UGATE). PHASE This return path upper gate driver. Connect this upper MOSFET source, connect capacitor BOOT bootstrap voltage. This also used monitor voltage drop across lower MOSFET over-current protection. This signal ground pin. Connect good ground plane. PGND This power ground lower gate driver. should tied board. COMP This output error amplifier. used compensation components. This inverting input error amplifier. used output voltage compensation components. This also monitored over-voltage protection. When voltage over 135% reference voltage, controller will make Low-side gate signal fully turn until fault events removed. UGATE This gate driver upper MOSFET output.
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LGATE This gate driver lower MOSFET output. DRIVE This drives gate external N-channel MOSFET linear regulator. also used compensation some specific applications,for example, with values output capacitance ESR. This inverting input linear regulator error amplifier. used output voltage. This also monitored under-voltage protection. When voltage under reference voltage (0.4V), both outputs will shutdown immediately. OCSET Connect resistor (Rocset) from this GND, internal 40uA current source will flow through this resistor create voltage drop. When VCC12 reaches rising threshold voltage, voltage drop Rocset will memoried compared with voltage across lower MOSFET. threshold over current limit therefore given
ILIMIT
IOCSET ROCSET RDS(ON)(LOW Side)
REF_OUT This provides buffed voltage, which from internal reference voltage. recommended that capacitor connected ground stability. FS_DIS This provides shutdown function. open drain logic signal pull this disable both outputs, leave open enable both outputs.
APW7068
Typical Characteristics
Power
VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V, L=1uH
Power
VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V, L=1uH
CH1: VCC12 (10V/div) CH2: (1V/div) CH3: (2V/div) Time: 10ms/div
CH1: VCC12 (10V/div) CH2: (1V/div) CH3: (2V/div) Time: 10ms/div
VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH
Shutdown(FS_DIS=GND)
VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH
CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: (1V/div) CH4: (2V/div) Time: 10ms/div
CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: (1V/div) CH4: (2V/div) Time: 10ms/div
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
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APW7068
Typical Characteristics (Cont.)
UGATE Rising
Vcc12=12V, Vin1=12V, Vo1=1.2V
UGATE Falling
Vcc12=12V, Vin1=12V, Vo1=1.2V
CH1: (20V/div) CH2: Phase (10V/div) CH3: (10V/div) Time: 50ns/div
CH1: (20V/div) CH2: Phase (10V/div) CH3: (10V/div) Time: 50ns/div
OVP_PWM Controller 135% VREF)
Vcc12=12V, Vin1=12V Vo1=1.2V, Vo2=2.5V,L=1uH
UVP_Linear Regulator (FBL< VREF)
VCC12=12V, Vin2=3.3V Vo2=2.5V, Io2=3A
CH1: (20V/div) CH2: (10V/div) CH3: (500mV/div) CH4: (2V/div) Time: 10ms/div CH1: (1V/div) CH2: Drive (5V/div) CH3: (2V/div) Time: 100us/div
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APW7068
Typical Characteristics (Cont.)
Load Transient Response(PWM Controller) VCC12=12V, Vin1=12V, Vo1=2V, Fosc=300KHz slew rate= A/us
CH1: (100mV/div,AC) CH2: (20V/div) CH3: Io1(10A/div) Time: 20us/div
CH1: (100mV/div,AC) CH2: (20V/div) CH3: Io1(10A/div) Time: 50us/div
CH1: (100mV/div,AC) CH2: (20V/div) CH3: Io1(10A/div) Time: 20us/div
Load Transient Response(Linear Regulator) VCC12=12V, Vin2=3.3V, Vo2=2.5V slew rate= 3A/us
CH1: (100mV/div,AC) CH2: Io2(2A/div) Time: 1us/div
CH1: (100mV/div,AC) CH2: Io2(2A/div) Time: 10us/div
CH1: (100mV/div,AC) CH2: Io2(2A/div) Time: 1us/div
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
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APW7068
Typical Characteristics (Cont.)
Over Current Protection
VCC12=12V, Vin1=12V, Vo1=1.2V,Vin2=3.3V, Vo2=2.5V, L=1uH, COUT=470uFx2 Rocset=1K Rds(on)=4m
Short Test after Power Ready
VCC12=12V, Vin1=12V, Vo1=1.2V,Vin2=3.3V, Vo2=2.5V, L=1uH, COUT=470uFx2 Rocset=1K Rds(on)=4m
CH1: (1V/div) CH2: Drive (5V/div) CH3: (20V/div) CH4: (10A/div) Time: 50us/div
CH1: (1V/div) CH2: Drive (5V/div) CH3: (20V/div) CH4: (10A/div) Time: 50us/div
Short Test before Power
VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH
0.804
VREF Junction Temperature
COUT=470uFx2
0.8035
Reference Voltage(V)
0.803
0.8025
0.802
VREF
0.8015
0.801
0.8005
CH1: VCC12 (10V/div) CH2: (1V/div) CH3: (20V/div) CH4: (10A/div) Time: 2ms/div
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
Junction Temperature
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APW7068
Typical Characteristics (Cont.)
UGATE Source Current UGATE Voltage
UGATE Sink Current UGATE Voltage
UGATE Source Current
VBOOT=12V
VBOOT=12V
UGATE Sink Current
PHASE=0V
PHASE=0V
UGATE Voltage
UGATE Voltage
LGATE Source Current LGATE Voltage
LGATE Sink Current LGATE Voltage
LGATE Source Current
VCC=12V
VCC=12V
LGATE Sink Current
LGATE Voltage
LGATE Voltage
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
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APW7068
Function Descriptions
Power Reset (POR) Power-On Reset (POR) function APW7068 continually monitors input supply voltage (VCC12), ensures supply voltage exceed rising threshold voltage. function initiates soft-start interval operation while VCC12 voltages exceed their threshold inhibits operation under disabled status. Soft-Start Figure shows soft-start interval. When VCC12 reaches rising threshold voltage, internal reference voltage controlled follow voltage proportional soft-start voltage. soft-start interval variable oscillator frequency. formulation given
Voltage(V)
Time VOUT1 VOUT2 VCC12 Voltage(V)
Figure Soft-Start Interval
20mV 32/Fosc
Figure shows more detail voltage ramps. voltage soft-start ramps formed with many small steps voltage. voltage step about 20mV FBL, period step about 64/FOSC. This method provides controlled voltage rise prevents large peak current charge output capacitor. voltage compares voltage shift earlier time establishment Figure2. voltage estabilishment time difference variable oscillator. formulation given Over-Current Protection
32/Fosc
20mV
Time
Figure Controlled Stepped Voltage during Soft-Start
Connect resistor (Rocset) from this GND, internal 40uA current source will flow through this resistor create voltage drop, which will compared with voltage across lower MOSFET.
FOSC
When voltage across lower MOSFET exceeds voltage drop across ROCSET, over-current condition detected controller will shutdown directly, converter's output latched.
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APW7068
Function Descriptions
Over-Current Protection (Cont.) threshold over current limit therefore given voltage over 135% reference voltage, controller will make Low-Side gate signal fully turn until fault events removed.
ILIMIT
IOCSET ROCSET RDS(ON)(LOW Side)
Under Voltage Protection monitored during converter operation Under Voltage(UV) comparator. voltage drop below reference voltage (50% 0.8V 0.4V), fault signal internally generated, device turns both highside low-side MOSFET converter' outs latched floating. controller will shutdown directly. Shutdown Enable Pulling FS_DIS voltage open drain transistor, shown typical application circuit, shutdown APW7068 controller. shutdown mode, UGATE LGATE turn pull PHASE respectively.
over-current never occurred normal operating load range; variation parameters above equation should determined. MOSFET' RDS(ON) varied temperature gate source voltage, user should determine maximum RDS(ON) manufacturer' datasheet. minimum IOCSET (36uA) minimum ROCSET should used above equation. Note that ILIMIT current flow through lower MOSFET; ILIMIT must greater than maximum output current half inductor ripple current. Over Voltage Protection monitored during converter operation Over Voltage(OV) comparator.
Application Information
Output Voltage Selection output voltage converter programmed with resistive divider. better resistors resistive divider recommended. inverter input error amplifier, reference voltage 0.8V. output voltage determined linear regulator output voltage VOUT2 also means external resistor divider. inverter input error amplifier, reference voltage 0.8V. output voltage determined
VOUT1 GND1
Where resistor connected from VOUT1 RGND1 resistor connected from GND.
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VOUT2 GND2
Where resistor connected from VOUT2 RGND2 resistor connected from GND.
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APW7068
Application Information (Cont.)
Linear Regulator Input/Output Capacitor Selection input capacitor chosen based voltage rating. Under load transient condition, input capacitor will momentarily supply required transient current. output capacitor linear regulator chosen minimize droop during load transient condition. addition, capacitor chosen based voltage rating. Linear Regulator Input/Output MOSFET Selection maximum DRIVE voltage about when VCC12 equal 12V. Since this drives external N-channel MOSFET, therefore maximum output voltage linear regulator dependent upon VGS. OUT2MAX Another criterion efficiency heat removal. power dissipated MOSFET given
PHASE OUTPUT1
loop. compensation network among COMP, VOUT1 should added. compensation network shown Fig. output filter consists output inductor output capacitors. transfer function filter given
GAINLC
COUT1 COUT1 COUT1
poles zero this transfer functions are:
OUT1
FESR
OUT1
double poles filter, FESR zero introduced output capacitor.
IOUT2 (VIN OUT2 Where IOUT2 maximum load current, VOUT2 nominal output voltage. some applications, heatsink might required help maintain junction temperature MOSFET below maximum rating. Linear Regulator Compensation Selection linear regulator stable over loads current. However, transient response further enhanced DRIVE pin. Depending output capacitance load current application, value this network then varied. Compensation output filter step down converter introduces double pole, which contributes with -40dB/decade gain slope degrees phase shift control
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Frequency(Hz) GAIN (dB) -40dB/dec
COUT1
Figure Output Filter
connecting network between
FESR -20dB/dec
Figure Filter GAIN Frequency
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APW7068
Application Information (Cont.)
Compensation (Cont.) modulator shown Figure input output error amplifier output PHASE node. transfer function modulator given
OUT1 COMP
GAINPWM
VIN1 VOSC
Driver
Figure Compensation Network
closed loop gain converter written GAINLC GAINPWM GAINAMP
PHASE
VOSC
Comparator
Output Error Amplifier Driver
Figure shows asymptotic plot closed loop converter gain, following guidelines will help design compensation network. Using below guidelines should give compensation similar curve plotted. stable closed loop -20dB/ decade slope phase margin greater than degree. 1.Choose value usually between 2.Select desired zero crossover frequency (1/5 1/10) >FO>FESR following equation calculate
VOSC
Figure Modulator compensation network shown Figure provides close loop transfer function with highest zero crossover frequency sufficient phase margin. transfer function error amplifier given
VCOMP VOUT1 R1//
GAINAMP
3.Place first zero before output filter double pole frequency FLC. 0.75 Calculate equation:
0.75
poles zeros transfer function are:
4.Set pole zero frequency FESR: FESR Calculate equation:
FESR
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Copyright ANPEC Electronics Corp. Rev. Jun., 2006
APW7068
Application Information (Cont.)
Compensation (Cont.) 5.Set second pole half switching frequency also second zero output filter double pole FLC. compensation gain should exceed error amplifier open loop gain, check compensation gain with capabilities error amplifier. Combine equations will following component calculations:
ripple voltage approximated
IRIPPLE
VIN1 VOUT1 VOUT1 VIN1
VOUT1 IRIPPLE
where switching frequency regulator. Although increase inductor value frequency reduces ripple current voltage, tradeoff will exist between inductor' ripple current regulator load transient response time. smaller inductor will give regulator faster load transient response expense higher ripple current. Increasing switching frequency (FS) also reduces ripple current voltage, will increase switching loss MOSFET power dissipation converter. maximum ripple current occurs maximum input voltage. good starting point choose ripple current approximately maximum output current.
Once inductance value been chosen, select inductor that capable carrying required peak current without going into saturation. some types inductors, especially core that made ferrite, ripple current will increase abruptly when saturates. This will result larger output ripple voltage.
GAIN (dB)
20log (R2/R1)
20log (VIN
Compensation Gain
Filter Gain Frequency(Hz) Converter Gain
Output Capacitor Selection Higher capacitor value lower reduce output ripple load transient drop. Therefore, selecting high performance capacitors intended switching regulator applications. some applications, multiple capacitors have parallel achieve desired value. small decoupling capacitor parallel bypassing noise also recommended, voltage rating output capacitors also must considered. tantalum capacitors used, make sure they surge tested
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Figure Converter Gain Frequency Output Inductor Selection inductor value determines inductor ripple current affects load transient response. Higher inductor value reduces inductor' ripple current induces lower output ripple voltage. ripple current
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APW7068
Application Information (Cont.)
Output Capacitor Selection (Cont.) manufactures. doubt, consult capacitors manufacturer. Input Capacitor Selection input capacitor chosen based voltage rating current rating. reliable operation, select capacitor voltage rating least times higher than maximum input voltage. maximum current rating requirement approximately IOUT1/2, where IOUT1 load current. During power input capacitors have handle large amount surge current. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. high frequency decoupling, ceramic capacitor connected between drain upper MOSFET source lower MOSFET. applications, multiple capacitors have parallel achieve desired value. small decoupling capacitor parallel bypassing noise also recommended, voltage rating output capacitors also must considered. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. Input Capacitor Selection input capacitor chosen based voltage rating current rating. reliable operation, select capacitor voltage rating least times higher than maximum input voltage. maximum current rating requirement approximately IOUT1/2, where IOUT1 load current. During power input capacitors have handle large amount surge current. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. high frequency decoupling, ceramic
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
capacitor connected between drain upper MOSFET source lower MOSFET. MOSFET Selection selection N-channel power MOSFETs determined RDS(ON), reverse transfer capacitance (CRSS) maximum output current requirement. There components loss MOSFETs: conduction loss transition loss. upper lower MOSFET, losses approximately given following: PUPPER IOUT1 TC)(RDS(ON))D (0.5)( IOUT1)(VIN1)( tSW)FS PLOWER IOUT1 TC)(RDS(ON))(1-D) Where IOUT1 load current temperature dependency RDS(ON) switching frequency switching interval duty cycle Note that both MOSFETs have conduction loss while upper MOSFET include additional transition loss. switching internal, function reverse transfer capacitance RSS. (1+TC) term factor temperature dependency RDS(ON) extracted from "RDS(ON) Temperature" curve power MOSFET. Layout Considerations high switching frequency converter, correct layout important ensure proper operation regulator. With power devices switching 300KHz above, resulting current transient will cause voltage spike across interconnecting impedance parasitic circuit elements. example, consider turn-off transition MOSFET. Before turn-off, MOSFET carrying full load current. During turn-off, current stops flowing MOSFET free-wheeling lower MOSFET parasitic diode. parasitic inductance circuit genwww.anpec.com.tw
APW7068
Application Information (Cont.)
Layout Considerations (Cont.) erates large voltage spike during switching interval. general, using short, wide printed circuit traces should minimize interconnecting impedances magnitude voltage spike. signal power grounds kept separate till combined using ground plane construction single point grounding. Figure illustrates layout, with bold lines indicating high current paths; these traces must short wide. Components along bold lines should placed lose together. Below checklist your layout: metal plate bottom packages (QFN-16) must soldered connected plane backside through several thermal vias. Keep switching nodes (UGATE, LGATE PHASE) away from sensitive small signal nodes since these nodes fast moving signals. Therefore, keep traces these nodes short possible. traces from gate drivers MOSFETs (UG, DRIVE) should short wide. Place source high-side MOSFET drain low-side MOSFET close possible. Minimizing impedance with wide layout plane between pads reduces voltage bounce node. Decoupling capacitor, compensation component, resistor dividers, boot capacitors, REF_OUT capacitors should close their pins. (For example, place decoupling ceramic capacitor near drain high-side MOSFET close possible. bulk capacitors also placed near drain). input capacitor should near drain
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upper MOSFET; output capacitor should near loads. input capacitor should close output capacitor lower MOSFET GND. drain MOSFETs (VIN1 PHASE nodes) should large plane heat sinking.
APW7068 VIN1 VCC12 VIN2 BOOT DRIVE VOUT2
UGATE PHASE
LGATE REF_OUT
VOUT1
Figure Layout Guidelines
APW7068
Package Information
(150mil)
0.015
GAUGE PLANE SEATING PLANE
0.010
Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 1.274 5.808 0.382 6.215 1.274 0.228 0.015 Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150
Inches Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 0.244 0.050
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APW7068
Package Information
QSOP-16
GAUGE PLANE
Millimeters Min. 1.35 0.10 0.20 4.80 5.79 3.81 0.635 TYP. 0.41 1.27 0.016 Max. 1.75 0.25 0.30 5.00 6.20 3.99 Min. 0.053 0.004 0.008 0.189 0.228 0.150
Inches Max. 0.069 0.010 0.012 0.197 0.244 0.157 0.025 TYP. 0.050
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APW7068
Packaging Information
QFN-16
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Millimeters Min. 0.76 0.00 0.57 0.20 REF. 3.90 3.90 0.25 2.05 2.05 0.650 0.50 0.60 0.002 4.10 4.10 0.35 2.15 2.15 0.154 0.154 0.010 0.081 0.081 0.0257BSC 0.024 Max. 0.84 0.04 0.63 Min. 0.030 0.00 0.022 0.008 REF. 0.161 0.161 0.014 0.085 0.085 Inches Max. 0.033 0.0015 0.025
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APW7068
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material 90/10 63/37 SnPb), 100%Sn Meets Specification RSI86-91, ANSI/J-STD-002 Category
Reflow Condition
(IR/Convection Reflow)
Critical Zone
Ramp-up
Temperature
Tsmax
Tsmin Ramp-down Preheat
Peak
Classification Reflow Profiles
Profile Feature Average ramp-up rate Preheat Temperature (Tsmin) Temperature (Tsmax) Time (min max) (ts) Time maintained above: Temperature (TL) Time (tL) Peak/Classificatioon Temperature (Tp) Time within actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds table 10-30 seconds Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds table 20-40 seconds
6°C/second max. 6°C/second max. minutes max. minutes max. Time 25°C Peak Temperature Notes: temperatures refer topside package. Measured body surface.
Copyright ANPEC Electronics Corp. Rev. Jun., 2006 www.anpec.com.tw
APW7068
Classification Reflow Profiles(Cont.)
Table SnPb Entectic Process Package Peak Reflow Temperatures Package Thickness Volum Volume <350 <2.5 +0/-5°C +0/-5°C +0/-5°C +0/-5°C
Table Pb-free Process Package Classification Reflow Temperatures Package Thickness Volume Volume Volume <350 350-2000 >2000 <1.6 +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* *Tolerance: device manufacturer/supplier shall assure process compatibility including stated classification temperature (this means Peak reflow temperature +0°C. example 260°C+0°C) rated level.
Reliability Test Program
Test item SOLDERABILITY HOLT Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD Description 245°C, 1000 Bias @125°C Hrs, 100%RH, 121°C -65°C~150°C, Cycles VHBM 2KV, 200V 10ms, 100mA
Carrier Tape Reel Dimensions
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
www.anpec.com.tw
APW7068
Carrier Tape Reel Dimensions(Cont.)
Application
SOP-14 (150mil) Application
330REF
100REF
13.0
16.5REF 12.4
0.3±0.05
1.75
16.0 2.10 5.2±
0.50 1.50 (MIN) +1.5 1.55 +0.1
1.75±0.1
12.75+ 0.15
QSOP-
5.5±
1.55+ 0.25
2.1± 0.3±0.013
(mm)
Shipping Tray
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
www.anpec.com.tw
APW7068
Shipping Tray (Cont.)
Cover Tape Dimensions
Application SOP- QSOP- Carrier Width Cover Tape Width 21.3 Devices Reel 2500 2500
Customer Service
Anpec Electronics Corp. Head Office No.6, Dusing Road, SBIP, Hsin-Chu, Taiwan, R.O.C. 886-3-5642000 886-3-5642050 Taipei Branch 137, Lane 235, Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, 886-2-89191368 886-2-89191369
Copyright ANPEC Electronics Corp. Rev. Jun., 2006
www.anpec.com.tw

Synchronous Buck Linear Controller with 0.8V Reference Voltage Re

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