Dual Synchronous Buck Controllers Linear Controller Synchronous B

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Dual Synchronous Buck Controllers Linear Controller Synchronous B

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APW7066
Dual Synchronous Buck Controllers Linear Controller
Synchronous Buck Converters Linear Regulator range Input Power Supplies Require generate Shunt Regulator 5.8V 0.6V Reference VOUT1 VOUT3 with 0.8% accurate 3.3V Reference VOUT2 with 0.8% accurate Buffered Reference Output Three Outputs have Independent Soft-Start Enable Internal 300kHz Oscillator Programmable Frequency range from 800kHz Synchronous Switching Frequency mode Independent Mode Selection Phase Shift Selection Power Good Function Short-Circuit Protection VOUT1 VOUT2 Thermally Enhanced TSSOP-24 QFN-32 Package Lead Free Available (RoHS Compliant)
General Description
APW7066 synchronous buck controllers linear controller with high precision internal references voltage offer accurate outputs. controllers designed drive N-channel MOSFETs synchronous buck topology, linear controller drives external N-channel MOSFET. device requires power supplies, supply available, VCC12 offer optional shunt regulator 5.8V supply. outputs have independent soft-start enable functions SS/EN pins control. Connect capacitor from each SS/EN ground setting soft-start time, pulling SS/EN below disable regulator. Pull SS2/EN2 VCC, enter mode, SS1/EN1 controls both VOUT1 VOUT2, allows VOUT2 track VOUT1. also offers phase shift function REFOUT select phase shift between VOUT1 VOUT2 mode Independent mode. When SS/EN pins exceed 3.3V faults detected, PGOOD goes high indicate regulators ready. SS/EN pins goes below 3.2V outputs fault condition, PGOOD will pulled low. internal oscillator nominally 300kHz (keep FS/SYNC open short GND), offers programmable frequency function from 70kHz 800kHz; connecting resistor from FS/SYNC decrease frequency, conversely, connect resistor from FS/SYNC increase frequency. also provides synchronous frequency function. Connect LGATE signal another converter FS/SYNC pin; forcing switching frequency follow
Applications
Graphic Cards memory Power Supplies Low-Voltage Distributed Power Supplies
ANPEC reserves right make changes improve reliability manufacturability without notice, advise customers obtain latest version relevant information verify before placing orders. Copyright ANPEC Electronics Corp. Rev. Jun., 2005 www.anpec.com.tw
APW7066
General Description (Cont.)
external clock. possible synchronous frequency from 150kHz 800kHz. There Rds(on) sensing under-voltage sensing APW7066. However, provides simple short-circuit protection monitoring COMP1 COMP2 over-voltage. When pins exceeds their trip point condition persists internal clock cycle (3-6us 300kHz), then will shut down regulators.
COMP2 COMP1
Description
REFIN
BOOT1
UGATE1 PGND_1 VCC12_1
SS2/EN2 SS3/EN3 VREF DRIVE3
COMP1 COMP2 REFIN REFOUT SS1/EN1
BOTTOM SIDE
BOOT1 UGATE1
REFOUT SS1/EN1 SS2/EN2 SS3/EN3 VREF DRIVE3 PGOOD FS/SYNC UGATE2 BOOT2 BOTTOM SIDE
VCC12 LGATE1 LGATE2 PGND UGATE2 BOOT2 PGOOD FS/SYNC
LGATE1 LGATE2 VCC12_2 PGND_2
TSSOP-24 VIEW
QFN32 View
Ordering Marking Information
APW7066
Lead Free Code Handling Code Temp. Range TSSOP-P Operating Ambient Temp. Range Handling Code Tube Tape Reel Lead Free Code Lead Free Device Blank Original Device XXXXX Date Code
PW7066
XXXXX
PW7066
XXXXX
XXXXX Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials 100% matte plate termination finish; which fully compliant with RoHS compatible with both SnPb lead-free soldiering operations. ANPEC lead-free products meet exceed lead-free requirements IPC/JEDEC STD-020C classification lead-free peak reflow temperature.
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APW7066
Block Diagram
VREF VCC12
5.8V 30uA Power Reset Control
SS1/EN1 BOOT1 30uA Bias Current SS2/EN2 30uA LGATE1 SS3/EN3 3.3V BOOT2 Gate Control Logic Oscillator LGATE2 0.6V 3.3V 3.3V Gate Control Logic UGATE1
UGATE2
PGOOD
Monitor COMP Pins Short Protection
COMP1 0.6V 3.3V Clock Cycle Filter
FS/SYNC
REFOUT
short, Filter shut down outputs
REFIN VCC12 0.6V
COMP2
DRIVE3
PGND
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APW7066
Absolute Maximum Ratings
Symbol VCC12 VCC12 Parameter Rating -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +0.3 +150 +150 Unit
VCC, separate supply VCC, separate supply VCC, shunt regulator VCC, shunt regulator UGATE1, UGATE2, BOOT1, BOOT2 LGATE1, LGATE2, DRIVE3 FS/SYNC REFIN, REFOUT, PGOOD, VREF FB1, COMP1, FB2, COMP2, SS1/EN1, SS2/EN2, SS3/EN3 PGND TSTG UGATE1, UGATE2, BOOT1, BOOT2 LGATE1, LGATE2, DRIVE3 FS/SYNC REFIN, REFOUT, PGOOD, VREF FB1, COMP1, FB2, COMP2, SS1/EN, SS2/EN2, SS3/EN3 PGND Operating Temperature Range Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10sec)
Electrical Characteristics
Operating Conditions: VCC12 12V, 70°C, Unless Otherwise Specified.
Parameter INPUT SUPPLY POWER Input Supply Current (Quiescent) Test Conditions VCC; outputs disabled VCC12; outputs disabled Min. Typ. Max. Units
VCC12; UGATEs, LGATEs 1nF, 300KHz Input Supply Current (Dynamic) VCC; UGATEs, LGATEs 1nF, 300KHz 20mA current; ~Equivalent Shunt Regulator Output Voltage resistor Shunt Regulator Current resistor
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APW7066
Electrical Characteristics (Cont.)
Operating Conditions: VCC12 12V, 70°C, Unless Otherwise Specified.
Parameter INPUT SUPPLY POWER Rising Power-On Reset Threshold Falling VCC12 Rising VCC12 Falling 4.15 7.55 4.23 4.15 7.55 Test Conditions Min. Typ. Max. Units
SYSTEM ACCURACY Outputs Reference Voltage Output Reference Voltage Outputs System Accuracy Output System Accuracy OSCILLATOR Accuracy Frequency Adjustment Range FS/SYNC open FS/SYNC pin: resistor GND; resistor VCC12
3.3V -0.8 -0.8
V/µs
Sawtooth Amplitude Duty-Cycle Range ERROR AMPLIFIER (OUT1 OUT2) Open-Loop Gain ground Open-Loop Bandwidth 100pF, ground Slew Rate 100pF, ground Offset COMP1/2 FB1/2; compare internal VREF/REFIN Maximum Output Voltage ground; (may trip short-circuit) Output High Source Current COMP1/2, VCOMP=2V Output Sink Current COMP1/2, VCOMP=2V PROTECTION MONITOR Under-Voltage Threshold Causes PGOOD low; there (COMP1 COMP2) filter time, implies COMP pin(s) out-of-range, shuts down Based internal oscillator clock filter time frequency (nominal 300kHz 3.3µs clock period) PGOOD Voltage IPGOOD LINEAR REGULATOR (OUT3) DRIVE3 FB3; compare internal Offset VREF DRIVE3 High Output Voltage
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Clock pulses
VCC12
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APW7066
Electrical Characteristics (Cont.)
Operating Conditions: VCC12 12V, 70°C, Unless Otherwise Specified.
Parameter LINEAR REGULATOR (OUT3) DRIVE3 High Output Source Current DRIVE3 Output Sink Current VREF Output Voltage Output Accuracy Source Current REFOUT (VTTREF) Output Voltage Offset Voltage Source Current Sink Current Output Capacitance Output High Voltage Minimum select degree phase; Table ENABLE/SOFTSTART (SS/EN 1,2,3) Rising Enable Threshold falling Soft-Start Current Soft-Start High Voltage Output High Voltage FS/SYNC Frequency range Lock-in High Voltage GATE DRIVERS Output1 GATE Driver Source Output2 GATE Driver Source Output1 GATE Driver Sink Output2 GATE Driver Sink Output Voltage Output Voltage from another example) UGATE1, LGATE1=3V, BOOT=12V UGATE2, LGATE2=3V, BOOT=12V UGATE1, LGATE1=3V, BOOT=12V UGATE2, UGATE2=3V, BOOT=12V UGATE1, UGATE2 LGATE1, LGATE2 ramp select mod; Table 1.05 0.95 Determined REFIN voltage 1.1µF capacitance -0.8 Test Conditions Min. Typ. Max. Units
+0.8 0.48
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APW7066
Typical Application Circuit
APW7066 MODE
VCC12 Optional shunt regulator
COMP1 VOUT1 BOOT1 VIN1
UGATE1 COMP2 VOUT2 LGATE1 VCC12
VOUT1
VOUT1(DDR) REFIN PHASE SHIFT PHASE SHIFT VTTREF APW7066 VCC12
BOOT2
VIN2=VOUT1(DDR)
UGATE2 LGATE2 REFOUT VREF PGOOD
VOUT2
VIN3
SYNCHRONOUS FREQUENCY
FS/SYNC SS1/EN1 SS2/EN2 SS3/EN3 PGND DRIVE3 VOUT3
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APW7066
Typical Application Circuit (Cont.)
APW7066 INDEPENDENT MODE
VCC12 Optional shunt regulator
COMP1 VOUT1 BOOT1 VIN1
UGATE1 COMP2 VOUT2 LGATE1 VCC12
VOUT1
VREF PHASE SHIFT PHASE SHIFT VTTREF VCC12
BOOT2 REFIN APW7066 UGATE2
VIN2
VOUT2
LGATE2 REFOUT VREF PGOOD VIN3
SYNCHRONOUS FREQUENCY
FS/SYNC SS1/EN1 SS2/EN2 SS3/EN3 PGND DRIVE3 VOUT3
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APW7066
Function Descriptions
Power supply input pin. Connect nominal power supply this control circuit, connect resistor (nominally 300) VCC12 shunt regulator function (typical 5.8V). recommended that decoupling capacitor 10uF) connected noise decoupling. This signal ground pin. metal thermal under package substrate; connects metal thermal together board, ties good plane electrical thermal conduction. VCC12 Power supply input pin. Connect nominal power supply this gate driver. recommended that decoupling capacitor 10uF) connected noise decoupling. PGND This power ground gate driver linear driver circuit. should tied GND. FB1, FB2, These pins inverting inputs error amplifiers their respective regulators. They used output oltage compensation components. SS1/EN1, SS2/EN2, SS3/EN3 These pins provide functions. Connect capacitor setting soft-start time. open drain logic signal pull SS/EN disable respective output, leave open enable respective output. COMP1, COMP2 These pins outputs error amplifiers their respective regulators. They used compensation components. UGATE1, UGATE2 These pins provide gate driver upper MOSFETs VOUT1 VOUT2. LGATE1, LGATE2 These pins provide gate driver lower MOSFETs VOUT1 VOUT2.
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BOOT1, BOOT2 These pins provide bootstrap voltage gate driver driving upper MOSFETs. connected power voltage directly, difference voltage between BOOT must high enough drive upper MOSFETs. REFIN This reference input voltage error amplifier VOUT2. also provides voltage into buffer, which REFOUT pin. REFOUT This provides buffed voltage, which from REFIN pin. Independent mode, used other ICs. mode, from VOUT1, used buffer. This also uses select phase shift (see table1). When this pulls VCC, buffer disabled REFOUT available use. recommended that 0.1uF capacitor connected ground stability. VREF This provides 3.3V reference voltage, which used REFIN other voltage reference. recommended that capacitor connected ground stability. DRIVE3 This drives gate external N-channel MOSFET linear regulator. PGOOD This open drain device; connect pull resistor PGOOD function. FS/SYNC This used adjust switching frequency. Connecting resistor from FS/SYNC ground increases switching frequency. Conversely, connecting resistor from this VCC12 reduces switching frequency. addition, this also provides synchronous frequency function. external clock into this pin, force switching frequency follow external clock.
APW7066
Typical Characteristics
VOUT1 Power
VCC12(5V/div)
VOUT2 Power
VCC12(5V/div)
VCC(2V/div)
VCC(2V/div)
VOUT2(2V/div) VOUT1(1V/div)
SS1(2V/div)
SS2(2V/div)
Time(5ms/div)
Time(5ms/div)
VOUT3 Power
VCC12(5V/div)
VREF Power
VCC12(5V/div)
VCC(2V/div)
VCC(2V/div)
VOUT3(1V/div) VREF(2V/div)
SS3(2V/div)
SS2(2V/div)
Time(5ms/div)
Time(5ms/div)
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APW7066
Typical Characteristics (Cont.)
VOUT1 Power
UGATE1(20V/div)
VOUT2 Power
UGATE2(20V/div)
LGATE1(10V/div)
LGATE2(10V/div)
VOUT1(1V/div)
VOUT2(5V/div)
SS1(2V/div)
SS2(2V/div)
Time(2ms/div)
Time(2ms/div)
Mode Power
SS2=VCC VOUT1=REFIN
Phase Shift degrees
VREF(2V/div)
LG1(10V/div)
VOUT2(2V/div) LG2(10V/div) VOUT1(1V/div)
SS1(2V/div)
Time(2ms/div)
Time(1us/div)
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APW7066
Typical Characteristics (Cont.)
Phase Shift degrees
Phase Shift degrees
LG1(10V/div)
LG1(10V/div)
LG2(10V/div)
LG2(10V/div)
Time(1us/div)
Time(1us/div)
PGOOD High
SS1(2V/div)
PGOOD
SS1(2V/div) SS2(2V/div) SS2(2V/div)
SS3(2V/div)
SS3(2V/div)
PGOOD(5V/div)
PGOOD(5V/div)
Time(5ms/div)
Time(5ms/div)
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APW7066
Typical Characteristics (Cont.)
VOUT2 Short Circuit Protection
VOUT1 Short Circuit Protection
Comp1 (2V/div) Comp2 (2V/div) (2V/div) (2V/div)
(20V/div) (20V/div)
PGOOD (5V/div)
PGOOD (5V/div)
Time(5us/div)
Time(5us/div)
VOUT1 Load Transient
VOUT1=VIN3 VOUT1 (0.2V/div)
VOUT2 Load Transient
VOUT1 (0.1V/div) VOUT1=VIN3
VOUT2 (0.1V/div)
VOUT2 (0.1V/div)
VOUT3 (0.1V/div)
VOUT3 (0.05V/div)
IOUT2 (5A/div) IOUT1 (10A/div)
Time(20us/div)
Time(20us/div)
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APW7066
Typical Characteristics (Cont.)
VOUT3 Load Transient
VOUT1=VIN3 VOUT1 (0.1V/div)
Rising
(10V/div)
VOUT2 (0.1V/div)
Phase1 (10V/div)
VOUT3 (0.1V/div)
(10V/div)
IOUT3 (2A/div)
Time(20us/div)
Time(50ns/div)
Falling
Rising
(10V/div)
(10V/div)
Phase1 (10V/div)
Phase2 (10V/
(10V/div) (10V/div)
Time(50ns/div)
Time(50ns/div)
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APW7066
Typical Characteristics (Cont.)
Falling
PGOOD Sink Current PGOOD Voltage
(10V/div)
Sink Current (mA)
Phase2 (10V/div)
(10V/div)
Time(50ns/div)
PGOOD Voltage (mV)
REFOUT Voltage Source Current
3.35 3.34 3.33
VREF Voltage Source Current
3.32
REFOUT Voltage
3.31
3.31 3.29 3.28 3.27 3.26 3.25
VREF Voltage
3.32
3.29
3.28
Source Current (mA)
Source Current (mA)
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APW7066
Typical Characteristics (Cont.)
Sink Current Voltage
Source Current Voltage
Source Current
Sink Current
Voltage
Voltage
Sink Current Voltage
Source Current Voltage
Source Current
Sink Current
Voltage
Voltage
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APW7066
Typical Characteristics (Cont.)
Sink Current Voltage
BOOT=12V
Source Current Voltage
BOOT=12V
Sink Current
Source Current
Voltage
Voltage
Sink Current Voltage
Source Current Voltage
Source Current
Sink Current
Voltage
Voltage
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APW7066
Typical Characteristics (Cont.)
DRIVE3 Sink Current Voltage
DRIVE3 Source Current Voltage
Source Current (mA)
Sink Current (mA)
DRIVE3 Voltage
DRIVE3 Voltage
Resistance Switching Frequency
1000
VCC12
Shunt Regulator Sink Current Voltage
Resistance
Sink Current (mA)
Switching Frequency (kHz)
Shunt Regulator Voltage
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APW7066
Typical Characteristics (Cont.)
Comp Sink Current Voltage
Comp Source Current Voltage
Sink Current (mA)
Source Current (mA)
Comp Voltage
Comp Voltage
Voltage Temperature
VREF Voltage Temperature
3.35 3.34 3.33
VREF Voltage
3.32 3.31 3.29 3.28 3.27 3.26 3.25
Voltage
Temperature (°C)
Temperature (°C)
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APW7066
Function Descriptions
Operational Modes APW7066 independent synchronous buck converters, also mode operation allow VOUT2 track VOUT1. independent mode operation, connect capacitor from each SS/EN ground each regulator' soft-start time. 3.3V reference VREF used directly, divided resistors REFIN, since VREF controlled SS2/EN2. mode chosen connecting SS2/EN2 VCC(5V). this mode, SS2/EN2 function will disabled, SS1/EN1 used control soft start enable both VOUT1 VOUT2. VOUT1 used REFIN VOUT2, that makes VOUT2 track VOUT1.
VREF REFIN
Phase Shift APW7066 phase shift function, REFOUT select phase shift between Independent mode mode. Connect REFOUT degrees either mode. this case, buffer REFOUT disabled. Leave REFOUT open shifts phase degrees mode, degrees Independent mode, REFOUT used this case Table 1.).
MODE Independent Independent SS2/EN2 REFOUT REFIN PHASE SHIFT CH1/CH2 VOUT1 SS1/EN1 Open Open VOUT1 VREF VREF SS1/EN1 SS2/EN2
Table1.Mode Phase Selection advantage Phase shift avoid overlapping switching current spikes channels, interaction between channels; also reduces current input capacitors, allowing fewer caps employed. However, phase shift between rising edge LGATE1 LGATE2 (See figure 3.), depending duty cycles, falling edges channels might overlap; user should check
SS1/EN1 SS2/EN2 SS3/EN3
Figure Independent Mode Circuit
VOUT1 REFIN
(0deg) (90deg) (180deg)
SS1/EN1 SS2/EN2 SS3/EN3
Figure 2.DDR Mode Circuit
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Figure Phase with respect rising edge
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APW7066
Function Descriptions (Cont.)
Soft-Start/Enable three SS/EN pins control soft-start enable disable controller. Independent mode, three regulators have independent soft-start enable functions. Connect soft-start capacitor from each SS/EN soft-start interval, open drain logic signal each SS/EN will enable disable respective output. Figure Shows soft-start interval. When both VCC12 reach their Power-On-Reset threshold 4.23V 7.8V, 30uA current source starts charge capacitor. When reaches enabled threshold about internal 0.6V reference starts rise follows error amplifier output (COMP) suddenly raises 1.1V, which valley oscillator' triangle wave, leads VOUT start Until reaches about 3.0V, internal reference completes soft-start interval reaches 0.6V; then VOUT1 regulation. still rises 3.5V then stops.
VOLTAGE
PGOOD PGOOD output open-drain device, when present; gate open-drain device will high, forcing PGOOD low. three SS/EN pins signals control PGOOD signal (see block diagram), after three SS/EN signals over threshold high 3.3V three outputs have short-circuit, PGOOD goes high indicate regulators ready. SS/EN pins goes below threshold 3.2V, PGOOD will low. Also, outputs short, PGOOD pull short-circuit condition continues clock pulses, regulators will shut down. short-circuit long enough shut down, still cause PGOOD momentarily. Because PGOOD open-drain device, typical range value connect pull high resistor will 10k; PGOOD used, leave open. Shunt Regulator APW7066 must have power supplies (5V) VCC12 (12V) drive (5V) control circuit VCC12 (12V) drivers outputs. also operate only VCC12, because shunt regulator 5.8V designed (5V); range shunt regulator designed over usual range 4.5V 5.5V typical power supplies. Connect resistor from VCC12 shunt regulator supply current. input supply current 7mA; minimum shunt regulator current about 7mA, therefore 20mA shunt regulator current enough; thus, typical value, resistor recommended. relation among minimun shunt regulator current, required shunt regulator current supply current
TIME
Figure Soft-Start Interval
TSoft Start
Where: external Soft-Start capacitor Soft-Start current 30µA
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APW7066
Function Descriptions (Cont.)
PGOOD (Cont.) ISHUNT ISHUNT(MIN) Where: ISHUNT Required Shunt Regulator Current Supply Current ISHUNT(MIN) Minimum Shunt Regulator Current
OPTIONAL (5.8V) SHUNT REGULATOR VCC12
SYNC switching frequency also synchronized external frequency. there switching converters same board, taking LGATE signal from another switching converter, through resistor, connecting FS/SYNC pin. APW7066 will read another converter' frequency after several milliseconds, APW7066 will change frequency. another converter' signal lost, APW7066 will return internal oscillator. This allows switching converters operating same frequency avoid interference from independent frequencies between them. acceptable frequency range 150kHz 800kHz. Short-Circuit Protection APW7066 simple short-circuit protection monitor COMP1 COMP2 VOUT1/2. When output voltage short, should start follow output, since resistor divider from output. inverting input Error-Amp, when lower than Error-Amp reference, then COMP will rise increase duty-cycle upper MOSFET gate driver, this allows output higher voltage. short-circuit condition long enough, COMP will exceed trip point 3.3V, duty circle will maximum. This means that either Over-Current Under-Voltage condition detected. COMP1 COMP2 exceeds their trip points, holds over filter time (1-2 clock cycle switching frequency), then regulators will shut down, require either VCC12 restart. Note that linear regulator short-circuit protection.
Oscillator 7066 provides oscillator switching frequency adjustment. Connect resistor from FS/SYNC ground, nominally 300kHz oscillator switching frequency increased according value resistor. adjustment range switching frequency 300kHz 800kHz. Conversely, connecting resistor from FS/SYNC VCC12 reduces switching frequency.The adjustment range switching frequency 70kHz 300kHz.
1000 Resistance (kO) Switching Frequency (kHz) VCC12
Figure FS/SYNC Resistance Frequency
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APW7066
Application Information
Output Voltage Setting output voltage adjusted with resistive divider, from output voltage ground. better resistors these resistor dividers recommended. reference voltages VOUT1 VOUT3 0.6V, reference voltage VOUT2 REFIN voltage. VREF voltage REFIN independent mode. following equations used calculate output voltage:
VOUT1 0.6V
Linear Regulator Input/Output MOSFET Selection maximum DRIVE3 voltage determined VCC12. Since this drives external N-channel MOSFET, therefore maximum output voltage linear regulator dependent upon VGS. VOUT3MAX VCC12 Another criteria efficiency heat removal. power dissipated MOSFET given Pdiss Iout (VIN VOUT3) where Iout maximum load current VOUT3 nominal output voltage some applications, heatsink might required help maintain junction temperature MOSFET below maximum rating. Linear Regulator Compensation Selection linear regulator stable over load current. However, transient response further enhanced connecting network between DRIVE3 pin. Depending output capacitance load current application, value this network then varied. good starting point resistor value 6.8k 470pF capacitor. Compensation output filter step down converter introduces double pole, which contributes with -40dB/decade gain slope degrees phase shift control loop. compensation network between COMP, VOUT should added. compensation network shown Fig. output filter consists output inductor output capacitors. transfer function filter given GAINLC
VOUT2 REFIN VOUT3 0.6V
VOUT1 (DDR Mode) REFIN VREF (Independe Mode) REFIN
Where: resistor from VOUT resistor from resistor from VREF VOUT1 REFIN resistor from REFIN Note that part compensation. should conformed feedback compensation. Linear Regulator Input/Output Capacitor Selection input capacitor chosen based voltage rating. Under load transient condition, input capacitor will momentarily supply required transient current. output capacitor linear regulator chosen minimize droop during load transient condition. addition, capacitor chosen based voltage rating.
COUT
COUT COUT
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APW7066
Application Information (Cont.)
Compensation (Cont.) poles zero this transfer function are:
COUT
Comparator VOSC Output Error Amplifier Driver PHASE Driver
FESR
double poles filter, FESR zero introduced output capacitor.
PHASE COUT Output
Figure Modulator compensation circuit shown Figure provide close loop transfer function with highest zero crossover frequency sufficient phase margin. transfer function error amplifier given
Figure Output Filter
-40dB/dec FESR -20dB/dec
COMP GAINAMP
(R1+
poles zeros transfer function are:
Frequency
Figure Filter Gain Frequency modulator shown Figure. input output error amplifier output PHASE node. transfer function modulator given GAINPWM
(R1+
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APW7066
Application Information (Cont.)
Compensation (Cont.)
VOUT
VREF
VCOMP
Figure Compensation Network closed loop gain converter written GAINLC GAINPWM GAINAMP Figure shows asymptotic plot closed loop converter gain following guidelines will help design compensation network. Using below guidelines should give compensation similar curve plotted. stable closed loop -20dB/ decade slope phase margin greater than degree. 1.Choose value uaually between 2.Select desired zero crossover frequency (1/5 1/10) >FO>FESR following equation calculate
5.Set second pole half switching frequency also second zero output filter double pole FLC. compensation gain should exceed error amplifier open loop gain, check compensation gain with capabilities error amplifier. 0.5xFO Combine equations will following component calculations: 2xFLC
Open Loop Error Gain Gain FZ1=0.75FLC FP1=FESR FZ2=FLC 20log (R2/R1) FP2=0.5FS
FESR Filter Gain
20log (VIN VOSC) Compensation Gain
Converter Gain Frequency
3.Place first zero before output filter double pole frequency FLC. 0.75 Calculate equation:
0.75
Figure Converter Gain Frequency Output Inductor Selection inductor value determines inductor ripple current affects load transient response. Higher inductor value reduces inductor' ripple current induces lower output ripple voltage. ripple current ripple voltage approximated
IRIPPLE VOUT VOUT
4.Set pole zero frequency FESR: FESR Calculate equation:
FESR
VOUT IRIPPLE
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APW7066
Application Information (Cont.)
Output Inductor Selection (Cont.) where switching frequency regulator. Although increase inductor value frequency reduce ripple current voltage, there tradeoff exists between inductor' ripple current regulator load transient response time. smaller inductor will give regulator faster load transient response expense higher ripple current. Increasing switching frequency (FS) also reduces ripple current voltage, will increase switching loss MOSFET power dissipation converter. maximum ripple current occurs maximum input voltage. good starting point choose ripple current approximately maximum output current. Once inductance value been chosen, select inductor that capable carrying required peak current without going into saturation. some types inductors, especially core that made ferrite, ripple current will increase abruptly when saturates. This will result larger output ripple voltage. Output Capacitor Selection Higher Capacitor value lower reduce output ripple load transient drop. Therefore select high performance capacitors that intended switching regulator applications. some applications, multiple capacitors have parallel achieve desired value. small decoupling capacitor parallel bypassing noise also recommended, voltage rating output capacitors also must considered. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. Input Capacitor Selection input capacitor chosen based voltage
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rating current rating. reliable operation, select capacitor voltage rating least times higher than maximum input voltage. maximum current rating requirement approximately IOUT/2, where IOUT load current. During power input capacitors have handle large amount surge current. tantalum capacitors used, make sure they surge tested manufactures. doubt, consult capacitors manufacturer. high frequency decoupling, ceramic capacitor connected between drain upper MOSFET source lower MOSFET. MOSFET Selection selection N-channel power MOSFETs determined RDS(ON), reverse transfer capacitance (CRSS) maximum output current requirement.The losses MOSFETs have components: conduction loss transition loss. upper lower MOSFET, losses approximately given following PUPPER Iout TC)(RDS(ON))D (0.5)(Iout)(VIN)(tsw)FS PLOWER Iout TC)(RDS(ON))(1-D) where IOUT load current temperature dependency RDS(ON) switching frequency switching interval duty cycle Note that both MOSFETs have conduction losses while upper MOSFET include additional transition loss.The switching internal, tsw, function reverse transfer capacitance CRSS. (1+TC) term factor temperature dependency RDS(ON) extracted from "RDS(ON) Temperature" curve power MOSFET.
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APW7066
Application Information (Cont.)
Connecting Input from Another Output connected outputs input voltage 2nd. these cases output current first output includes load current output' load current. Therefore, components first output must designed sized both outputs. soft-start first output must faster than output. first output present when output tries start output cannot smooth controlled output voltage rise,
even cause short-circuit protection.
short; COMP will have sharp rise. However, current rises fast, cause false trip. output capacitance affect rising time current during short. Layout Considerations high power switching regulator, correct layout important ensure proper operation regulator. general, interconnecting impedances should minimized using short, wide printed circuit traces. Signal power grounds kept separate finally combined using ground plane construction single point grounding. Figure illustrates layout, with bold lines indicating high current paths; these traces must short wide. Components along bold lines should placed lose together. Below checklist your layout
Short Circuit Protection 7066 prov ides simple short circuit protection function, easy predict performance, since many factors affect well works. Therefore, limitations suggestions this method must provided users understand work well.
metal plate bottom packages
(TSSOP-24 QFN-32) must soldered connected plane backside through several thermal vias.
short circuit protection designed
work output initial short condition. this case, short circuit protection work, damage MOSFETs. circuit still works, remove short cause inductive kick phase pin, damage MOSFETs.
Keep switching nodes (UGATE, LGATE
PHASE) away from sensitive small signal nodes since these nodes fast moving signals. Therefore, keep traces these nodes short possible.
resistance short enough
cause protection, regulator will work load increased, continue regulate until MOSFETs damaged. resistance short should include wiring, traces, contact resistances, return paths.
traces from gate drivers MOSFETs
(UG1, LG1, UG2, LG2, DRIVE3) should short wide.
Decoupling capacitor, compensation component,
resistor dividers, boot capacitors, capacitors should close their pins.
higher duty cycle will give higher COMP
voltage level, easy touch trip point. compensation components also affect response COMP voltage; smaller caps give faster response.
input capacitor should near drain
upper MOSFET; output capacitor should near loads. input capacitor should close output capacitor lower MOSFET GND.
output current faster rising time during
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drain MOSFETs (VIN phase nodes)
should large plane heat sinking.
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APW7066
Application Information (Cont.)
APW7066 BOOT REFOUT VREF BOOT PGND VCC12 CVCC12 REFOUT VREF COUT VOUT
Figure Layout Guidelines
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APW7066
Packaging Information
TSSOP/ TSSOP-P (Reference JEDEC Registration MO-153)
GAUGE PLANE
EXPOSED THERMAL ZONE
0.25
(L1)
BOTTOM VIEW
(THERMALLY ENHANCED VARIATIONDS ONLY)
Millimeters Max. 0.00 0.15 0.80 1.05 0.19 0.30 (N=20PIN) (N=20PIN) (N=24PIN) (N=24PIN) (N=28PIN) (N=28PIN) (N=20PIN) (N=24PIN) (N=28PIN) 0.65 6.40 4.30 4.50 (N=20PIN) (N=24PIN) (N=28PIN) 0.45 0.75 0.09 0.09
Inches Max. 0.047 0.000 0.006 0.031 0.041 0.007 0.012 0.260 (N=20PIN) 0.252 (N=20PIN) 0.303 (N=24PIN) 0.311 (N=24PIN) 0.378 (N=28PIN) 0.386 (N=28PIN) 0.165 (N=20PIN) 0.188 (N=24PIN) 0.150 (N=28PIN) 0.026 0.252 0.169 0.177 0.118 (N=20PIN) 0.127 (N=24PIN) 0.110 (N=28PIN) 0.018 0.030 0.039REF 0.004 0.004 0.008
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Min.
Min.
Rev. Jun., 2005
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APW7066
Packaging Information
QFN-32
Millimeters Min. 0.00 0.20 REF. 4.90 4.90 0.18 3.50 3.50 0.500 0.35 0.45 0.014 5.10 5.10 0.28 3.60 3.60 0.192 0.192 0.007 0.138 0.138 Max. 0.84 0.04 Min. 0.00
Inches Max. 0.033 0.0015 0.008 REF. 0.200 0.200 0.011 0.142 0.142 0.020 0.018
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APW7066
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material 90/10 63/37 SnPb), 100%Sn Meets Specification RSI86-91, ANSI/J-STD-002 Category
Reflow Condition
(IR/Convection Reflow)
Critical Zone
Ramp-up
Temperature
Tsmax
Tsmin Ramp-down Preheat
Peak
Time
Classification Reflow Profiles
Profile Feature Average ramp-up rate Preheat Temperature (Tsmin) Temperature (Tsmax) Time (min max) (ts) Time maintained above: Temperature (TL) Time (tL) Peak/Classificatioon Temperature (Tp) Time within actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds table 10-30 seconds Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds table 20-40 seconds
6°C/second max. 6°C/second max. minutes max. minutes max. Time 25°C Peak Temperature Notes: temperatures refer topside package .Measured body surface. (mm)
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APW7066
Classification Reflow Profiles(Cont.)
Table SnPb Entectic Process Package Peak Reflow Temperature Package Thickness Volume Volume <350 <2.5 +0/-5°C +0/-5°C +0/-5°C +0/-5°C
Table Pb-free Process Package Classification Reflow Temperatures Package Thickness Volume Volume Volume <350 350-2000 >2000 <1.6 +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* *Tolerance: device manufacturer/supplier shall assure process compatibility including stated classification temperature (this means Peak reflow temperature +0°C. example 260°C+0°C) rated level.
Reliability Test Program
Test item SOLDERABILITY HOLT Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD Description 245°C, 1000 Bias @125°C Hrs, 100%RH, 121°C -65°C~150°C, Cycles VHBM 2KV, 200V 10ms, 100mA
Carrier Tape Reel Dimensions
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APW7066
Carrier Tape Reel Dimensions(Cont.)
Application
+0.1
±0.5
±0.5 ±0.1
16.4 ±0.2 ±0.1
±0.2 ±0.1
±0.3 ±0.1
±0.1 ±0.1
1.75±0.1 0.3±0.05
TSSOP-
±0.1
(mm)
Shipping Tray
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APW7066
Shipping Tray(Cont.)
Cover Tape Dimensions
Application TSSOP- Carrier Width Cover Tape Width 21.3 Devices Reel 2000
Customer Service
Anpec Electronics Corp. Head Office Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. 886-3-5642000 886-3-5642050 Taipei Branch 137, Lane 235, Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, 886-2-89191368 886-2-89191369
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