Stereo 2.7-W Audio Power Amplifier (with DC_Volume Control) Opera
|
|
|
Top Searches for this datasheet
APA2065
Stereo 2.7-W Audio Power Amplifier (with DC_Volume Control)
Operating Current with 14mA Improved Depop Circuitry Eliminate Turn-on Turn-off Transients Outputs High PSRR Steps Volume Adjustable Voltage with Hysteresis Channel Output Power into Load Mode Output Modes Allowable with Modes Selected SE/BTL Current Consumption Shutdown Mode (50µA) Short Circuit Protection Power Depop Circuit Integration PDIP-16 SOP-16 Packages Available Lead Free Available (RoHS Compliant)
General Description
APA2065 monolithic integrated circuit, which provides precise volume control, stereo bridged audio power amplifiers capable producing 2.7W(2.0W) into with less than 10%(1.0%) THD+N. attenuator range volume control APA2065 from 20dB (DC_Vol=0V) -80dB (DC_Vol=3.54V) with steps. advantage internal gain setting less components area. Both depop circuitry thermal shutdown protection circuitry integrated APA2065, that reduce pops clicks noise during power shutdown mode operation. also improves power noise protects chip from being destroyed over temperature short current failure. simplify audio system design, APA2065 combines stereo bridge-tied loads (BTL) mode speaker drive stereo single-end (SE) mode headphone drive into single chip, where both modes easily switched SE/BTL input control signal.
Applications
NoteBook Monitor
ANPEC reserves right make changes improve reliability manufacturability without notice, advise customers obtain latest version relevant information verify before placing orders. Copyright ANPEC Electronics Corp. Rev. Aug., 2005 www.anpec.com.tw
APA2065
Ordering Marking Information
APA2065
Lead Free Code Handling Code Temp. Range Package Code APA2065 APA2065 APA2065 XXXXX APA2065 XXXXX Package Code PDIP-16 SOP-16 Temp. Range Handling Code Tube Tape Reel Tray Lead Free Code Lead Free Device Blank Original Device XXXXX Date Code XXXXX Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials 100% matte plate termination finish; which fully compliant with RoHS compatible with both SnPb lead-free soldiering operations. ANPEC lead-free products meet exceed lead-free requirements IPC/JEDEC STD-020C classification lead-free peak reflow temperature.
Block Diagram
LOUT+ LIN-
RINVolume Control
LOUT-
BYPASS
BYPASS
ROUT+ VOLUME
SE/BTL
SE/BTL
ROUTSHUTDOWN
Shutdown Depop circuit
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol TSTG VESD
Note: 1.APA2065 integrated internal thermal shutdown protection when junction temperature ramp 150°C 2.Human body model: C=100pF, R=1500, positives pulse plus negative pulses 3.Machine model: C=200pF, L=0.5µF, positive pulses plus negative pulses
Parameter Supply Voltage Range Input Voltage Range, SE/BTL, SHUTDOWN Operating Ambient Temperature Range Maximum Junction Temperature Storage Temperature Range Soldering Temperature,10 seconds Electrostatic Discharge Power Dissipation
Rating -0.3 -0.3 VDD+0.3 Intermal Limited* +150 -3000 3000*2 -200 200*3 Intermal Limited
Unit
Recommended Operating Conditions
Min. Supply Voltage, High level threshold voltage, level threshold voltage, Common mode input voltage, VICM SHUTDOWN SE/BTL SHUTDOWN SE/BTL VDD-1.0 Max. Unit
Thermal Characteristics
Symbol THJA Parameter Thermal Resistance from Junction Ambient Free PDIP-16 SOP-16 Value Unit
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Electrical Characteristics
VDD=5V, -20°C<TA<85°C (unless otherwise noted)
Symbol Parameter Supply Voltage Supply Current Supply Current Shutdown Mode High input Current Input Current Output Differential Voltage SE/BTL=0V SE/BTL=5V SE/BTL=5V SHUTDOWN=0V Test Condition APA2065 Min. Typ. Max. Unit
Operating Characteristics, mode VDD=5V,TA=25°C,RL=4, Gain=2V/V (unless otherwise noted)
Symbol Parameter Test Condition THD=10%, RL=3, Fin=1kHz THD=10%, RL=4, Fin=1kHz THD=10%, RL=8, Fin=1kHz THD=1%, RL=3, Fin=1kHz THD=1%, RL=4, Fin=1kHz THD=0.5%, RL=8, Fin=1kHz PO=1.5W, RL=4, Fin=1kHz PO=1W, RL=8, Fin=1kHz VIN=0.1Vrms, RL=8, CB=1µF, Fin=120Hz CB=1µF, RL=8, Fin=1kHz PO=1.1W, RL=8, A_wieght APA2065 Unit Min. Typ. Max. 0.05 0.07
Maximum Output Power
THD+N Total Harmonic Distortion Plus Noise PSRR Power Ripple Rejection Ratio Xtalk Channel Separation Signal Noise Ratio
Operating Characteristics, mode VDD=5V,TA=25°C,RL=4, Gain=1V/V (unless otherwise noted)
Symbol Parameter Test Condition THD=10%, RL=8, Fin=1kHz THD=10%, RL=32, Fin=1kHz THD=1%, RL=8, Fin=1kHz THD=1%, RL=32, Fin=1kHz PO=250mW, RL=8, Fin=1kHz PO=75mW, RL=32, Fin=1kHz VIN=0.1Vrms, RL=8, CB=1µF, Fin=120Hz CB=1µF, RL=32, Fin=1kHz PO=75mW, RL=32, A_wieght
Maximum Output Power
THD+N Total Harmonic Distortion Plus Noise PSRR Power Ripple Rejection Ratio Xtalk Channel Separation Signal Noise Ratio
APA2065 Unit Min. Typ. Max. 0.08 0.08
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Description
ROUT+ SHUTDOWN RIN- VOLUME LOUT+ LIN- APA2065 PDIP-16
ROUT14 SE/BTL PASS LOUT9
VOLUME LOUT+ LIN- LOUT- BYPASS APA2065 SOP-16
RIN14 SHUTDOWN ROUT+ ROUT10 SE/BTL
Function Description
Name VOLUME LOUT+ LINLOUTBYPASS SE/BTL ROUTVDD ROUT+ SHUTDOWN RINI/P Config. Description Ground connection, Connected thermal pad. Input signal internal volume gain setting. Left channel positive output mode mode. Left channel input terminal Left channel negative output mode high impedance mode. Bias voltage generator Output mode control input, high output mode mode. Right channel negative output mode high impedance mode. Supply voltage internal circuit excepting power amplifier. Right channel positive output mode mode. will into shutdown mode when pull low. Right channel input terminal
Control Input Table
SE/BTL SHUTDOWN Operating mode Shutdown mode
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Typical Application Circuit
0.1µ
100µ
L-Ch input R-Ch input
LOUT+ LIN220
RINVolume Control
LOUT-
Control
Ring
2.2µ
BYPASS
SE/BTL
Sleeve
BYPASS
Headphone Jack
ROUT+ 100k 100k Shutdow Signal SHUTDOWN
Shutdown
VOLUME
220µ
SE/BTL
SE/BTL
ROUT-
Volume Control Table_BTL Mode
Supply Voltage Vdd=5V
Gain(dB) High(V) 0.12 0.23 0.34 0.46 0.57 0.69 0.80 0.91 1.03 1.14 1.25 1.37 1.48 1.59 1.71 Low(V) 0.00 0.17 0.28 0.39 0.51 0.62 0.73 0.84 0.96 1.07 1.18 1.29 1.41 1.52 1.63
Hysteresis(mV)
Recommended Voltage(V) 0.20 0.31 0.43 0.54 0.65 0.77 0.88 0.99 1.10 1.22 1.33 1.44 1.56 1.67
www.anpec.com.tw
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
APA2065
Volume Control Table_BTL Mode (Cont.)
Supply Voltage Vdd=5V
Gain(dB) High(V) 1.82 1.93 2.05 2.16 2.28 2.39 2.50 2.62 2.73 2.84 2.96 3.07 3.18 3.30 3.41 3.52 5.00 Low(V) 1.74 1.85 1.97 2.08 2.19 2.30 2.42 2.53 2.64 2.75 2.87 2.98 3.09 3.20 3.32 3.43 3.54 Hysteresis(mV) Recommended Voltage(V) 1.78 1.89 2.01 2.12 2.23 2.35 2.46 2.57 2.69 2.80 2.91 3.02 3.14 3.25 3.36 3.48
Typical Characteristics
THD+N Frequency
THD+N Output Power
VDD=5V RL=3 AV=2
VDD=5V RL=3 Po=1.75W
THD+N
AV=10 AV=2
THD+N
f=20kHz
f=1kHz
AV=5 f=20Hz
0.01
0.01 100m
Frequency (Hz)
Output Power
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Typical Characteristics
THD+N Frequency
THD+N Output Power
VDD=5V RL=4 AV=2
VDD=5V RL=4 Po=1.5W
THD+N
THD+N
f=20kHz
AV=2 AV=5 AV=10
f=1kHz f=20Hz
0.01
0.01 100m
200m
500m 800m
Frequency
Output Power
THD+N Frequency
THD+N Output Power
VDD=5V RL=8 AV=2
VDD=5V RL=8 Po=1.0W
THD+N
THD+N
f=20kHz
AV=2 AV=5 AV=10
f=1kHz f=20Hz
0.01
0.01
100m
Frequency (Hz)
Output Power
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Typical Characteristics (Cont.)
THD+N Frequency
THD+N Output Power
VDD=5V RL=8 Po=250mW
VDD=5V RL=8 AV=2
THD+N
THD+N
f=20kHz
AV=1 AV=5
f=20Hz AV=2.5 f=1kHz
0.01
0.01
100m
500m
Frequency (Hz)
Output Power
THD+N Frequency
THD+N Output Power
VDD=5V RL=16 Po=100mW
VDD=5V RL=16 AV=1
THD+N
THD+N
f=20Hz
f=20kHz
AV=2
AV=1
AV=2.5
0.01
f=1kHz
0.01
100m
300m
Frequency (Hz)
Output Power
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Typical Characteristics (Cont.)
THD+N Frequency
THD+N Output Power
VDD=5V RL=32 Po=75mW
VDD=5V RL=32 AV=1
f=20kHz
THD+N
AV=2.5 AV=1
THD+N
f=20Hz f=1kHz
AV=5
0.01
0.01
100m
200m
Frequency (Hz)
Output Power
THD+N Frequency
THD+N Output Swing
VDD=5V RL=10 Vo=1VRMS
VDD=5V RL=10 AV=1
THD+N
AV=2.5
AV=1
THD+N
f=20kHz f=1kHz f=20Hz
AV=5
0.01
0.01 100m
500m
Frequency (Hz)
Output Swing (VRMS)
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
Note:Dropout voltage definition:VIN-VOUT when VOUT below value VOUT VIN= VOUT+1V
APA2065
Typical Characteristics (Cont.)
Crosstalk Frequency
Crosstalk Frequency
VDD=5V RL=32 Po=75mW AV=1
VDD=5V RL=8 Po=1.0W AV=2
Crosstalk (dB)
Crosstalk (dB)
R-ch L-ch L-ch R-ch
R-ch L-ch L-ch R-ch
-100
-100
-120
-120
Frequency (Hz)
Frequency (Hz)
Noise Floor Frequency
100u
Noise Floor Frequency
100u AV=1
VDD=5V RL=32
Noise Floor (µVRMS)
Noise Floor (µVRMS)
Filter
A-Weight
Filter
A-Weight
VDD=5V RL=8 AV=2
Frequency (Hz)
Frequency (Hz)
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Typical Characteristics (Cont.)
Noise Floor Frequency
100u
Power Dissipation Output Power
0.18
Power Dissipation
Noise Floor (µVRMS)
VDD=5V RL=10K AV=1
0.16 0.14 0.12 0.08 0.06 0.04 0.02
Filter
RL=8
A-Weight
RL=16
RL=32 VDD=5V AV=1
0.05 0.15 0.25 0.35
Frequency (Hz)
Output Power
Power Dissipation Output Power
17.5
Supply Current Supply Voltage
Power Dissipation
Suuply Current (mA)
RL=3
12.5
RL=4
RL=8
VDD=5V AV=2
Load
Output Power
Supply Voltage
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Typical Characteristics (Cont.)
Output Power Supply Voltage
Output Power Supply Voltage
RL=8 AV=2
RL=32 AV=1
Output Power (mW)
Output Power
THD+N=10%
THD+N=10%
THD+N=1%
THD+N=1%
Supply Voltage
Supply Voltage
Output Power Load Resistance
Output Power Load Resistance
VDD=5V AV=1
VDD=5V AV=2
Output Power
Output Power
THD+N=10%
THD+N=1% THD+N=10%
THD+N=1%
6064
Load Resistance
Load Resistance
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Typical Characteristics (Cont.)
Close Loop Response
Close Loop Response
VDD=5V RL=8 AV=2 CO=330µF
VDD=5V RL=32 AV=1 CO=330µF
Loop Gain (dB)
Loop Gain (dB)
AV=2 AV=5 AV=10
AV=1 AV=2.5 AV=5
Frequency (Hz)
Frequency (Hz)
PSRR Frequency
Ripple Rejection Ratio (dB)
VDD=5V Vin=100mVRMS RL=8 Cbypass=2.2µF
Frequency (Hz)
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Application Descriptions
Operation APA2065 output stage (power amplifier) pairs operational amplifiers internally, allowed different amplifier configurations. Four times output power same conditions. configuration, such used APA2065, also creates second advantage over amplifiers. Since differential outputs, ROUT+, ROUT-, LOUT+, LOUT-, biased half-supply, need voltage exists across load. This eliminates need output coupling capacitor which required single supply, configuration. Single-Ended Operation
OUTOP2
OUT+
Volume Control amplifier output signal
Vbias Circuit
Figure APA2065 internal configuration (each channel) power amplifier' gain setting internal unity-gain input audio signal come from internal volume control amplifier, while second amplifier internally fixed unity-gain, inverting configuration. Figure shows that output connected input OP2, which results output signals with both amplifiers with identical magnitude, phase 180°. Consequently, differential gain each channel (Gain mode). driving load differentially through outputs OUT+ OUT-, amplifier configuration commonly referred bridged mode established. mode operation different from classical single-ended amplifier configuration where side load connected ground. amplifier design distinct advantages over configuration, provides differential drive load, thus doubling output swing specified supply voltage.
Consider single-supply configuration shown Application Circuit. coupling capacitor required block offset voltage from reaching load. These capacitors quite large (approximately 33µF 1000µF) they tend expensive, occupy valuable area, have additional drawback limiting low-frequency performance system (refer Output Coupling Capacitor). rules described still hold with addition following relationship: Cbypass 125k RiCi RLCC Output SE/BTL Operation ability APA2065 easily switch between modes most important costs saving features. This feature eliminates requirement additional headphone amplifier applications where internal stereo speakers driven mode external headphone speakers must accommodated. Internal APA2065, separate amplifiers drive OUT+ OUT- (see Figure SE/BTL input controls operation follower amplifier that drives LOUT- ROUT-. When SE/BTL held low, turn APA2065 mode.
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Application Descriptions (Cont.)
Output SE/BTL Operation (Cont.) When SE/BTL held high, high output impedance state, which configures APA2065 driver from OUT+. reduced approximately one-half mode. Control SE/BTL input logic-level source resistor divider network stereo headphone jack with switch shown Application Circuit. VOLUME input pin. APA2065 volume control consists steps that individually selected variable voltage level VOLUME control pin. range steps, controlled voltage, from 20dB -80dB. Each gain step corresponds specific input voltage range, shown table. minimize effect noise volume control pin, which affect selected gain level, hysteresis clock delay implemented. amount hysteresis corresponds half step width, shown volume control graph.
APA2021volumecontrolcurve Forward Backward
100k SE/BTL
Sleeve Control Ring
Headphone Jack
Figure SE/BTL input selection phonejack plug Figure input SE/BTL operates follows When phonejack plug inserted, resistor disconnected SE/BTL input pulled high enables mode. When input goes high, OUT- amplifier shutdown causing speaker mute. OUT+ amplifier then drives through output capacitor (CC) into headphone jack. When there headphone plugged into system, contact headphone jack connected from
Figure Gain setting VOLUME voltage highest accuracy, voltage shown recommended voltage'column table used select desired gain. This recommended voltage exactly halfway between nearest transitions. gain levels 2dB/step from 20dB -40dB mode, last step -80dB mute mode. Input Resistance, gain each audio input APA2065 internal resistors volume control amplifier inverting configuration.
www.anpec.com.tw
sgnal voltage divider resistors
100k Resistor then pulls SE/BTL pin, enabling function. Volume Control Function APA2065 internal stereo volume control whose setting function voltage applied
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
APA2065
Application Descriptions (Cont.)
Input Resistance, (Cont.) Gain Gain value important consider directly affects frequency performance circuit. Consider example where specification calls flat bass response down 100Hz. Equation reconfigured follow 2x10kxf
mode operation brings factor gain equation inverting amplifier mirroring voltage swing across load. varying gain setting, APA2065 generates each input resistance figure input resistance will affect frequency performance audio signal. minmum input resistance when gain setting 20dB resistance will ramp when close loop gain below 20dB. input resistance wide variation (+/-10%) caused process variation.
Ri(k)
Consider input resistance variation, 0.16µF would likely choose value range 0.22µF 1.0µF. further consideration this capacitor leakage path from input source through input network (Ri+Rf, load. This leakage current creates offset voltage input amplifier that reduces useful headroom, especially high gain applications. this reason low-leakage tantalum ceramic capacitor best choice. When polarized capacitors used, positive side capacitor should face amplifier input most applications level there held VDD/2, which likely higher that source level. Please note that important confirm capacitor polarity application. Effective Bypass Capacitor, Cbypass
Gain(BTL)
Gain(dB)
Figure Input resistance Gain setting Input Capacitor, typical application input capacitor, required allow amplifier bias input signal proper level optimum operation. this case, minimum input impedance (10k) form high-pass filter with corner frequency determined follow equation: FC(highpass)= 2x10kxCi
other power amplifiers, proper supply bypassing critical noise performance high power supply rejection. capacitors located both bypass power supply pins should close device possible. effect larger bypass capacitor will improve PSRR increased supply stability. Typical applications employ regulator with 1.0µF 0.1µF bypass capacitor supply filtering. This does eliminate need bypassing supply nodes APA2065. selection bypass capacitors, especially Cbypass, thus dependent upon desired PSRR requirements, click performance.
www.anpec.com.tw
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
APA2065
Application Descriptions (Cont.)
Effective Bypass Capacitor, Cbypass (Cont.) avoid start-up noise occurred, bypass voltage should rise slower than input bias voltage relationship shown equation should maintained. Cbypass 125k 100k bypass capacitor thru from 125k resistor inside amplifier 100k maximum input resistance (Ri+ Rf). Bypass capacitor, values 3.3µF 10µF ceramic tantalum low-ESR capacitors recommended best noise performance. bypass capacitance also effects start time. determined following equation: Tstart (Cbypass 125K) Output Coupling Capacitor, typical single-supply configuration, output coupling capacitor (Cc) required block bias output amplifier thus preventing currents load. with input coupling capacitor, output coupling capacitor impedance load form high-pass filter governed equation. FC(highpass)= 2RLCC power amplifier only used volume control amplifier internal circuit excepting power amplifier. APA2065 high-performance CMOS audio amplifier that requires adequate power supply decoupling ensure output total harmonic distortion (THD) possible. Power supply decoupling also prevents oscillations causing long lead length between amplifier speaker. optimum decoupling achieved using different type capacitors that target different type noise power supply leads. higher frequency transients, spikes, digital hash line, good equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF placed close possible device lead works best. filtering lower-frequency noise signals, large aluminum electrolytic capacitor 10µF greater placed near audio power amplifier recommended. Optimizing Depop Circuitry Circuitry been included APA2065 minimize amount popping noise power-up when coming shutdown mode. Popping occurs whenever voltage step applied speaker. order eliminate clicks pops, capacitors must fully discharged before turn-on. Rapid on/off switching device shutdown function will cause click circuitry. value will also affect turn-on pops (Refer Effective Bypass Capacitance). bypass voltage ramp should slower than input bias voltage. Although bypass current source cannot modified, size Cbypass changed alter device turn-on time amount clicks pops. increasing value Cbypass, turn-on reduced. However, tradeoff using larger bypass capacitor increase turn-on time this device. There linear relationship between
www.anpec.com.tw
example, 330µF capacitor with speaker would attenuate frequencies below 60.6Hz.The main disadvantage, from performance standpoint, load impedance typically small, which drives low-frequency corner higher degrading bass response. Large values required pass frequencies into load. Power Supply Decoupling, APA2065 provides independent power inputs right channel left channel used. PVDD used
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
APA2065
Application Descriptions (Cont.)
Optimizing Depop Circuitry (Cont.) size Cbypass turn-on time. configuration, output coupling capacitor, particular concern. This capacitor discharges through internal resistors. Depending size time constant relatively large. reduce transients mode, external resistor placed parallel with internal resistor. tradeoff using this resistor increase quiescent current. most cases, choosing small value range 0.33µF 1µF, being equal 4.7µF external resistor should placed parallel with internal resistor should produce virtually clickless popless turn-on. high gain amplifier intensifies problem small delta voltage multiplied gain. advantageous low-gain configurations. Shutdown Function order reduce power consumption while use, APA2065 contains shutdown externally turn amplifier bias circuitry. This shutdown feature turns amplifier when logic placed SHUTDOWN pin. trigger point between logic high logic level typically 2.0V. best switch between ground supply provide maximum device performance. switching SHUTDOWN low, amplifier enters low-current state, DD<50µA. normal operating, SHUTDOWN pull high level keeping shutdown mode. SHUTDOWN should tied definite voltage avoid unwanted state changes. Clock Generator APA2065 integrates clock block 130kHz avoid volume control function abnormal when VOLUME control signal with spike noise. APA2065 changes each step volume gain after four clock cycles make sure control signal ready. Amplifier Efficiency easy-to-use equation calculate efficiency starts being equal ratio power from power supply power delivered load. following equations basis calculating amplifier efficiency. Efficiency Where VORMS VORMS VPxVP VORMS (10) (11) PSUP
PSUP IDDAVG Efficiency configuration VPxVP (VDD 4VDD PSUP
(12)
Note that efficiency amplifier quite lower power levels rises sharply power load increased resulting nearly flat internal power dissipation over normal operating range. Note that internal dissipation full output power less than half power range. Calculating efficiency specific system proper power supply design. stereo audio system with loads supply, maximum draw power supply almost final point remember about linear amplifiers (either BTL) manipulate terms efficiency equation utmost advantage when possible. Note that equation,
www.anpec.com.tw
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
APA2065
Application Descriptions (Cont.)
Amplifier Efficiency (Cont.) denominator. This indicates that goes down, efficiency goes other words, efficiency analysis choose correct supply voltage speaker impedance application.
Efficiency IDD(A) VPP(V) 0.25 0.50 1.00 1.25 31.25 47.62 66.67 78.13 0.16 0.21 0.30 0.32 2.00 2.83 4.00 4.47 0.55 0.55 0.35
assuming 5V-power supply load, must greater than power dissipation that results from equation15: PD,MAX= TJ,MAX (15)
DIP-16 package with thermal pad, thermal resistance (JA) equal 45C/W. Since maximum junction temperature (TJ,MAX) APA2065 150C ambient temperature (TA) defined power system design, maximum power dissipation which package able handle obtained from equation15. Once power dissipation greater than maximum limit (PD,MAX), either supply voltage (VDD) must decreased, load impedance (RL) must increased ambient temperature should reduced.
**High peak voltages cause increase. Table Efficiency Output Power 5-V/8 Systems Power Dissipation Whether power amplifier operated modes, power dissipation major concern. equation13 states maximum power dissipation point mode operating given supply voltage driving specified load. VDD2 (13) mode PD,MAX= mode operation, output voltage swing doubled mode. Thus maximum power dissipation point mode operating same given conditions times mode. mode PD,MAX= 4VDD2 22RL (14)
Since APA2065 dual channel power amplifier, maximum internal power dissipation times that both equations depending mode operation. Even with this substantial increase power dissipation, APA2065 does require extra heatsink. power dissipation from equation14,
Copyright ANPEC Electronics Corp. Rev. Aug., 2005 www.anpec.com.tw
APA2065
Packaging Information
PDIP-16 Reference JEDEC Registration MS-001)
Millimeters Min. 0.38 3.17 2.92 0.36 1.14 0.76 0.20 18.632 7.605BSC 6.223 2.54BSC 8.492 1.397 0.58 9.506 1.651 0.84
Inches
Rev. Aug., 2005
Max. 5.32 3.42 3.80 0.56 1.78 1.14 0.36 19.646 6.477
Min. 0.015 0.125 0.115 0.014 0.045 0.030 0.008 0.735 0.300BSC 0.245 0.100BSC 0.335 0.055 0.023
Max. 0.210 0.135 0.150 0.022 0.070 0.045 0.014 0.775 0.255 0.375 0.065 0.033
www.anpec.com.tw
Copyright ANPEC Electronics Corp.
APA2065
Package Information
300mil Reference JEDEC Registration MS-013)
GAUGE PLANE
Millimeters Min. 2.35 0.10 0.33 Max. 2.65 0.30 0.51
Variations- Variations SO-16 SO-18 SO-20 SO-24 SO-28 SO-14 Min. 10.10 11.35 12.60 15.20 17.70 8.80 Max. 10.50 11.76 15.60 18.11 9.20
Inches Min. 0.093 0.004 0.013 Max. 0.1043 0.0120 0.020
Variations- Variations SO-16 SO-18 SO-20 SO-24 SO-28 SO-14 Min. 0.398 0.447 0.496 0.599 0.697 0.347 Max. 0.413 0.463 0.512 0.614 0.713 0.362
variations 7.40 7.60
variations 0.2914 0.2992
1.27BSC 0.40 10.65 1.27
0.050BSC 0.394 0.016 0.419 0.050
variations
variations
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material 90/10 63/37 SnPb), 100%Sn Meets Specification RSI86-91, ANSI/J-STD-002 Category
Reflow Condition
(IR/Convection Reflow)
Ramp-up
Critical Zone
Temperature
Tsmax
Tsmin Ramp-down Preheat
Peak
Time
Classificatin Reflow Profiles
Profile Feature Average ramp-up rate Preheat Temperature (Tsmin) Temperature (Tsmax) Time (min max) (ts) Time maintained above: Temperature Time (tL) Peak/Classificatioon Temperature (Tp) Time within actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds table 10-30 seconds Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds table 20-40 seconds
6°C/second max. 6°C/second max. minutes max. minutes max. Time 25°C Peak Temperature Notes: temperatures refer topside package .Measured body surface.
www.anpec.com.tw
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
APA2065
Classificatin Reflow Profiles(Cont.)
Table SnPb Entectic Process Package Peak Reflow Temperature Package Thickness Volume Volume <350 <2.5 +0/-5°C +0/-5°C +0/-5°C +0/-5°C
Table Pb-free Process Package Classification Reflow Temperatures Package Thickness Volume Volume Volume <350 350-2000 >2000 <1.6 +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* *Tolerance: device manufacturer/supplier shall assure process compatibility including stated classification temperature (this means Peak reflow temperature +0°C. example 260°C+0°C) rated level.
Reliability Test Program
Test item SOLDERABILITY HOLT Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD Description 245°C, 1000 Bias @125°C Hrs, 100%RH, 121°C -65°C~150°C, Cycles VHBM 2KV, 200V 10ms, 100mA
Carrier Tape Reel Dimensions
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
APA2065
Carrier Tape Reel Dimensions(Cont.)
Application
+0.1
16.4 +0.3 -0.2
1.75±0.1
SOP-
7.5±
1.5+ 0.25
10.9 10.8± 3.0± 0.3±0.013
(mm)
Cover Tape Dimensions
Application SOP- Carrier Width Cover Tape Width 21.3 Devices Reel 1000
Customer Service
Anpec Electronics Corp. Head Office Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. 886-3-5642000 886-3-5642050 Taipei Branch 137, Lane 235, Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, 886-2-89191368 886-2-89191369
Copyright ANPEC Electronics Corp. Rev. Aug., 2005
www.anpec.com.tw
Other recent searches
MAX5486 - MAX5486 MAX5486 Datasheet
MAX5486 - MAX5486 MAX5486 Datasheet
IRF840 - IRF840 IRF840 Datasheet
CSD17313Q2 - CSD17313Q2 CSD17313Q2 Datasheet
AO-10 - AO-10 AO-10 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
